CN113949477B - Synchronization method of clock signals with different frequencies - Google Patents
Synchronization method of clock signals with different frequencies Download PDFInfo
- Publication number
- CN113949477B CN113949477B CN202111565516.7A CN202111565516A CN113949477B CN 113949477 B CN113949477 B CN 113949477B CN 202111565516 A CN202111565516 A CN 202111565516A CN 113949477 B CN113949477 B CN 113949477B
- Authority
- CN
- China
- Prior art keywords
- pulse signal
- npps
- module
- period
- mpp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0617—Systems characterised by the synchronising information used the synchronising signal being characterised by the frequency or phase
Abstract
The invention discloses a synchronization method of clock signals with different frequencies, which comprises the following steps: the first module generates an nPPS pulse signal with a period of n seconds; carrying out frequency multiplication on the nPPS pulse signal to obtain a first mPP pulse signal with the period of m seconds; triggering the register of a counter of a second module to be cleared by utilizing the rising edge of the first mPP pulse signal; the second module generates a second mPP pulse signal with the period of m seconds in a counting frequency division mode; wherein m and n are both greater than 0, and n is greater than m. The invention realizes the rapid synchronization of the slow clock signal and the fast clock signal, shortens the time spent for one time of synchronization, is used for the production of actual projects at present and obtains better economic benefit.
Description
Technical Field
The invention relates to the technical field of clock signal synchronization, in particular to a synchronization method of clock signals with different frequencies.
Background
The problem of synchronization of an arbitrary-period N-second pulse and a local 1-second-period pulse is often encountered in the technical field of time unification, and N seconds are needed for each synchronization. If the period N of any periodic N-second pulse is relatively long, e.g. tens of seconds, minutes, then tens of seconds, or even minutes, are required for each synchronization. For many application scenarios, the frequency of signal synchronization is too low (i.e., each synchronization takes too long) to be acceptable.
Disclosure of Invention
The present invention is directed to overcoming one or more of the disadvantages of the prior art and providing a method for synchronizing clock signals of different frequencies.
The purpose of the invention is realized by the following technical scheme: a method of synchronizing clock signals of different frequencies, comprising:
the first module generates an nPPS pulse signal with a period of n seconds;
carrying out frequency multiplication on the nPPS pulse signal to obtain a first mPP pulse signal with the period of m seconds;
triggering the register of a counter of a second module to be cleared by utilizing the rising edge of the first mPP pulse signal;
the second module generates a second mPP pulse signal with the period of m seconds in a counting frequency division mode;
wherein m and n are both greater than 0, and n is greater than m.
Preferably, the nPPS pulse signal is a narrow pulse signal.
Preferably, the frequency doubling the nPPS pulse signal to obtain a first mPPS pulse signal with a period of m seconds, includes:
the second module acquires the period of the nPPS pulse signal;
and the second module carries out n/m frequency multiplication on the nPPS pulse signal to obtain a first mPPS pulse signal with the period of m.
Preferably, the second module acquires the period of the nPPS pulse signal, and includes:
writing the period of the nPPS pulse signal into a register inside a second module through a serial port;
the second module reads its register to obtain the period of the nPPS pulse signal.
Preferably, the second module performs n/m frequency multiplication on the nPPS pulse signal in a manner that:
and the second module carries out n/m times of phase-locked loop frequency multiplication on the nPPS pulse signal.
Preferably, the second module is a programmable logic, and the programmable logic calls an IP core thereof to find the phase-locked loop frequency multiplication of the nPPS pulse signal.
Preferably, triggering the register of the counter of the second module to be cleared by using the rising edge of the first mPPS pulse signal includes:
and adding a first code description to a counter of the second module, wherein the first code description triggers the counter to register and clear for the rising edge of the first mPP pulse signal.
Preferably, the first module is an embedded software system.
Preferably, the second module is programmable logic.
The invention has the beneficial effects that: the invention realizes the rapid synchronization of the slow clock signal and the fast clock signal, shortens the time spent for one time of synchronization, is used for the production of actual projects at present and obtains better economic benefit.
Drawings
FIG. 1 is a flow chart of a method for synchronizing clock signals of different frequencies.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the following embodiments, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.
Referring to fig. 1, the present embodiment provides a method for synchronizing clock signals with different frequencies:
as shown in fig. 1, a method for synchronizing clock signals with different frequencies includes:
s1, a first module generates an nPPS pulse signal with a period of n seconds, wherein n is greater than 0.
The nPPS pulse signal having a period of n seconds in this embodiment is a pulse signal output every n seconds. Generally, the time information source and the generation mode of the nPPS pulse signal are not required; in some embodiments, the nPPS pulse signal is a narrow pulse signal, which is generally understood to be a signal with a positive pulse width duty cycle of less than 10%, and may be defined otherwise.
And S2, carrying out frequency multiplication on the nPPS pulse signal to obtain a first mPPS pulse signal with a period of m seconds, wherein m is more than 0, and n is more than m. The values of m and n need to ensure that the nPPS pulse signal and the first mPPS pulse signal can obtain the same frequency after integral multiple frequency multiplication or frequency division. For example, the frequency of the nPPS pulse signal is 6.4MHz, the frequency of the first mPPS pulse signal is 10MHz, and then 10MHz can be multiplied by 64 to 640MHz, and 6.4MHz can be multiplied by 100 to 640 MHz.
The nPPS pulse signal having a period of m seconds in this embodiment is a pulse signal output every m seconds. Since n > m, the frequency of the nPPS pulse signal is lower than the frequency of the first and second mPPS pulse signals, and the nPPS pulse signal is a slow clock (low frequency) signal compared to the first and second mPPS pulse signals.
In some embodiments, frequency doubling the nPPS pulse signal to obtain a first mPPS pulse signal with a period of m seconds includes:
and S21, the second module acquires the period of the nPPS pulse signal.
The second module obtains the period of the nPPS pulse signal, including: writing the period of the nPPS pulse signal into a register inside a second module through a serial port; the second module reads its register to obtain the period of the nPPS pulse signal. For example, the period of the nPPS pulse signal is written to a register inside the second module through the SPI interface.
It should be noted that the second module may also obtain the period of the nPPS pulse signal in other manners besides the above-mentioned manner.
And S22, the second module carries out n/m frequency multiplication on the nPPS pulse signal to obtain a first mPPS pulse signal with the period of m.
In some embodiments, the second module multiplies the nPPS pulse signal by n/m in a manner that: the second module performs n/m times phase-locked loop frequency multiplication (PLL frequency multiplication) on the nPPS pulse signal. For example, when the second module is programmable logic, the programmable logic invokes its IP core to find a phase-locked loop multiple of the nPPS pulse signal. Therefore, the value of n is limited by the performance of a specific chip, and the frequency doubling range of which multiple can be determined according to actual conditions.
It should be noted that the second module may also perform n/m frequency multiplication on the nPPS pulse signal in other manners besides the above manner.
And S3, triggering the register of a counter of the second module to be cleared by utilizing the rising edge of the first mPP pulse signal.
For example, a logic code description of "the rising edge of the first mPPS pulse signal triggers the counter to register clear" is added to the counter of the second module.
And S4, the second module generates a second mPP pulse signal with the period of m seconds in a counting frequency division mode.
The rising edge of the first mPP pulse signal is used for triggering the register of a counter of the second module to be cleared, and the second module generates a second mPP pulse signal with the period of m seconds in a counting frequency division mode, so that the second mPP pulse signal is synchronous with the first mPP pulse signal; furthermore, since the first mPPS pulse signal generated by frequency multiplication of the nPPS pulse signal is synchronized with the nPPS pulse signal, the second mPPS pulse signal is also synchronized with the nPPS pulse signal. If frequency multiplication is not carried out, n seconds are needed for each synchronization, and only m seconds are needed for each synchronization by adopting the method of the embodiment, so that the time spent for one synchronization is shortened.
In some embodiments, the first module is an embedded software system and/or the second module is programmable logic.
The method of this embodiment is illustrated below, where the width of the nPPS pulse signal is 100ms, the value of n is 16 (that is, the period of the nPPS pulse signal is 16 seconds), the value of m is 1 (that is, the period of the first mPPS pulse signal is 16 seconds), the first module is an embedded software system, and the second module is programmable logic.
The embedded software system generates an nPPS pulse signal with the period of 16 seconds; the embedded software system writes the period of the nPPS pulse signal into a register in the programmable logic through the serial port within 16 seconds, and the programmable logic reads the register to obtain the period of the nPPS pulse signal written through the serial port.
The programmable logic carries out 16 times PLL frequency multiplication on the nPPS pulse signal given by the embedded software system to generate a synchronous enabling signal, namely the first mPP pulse signal, wherein the period of the first mPP pulse signal is 1 second.
The programmable logic generates a second mPP pulse signal in a counting and frequency dividing mode, the period of the second mPP pulse signal is 1 second, and a logic code description of 'the rising edge of the first mPP pulse signal triggers the register of the counter to be cleared' is added to a counter of the programmable logic, so that the second mPP pulse signal is synchronous with the first mPP pulse signal, and the second mPP pulse signal is synchronous with the npPS pulse signal. And finally, outputting the second mPP pulse signal to the outside through a proper line.
In the above example, if frequency doubling is not performed, 16 seconds are required for each synchronization, and with the method of the present embodiment, only 1 second is required for each synchronization, which shortens the time required for each synchronization.
The foregoing is illustrative of the preferred embodiments of this invention, and it is to be understood that the invention is not limited to the precise form disclosed herein and that various other combinations, modifications, and environments may be resorted to, falling within the scope of the concept as disclosed herein, either as described above or as apparent to those skilled in the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. A method for synchronizing clock signals of different frequencies, comprising:
the first module generates an nPPS pulse signal with a period of n seconds;
carrying out frequency multiplication on the nPPS pulse signal to obtain a first mPP pulse signal with the period of m seconds;
triggering the register of a counter of a second module to be cleared by utilizing the rising edge of the first mPP pulse signal;
the second module generates a second mPP pulse signal with the period of m seconds in a counting frequency division mode;
wherein m and n are both greater than 0, n is greater than m, and the values of m and n ensure that the same frequency can be obtained after integral multiple frequency multiplication or frequency division is carried out on the nPPS pulse signal and the first mPPS pulse signal;
frequency multiplication is carried out on the nPPS pulse signal to obtain a first mPP pulse signal with a period of m seconds, and the method comprises the following steps:
the second module acquires the period of the nPPS pulse signal;
and the second module carries out n/m frequency multiplication on the nPPS pulse signal to obtain a first mPPS pulse signal with the period of m.
2. The method of claim 1, wherein the nPPS pulse signal is a narrow pulse signal.
3. The method of claim 1, wherein the second module obtains the period of the nPPS pulse signal, and comprises:
writing the period of the nPPS pulse signal into a register inside a second module through a serial port;
the second module reads its register to obtain the period of the nPPS pulse signal.
4. The method according to claim 1, wherein the second module multiplies the nPPS pulse signal by n/m in a manner that:
and the second module carries out n/m times of phase-locked loop frequency multiplication on the nPPS pulse signal.
5. The method of claim 4, wherein said second module is programmable logic that invokes its IP core to effect a PLL multiplication of said nPPS pulse signal.
6. The method for synchronizing clock signals with different frequencies according to claim 1, wherein triggering the counter of the second module to register zero by using the rising edge of the first mPPS pulse signal comprises:
and adding a first code description to a counter of the second module, wherein the first code description triggers the counter to register and clear for the rising edge of the first mPP pulse signal.
7. The method according to claim 1, wherein the first module is an embedded software system.
8. The method of claim 1, wherein the second module is programmable logic.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111565516.7A CN113949477B (en) | 2021-12-21 | 2021-12-21 | Synchronization method of clock signals with different frequencies |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111565516.7A CN113949477B (en) | 2021-12-21 | 2021-12-21 | Synchronization method of clock signals with different frequencies |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113949477A CN113949477A (en) | 2022-01-18 |
| CN113949477B true CN113949477B (en) | 2022-03-04 |
Family
ID=79339360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111565516.7A Active CN113949477B (en) | 2021-12-21 | 2021-12-21 | Synchronization method of clock signals with different frequencies |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113949477B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101873187A (en) * | 2010-05-25 | 2010-10-27 | 中兴通讯股份有限公司 | Method and system of clock synchronization |
| CN106027187A (en) * | 2016-04-29 | 2016-10-12 | 国家电网公司 | GPS (Global Positioning System) synchronizing signal frequency source circuit |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5107264A (en) * | 1990-09-26 | 1992-04-21 | International Business Machines Corporation | Digital frequency multiplication and data serialization circuits |
| US6049238A (en) * | 1998-05-12 | 2000-04-11 | Mitsubishi Denki Kabushiki Kaisha | Clock generator and clock generating method capable of varying clock frequency without increasing the number of delay elements |
| CN1202620C (en) * | 2002-03-29 | 2005-05-18 | 扬智电子（上海）有限公司 | Method for generating double frequency pulse using clock |
| US7583106B2 (en) * | 2007-12-14 | 2009-09-01 | Icera, Inc. | Clock circuitry |
| CN102035472B (en) * | 2010-10-29 | 2013-02-06 | 中国兵器工业集团第二一四研究所苏州研发中心 | Programmable digital frequency multiplier |
| CN103199981B (en) * | 2013-03-25 | 2016-03-30 | 武汉大学 | A kind of digital synchronization pulse signal picosecond level vibration transmission method |
| CN106922015A (en) * | 2015-12-25 | 2017-07-04 | 联芯科技有限公司 | Wireless Telecom Equipment and its frequency synchronization method |
| US11025356B2 (en) * | 2017-09-08 | 2021-06-01 | Knowles Electronics, Llc | Clock synchronization in a master-slave communication system |
| CN112087276B (en) * | 2019-06-14 | 2023-10-24 | 海能达通信股份有限公司 | Clock calibration method and device |
| CN113364550B (en) * | 2020-03-04 | 2022-07-19 | 大唐移动通信设备有限公司 | Clock adjusting method and device |
| CN112362928A (en) * | 2020-09-16 | 2021-02-12 | 天津大学 | High-precision programmable pulse generation system and method capable of realizing synchronous measurement |
-
2021
- 2021-12-21 CN CN202111565516.7A patent/CN113949477B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101873187A (en) * | 2010-05-25 | 2010-10-27 | 中兴通讯股份有限公司 | Method and system of clock synchronization |
| CN106027187A (en) * | 2016-04-29 | 2016-10-12 | 国家电网公司 | GPS (Global Positioning System) synchronizing signal frequency source circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113949477A (en) | 2022-01-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105183423B (en) | A kind of cross-clock domain asynchronous data treating method and apparatus | |
| JP2008525761A5 (en) | ||
| EP3661055A1 (en) | True random number generator | |
| US8253450B2 (en) | Clock signal frequency dividing circuit and method | |
| CN113948030B (en) | Display signal generating device, driving device and display device | |
| CN110708133B (en) | Method and device for clock synchronization and time synchronization in system based on FPGA | |
| CN113949477B (en) | Synchronization method of clock signals with different frequencies | |
| CN104317542A (en) | Method and system for converting frequency of internal storage | |
| CN114546083B (en) | Reset synchronizer circuit and clock gating method thereof | |
| JP6759329B2 (en) | FSK decoding using envelope comparison in the digital domain | |
| JPS61186023A (en) | Clock generating circuit | |
| KR102553855B1 (en) | Shift register | |
| US7200173B2 (en) | Method and apparatus for generating a distortionless pulse width modulated waveform | |
| JP4888837B2 (en) | D / A converter | |
| CN113900480B (en) | Time synchronization method of periodic second pulse output aligned with specified time | |
| US11190135B2 (en) | Low power differential crystal oscillator circuit | |
| JPH1168861A (en) | Simultaneous two-way transmission reception method and simultaneous two-way transmission reception circuit | |
| KR930002256B1 (en) | Pcm clock generating circuit | |
| JP2924418B2 (en) | D / A converter | |
| KR980006918A (en) | 50% Duty Cycle Data Generator (50% Duty Cycle Data Generator) | |
| JPH03204251A (en) | Clock synchronizing circuit | |
| JPH0879210A (en) | Multiplex circuit | |
| JPH08321772A (en) | Pll circuit | |
| CN111669173A (en) | Timestamp phase discrimination method and device | |
| JP3177394B2 (en) | Digital PLL circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |