CN113948636B - Grid-controlled interface type nanofluid memristor and preparation method thereof - Google Patents
Grid-controlled interface type nanofluid memristor and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
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Abstract
The invention relates to an interface type nanofluid memristor, which comprises the following components: a substrate; a nano-channel disposed on top of the substrate; a metal layer covering the bottom and the side wall of the nano-channel and covering the surface of the substrate at one side or two sides of the nano-channel; and a silicon dioxide layer covering a part of the surface of the metal layer. The interface type nanofluid memristor provided by the invention adopts the metal layer as the gate control electrode, so that the influence of leakage current on other devices can be effectively prevented, and the processing technology of the memristor array formed by the memristor is very simple compared with the prior art. In addition, the interface type nanofluid memristor is used as a nanofluid nerve synaptic device, so that the function of an excited nanofluid nerve synaptic device can be realized, and the function of an inhibition type nanofluid nerve synaptic device can be realized. In addition, the invention also relates to a preparation method of the interface type nanofluidic memristor.
Description
Technical Field
The invention relates to the technical field of micro-nano electronics, in particular to a grid-control interface type nanofluid memristor and a preparation method thereof.
Background
After the memristor concept was proposed for nearly forty years, the hewlett-packard laboratory was first making metal oxide based memristors. Various memristors have emerged to date, including inorganic metal oxide memristors, organic memristors, and perovskite memristors. The unique properties of memristors make them widely used in low power storage devices and neuromorphic computing. A liquid memristor is a memristor that uses soft materials including liquid metals, electrolytes, ionic liquids, and ionic gels. The liquid memristor has the characteristics of simple preparation, low cost, flexibility and the like, and has great application potential in a bionic nerve morphology calculation structure.
Although memristor arrays can achieve very high integration density, they may cause the selected cell to be unable to be read or written due to leakage current. Currently, the effects of leakage current can be avoided by connecting each memristor to a gating device (e.g., diode or transistor) at each memristor node. However, this results in the fabrication process of the memristor array becoming very complex.
Therefore, there is a need to develop a memristor that can effectively avoid the effects of leakage currents and simplify the memristor array fabrication process.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide the gate-controlled interface type nanofluidic memristor, which adopts a metal layer as a gate control electrode, can effectively prevent the influence of leakage current on other devices, and has a very simple processing technology compared with the prior art.
The invention further aims at providing a preparation method of the nanofluid memristor.
In order to achieve the above object, the present invention provides the following technical solutions.
An interface-type nanofluid memristor, comprising:
a substrate;
a nano-channel disposed on top of the substrate;
a metal layer covering the bottom and the side wall of the nano-channel and covering the surface of the substrate at one side or two sides of the nano-channel; and
and the silicon dioxide layer covers part of the surface of the metal layer.
The preparation method of the interface type nanofluid memristor comprises the following steps:
providing a substrate;
forming a nano-channel on top of the substrate;
forming a metal layer on the bottom and side walls of the nano-channel and on the surface of the substrate on one or both sides of the nano-channel;
forming a silicon dioxide layer on the metal layer; and
and removing part of the silicon dioxide layer, thereby exposing the corresponding part of the metal layer.
Compared with the prior art, the invention achieves the following technical effects:
1. the interface type nanofluid memristor provided by the invention adopts the metal layer as the gate control electrode, so that the influence of leakage current on other devices can be effectively prevented, and the processing technology of the memristor array formed by the memristor is very simple compared with the prior art.
2. The interface type nanofluid memristor is used as a nanofluid nerve synaptic device, and can realize the functions of an excited nanofluid nerve synaptic device and a suppressed nanofluid nerve synaptic device.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 is a schematic diagram of an interface-type nanofluidic memristor of the present disclosure.
Fig. 2 and 3 are schematic diagrams of interface-type nanofluidic memristors of the present disclosure.
Description of the reference numerals
100 is a substrate, 200 is a first liquid reservoir, 300 is a first liquid, 400 is a first microchannel, 500 is a first electrode, 600 is a nanochannel, 700 is a second liquid reservoir, 800 is a second liquid, 900 is a second microchannel, 1000 is a second electrode, 1100 is a metal layer, 1200 is a silicon dioxide layer.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
The invention will be further described with reference to the accompanying drawings.
FIG. 1 presents a schematic view of an interface-type nanofluidic memristor of the present invention. Specifically, as shown in fig. 1, the interface-type nanofluidic memristor of the present invention includes: a substrate 100; a nano-channel 600 disposed on top of the substrate 100; a metal layer 1100 covering the bottom and sidewalls of the nano-channel 600 and covering the surface of the substrate at one or both sides of the nano-channel 600; and a silicon dioxide layer 1200 covering a portion of the surface of the metal layer 1100.
In the present invention, the substrate 100 may be a silicon substrate or a Polydimethylsiloxane (PDMS) substrate.
The depth of the nanochannel 600 can be 1-100nm, preferably 1-60nm; the width may be 1-400nm, preferably 1-200nm; the length may be 1-10 μm.
The metal layer 1100 may be chromium metal, titanium metal, nickel metal, or platinum metal. The thickness of the metal layer 1100 may be 50nm-200nm. The metal layer 1100 covers the entire bottom and both sidewalls of the nano-channel 600 and covers the surface of the substrate at one or both sides of the nano-channel 600. The metal layer 1100 is an uninterrupted continuous layer structure.
The silicon dioxide layer 1200 serves as an insulator and may have a thickness of 100nm-1 μm. The silicon dioxide layer 1200 completely covers the portion of the metal layer 1100 that is located on the bottom and sidewalls of the nano-channel 600. The portion of the metal layer 1100 not covered by the silicon dioxide layer 1200 (i.e., the exposed portion of the metal layer) is located on the substrate surface for connection to a power source. The present invention is not particularly limited in shape, position and number of exposed portions as long as connection to a power source can be achieved. Preferably, there are exposed portions of the metal layer on both sides of the nanochannel 600 for connection to a power source.
In a preferred embodiment, both ends of the nano-channel 600 may be provided with a first liquid reservoir and a second liquid reservoir in communication therewith for filling the nano-channel 600 with the first liquid and the second liquid. The liquid storage tank has larger volume, and can reduce the influence of solution volatilization on the performance of the device. There is a difference in conductivity between the first liquid and the second liquid, and the two liquids are not compatible with each other, and an immiscible liquid-liquid interface may be formed in the nanochannel 600. The first liquid cannot charge the inner wall of the nano-channel 600, and thus the nano-channel 600 has no ion selectivity to the first liquid. Preferably, the first liquid may be an ionic liquid, preferably an organic weak electrolyte such as [ BMIM ] PF6 or [ BMIM ] Br. The second liquid can react with the inner wall of the nano-channel 600 in a solid-liquid manner, so that the area where the nano-channel 600 contacts with the second liquid is charged, and the nano-channel 600 has ion selectivity to the second liquid. Preferably, the second liquid is a strong electrolyte solution, such as an aqueous KCl solution or an aqueous NaCl solution.
Because the first liquid adopts organic weak electrolyte, the second liquid adopts strong electrolyte solution, the conductivity of the first liquid is far smaller than that of the second liquid, and the first liquid and the second liquid form an immiscible liquid-liquid interface in the nano channel, when the position of the liquid-liquid interface changes in the nano channel, the conductivity of the whole nano channel can obviously change.
In the present invention, both ends of the nano-channel 600 are respectively in communication with the first electrode and the second electrode. The first electrode and the second electrode can both be Ag/AgCl reference electrodes. Preferably, the first electrode is disposed in the first liquid reservoir, and the second electrode is disposed in the second liquid reservoir.
In another preferred embodiment, the interface-type nanofluidic memristor of the present invention may further comprise: a first micro channel 400 disposed on top of the substrate 100 and communicating with one end of the nano channel 600; and a second micro channel 900 disposed on top of the substrate 100 and communicating with the other end of the nano channel 600.
The depth of the first and second micro channels 400 and 900 may be 1-100 μm, respectively, the width may be 1-100 μm, and the length may be 1-3mm, respectively.
Preferably, the microchannel dimensions are above three orders of magnitude greater than the nanochannel width and depth, which may make the resistance of the first microchannel 400 and the second microchannel 900 negligible relative to the resistance of the nanochannel 600. When a voltage is applied to the nanochannel, an electroosmotic flow effect is created in the nanochannel, causing the liquid-liquid interface to move, resulting in a change in conductance across the nanochannel. When the voltage is removed, the liquid-liquid interface is stopped quickly under the damping action due to the high viscosity coefficient of the ionic liquid, and the resistance state of the whole device is recorded.
Preferably, the first micro channel 400 is provided with a first liquid reservoir 200 in communication therewith for filling the nano channel 600 with a first liquid. Preferably, the number of the first liquid storage tanks 200 may be 2 or more. The first reservoir 200 may communicate with both ends or the middle of the first micro channel 400. The position of the first liquid storage tanks 200 is not particularly limited in the present invention, and for example, as shown in fig. 1, 2 first liquid storage tanks 200 are respectively provided at 2 top corners of the substrate 100.
In the present invention, the first micro channel 400 communicates with the first electrode 500. The first electrode 500 may be an Ag/AgCl reference electrode. Preferably, the first electrode 500 is disposed within the first reservoir 200. The number of the first electrodes 500 may be 1 or more, and may increase as the number of the first liquid storage tanks 200 increases. For example, when the first micro channel 400 communicates with 2 first reservoirs 200, 1 electrode may be disposed in one of the reservoirs; when the first micro channel 400 communicates with 3 first reservoirs 200, 1 electrode may be disposed in each of the two reservoirs.
Preferably, the second micro channel 900 is provided with a second liquid reservoir 700 in communication therewith for filling the nano channel 600 with a second liquid. Preferably, the number of the second liquid storage tanks 700 may be 2 or more. The second reservoir 700 may communicate with both ends or the middle of the second micro channel 900. The position of the second liquid storage tanks 700 is not particularly limited in the present invention, and for example, as shown in fig. 1, 2 second liquid storage tanks 700 are respectively provided at 2 top corners of the substrate 100.
In the present invention, the second micro channel 900 communicates with the second electrode 1000. The second electrode 1000 may be an Ag/AgCl reference electrode. Preferably, the second electrode 1000 is disposed within the second reservoir 700. The number of the second electrodes 1000 may be 1 or more, and may increase as the number of the second liquid storage tanks 700 increases. For example, when the second micro channel 900 is in communication with 2 second reservoirs 700, 1 electrode may be disposed in one of the reservoirs; when the second micro channel 900 is in communication with 3 second reservoirs 700, 1 electrode may be disposed in each of the two reservoirs.
Preferably, in the present invention, the metal layer 1100 covers only the bottom and sidewalls of the nano-channel 600 and the substrate surface located at one or both sides of the nano-channel 600, and does not cover the bottoms and sidewalls of the first micro-channel 400, the second micro-channel 900, the first liquid reservoir 200, and the second liquid reservoir 700.
The working principle of the interface type nanofluid memristor is as follows. The wall surface of the nano channel is hydrolyzed in the second liquid, so that the wall surface of the nano channel has a certain charge, and the wall surface of the nano channel can be positively charged or negatively charged according to the different materials of the second liquid and the wall surface of the nano channel. The substrate selected by the invention is a silicon substrate or a PDMS substrate, and is negatively charged after hydrolysis. By applying a voltage to the exposed portion (i.e., the gate terminal) of the metal layer, a charge-discharge effect of the capacitor is generated, and the charge properties of the wall surface of the nano-channel can be changed. When the wall surface of the nano channel is negatively charged, as shown in fig. 2, a forward voltage is applied to the nano channel (the positive electrode of the nano fluid memristor is set to be a first liquid end), and a liquid-liquid interface in the nano channel moves towards a second liquid side under the action of electroosmosis; and applying reverse voltage to the nano channel, and moving a liquid-liquid interface in the nano channel to the first liquid side under the action of electroosmosis. When the wall surface of the nano channel is positively charged, as shown in fig. 3, a forward voltage is applied to the nano channel (the positive electrode of the nano fluid memristor is set to be a first liquid end), and a liquid-liquid interface in the nano channel moves towards a second liquid side under the action of electroosmosis; negative voltage is applied to the nano-channel, and the liquid-liquid interface in the nano-channel moves to the first liquid side under the action of electroosmotic flow.
After the interface type nanofluid memristor is arrayed, the switch of a certain memristor unit can be selected at fixed point by controlling the gate control voltage, and gating of the memristor is realized, so that mutual crosstalk among array units is eliminated, and the influence of leakage current on other devices is prevented. The interface type nano-fluid memristor can solve the limit that one memristor and one gating device are matched for use in the existing memristor array unit, greatly simplifies the processing process flow of the memristor array, and has great significance for the integration of nano-fluid nerve morphology devices. In addition, the interface type nanofluid memristor can realize the change of the voltage-driven electroosmosis flow direction by changing the positive and negative properties of the wall surface of the nano channel, thereby simultaneously realizing the functions of an excited nanofluid nerve synapse device and an inhibited nanofluid nerve synapse device.
The invention also provides a preparation method of the interface type nanofluid memristor, which comprises the following steps.
First, a substrate 100 is provided.
Then, a nano-channel 600 is formed on top of the substrate 100.
The method of forming the nano-channel 600 is not particularly limited in the present invention, and for example, a combination of electron beam lithography and plasma etching may be employed.
Thereafter, a metal layer is formed on the bottom and sidewalls of the nanochannel and on the surface of the substrate on one or both sides of the nanochannel.
The method for forming the metal layer is not particularly limited, and may be, for example, physical vapor deposition, electroplating, electron beam evaporation, magnetron sputtering, or the like.
Next, a silicon dioxide layer is formed on the metal layer.
The invention can use chemical vapor deposition to form silicon dioxide layer. The silicon dioxide layer completely covers the metal layer. In some embodiments, the silicon dioxide layer covers the entire upper surface of the substrate.
Finally, a portion of the silicon dioxide layer is removed, thereby exposing a corresponding portion of the metal layer.
Preferably, a combination of photolithography and etching may be employed to remove portions of the silicon dioxide layer. The etching method is not particularly limited, and dry etching, wet etching, a combination thereof, or the like may be employed. Dry etching may include ion milling etching, inductively Coupled Plasma (ICP) etching, and deep reactive ion etching.
In a preferred embodiment, a combination of photolithography and etching is used to form a first reservoir and a second reservoir at and in communication with both ends of the nanochannel.
Preferably, lithography can be performed using a uv lithography machine. The photolithography process includes aligning the nanochannels and overlay exposure. Preferably, the etching may be plasma etching. In one embodiment, the forming of the first reservoir and the second reservoir includes: the method comprises the steps of spin coating negative photoresist on a substrate, aligning a nano channel in an ultraviolet photoetching machine, carrying out alignment exposure, developing by using a developing solution, carrying out plasma etching, and carrying out post-development.
In another preferred embodiment, a combination of photolithography and etching is used to form the first and second micro-channels at both ends of the nano-channel.
Preferably, lithography can be performed using a uv lithography machine. The photolithography process includes aligning the nanochannels and overlay exposure. Preferably, the etching may be plasma etching. In one embodiment, the forming of the first and second microchannels includes: the method comprises the steps of spin coating negative photoresist on a substrate, aligning a nano channel in an ultraviolet photoetching machine, carrying out alignment exposure, developing by using a developing solution, carrying out plasma etching, and carrying out post-development.
In another preferred embodiment, a combination of photolithography and etching is utilized to form first and second reservoirs in communication with the first and second microchannels, respectively.
Preferably, lithography can be performed using a uv lithography machine. The photolithographic process includes aligning the first or second micro-channel and an overlay exposure. Preferably, the etching may be plasma etching. In one embodiment, the forming of the first reservoir and the second reservoir includes: a negative photoresist is spin coated on a substrate, then the first micron channel or the second micron channel is aligned in an ultraviolet photoetching machine, the alignment exposure is carried out, then the development is carried out by using a developing solution, then the plasma etching is carried out, and the post development is carried out.
In a preferred embodiment, after the first and second electrodes are placed in the first and second reservoirs, respectively, the cured PDMS is aligned and sealed over all channels and all reservoirs, wherein the cured PDMS is provided with small holes for filling at positions corresponding to the reservoirs. The present invention is not particularly limited in the number, size and shape of the small holes as long as the liquid injection can be achieved.
The invention will be further illustrated with reference to specific examples, but the invention is not limited thereto.
First, a substrate is provided. Then, photoresist is spin-coated on the substrate, and a nano-channel pattern is exposed on the substrate by using an electron beam exposure system, and then development, etching and photoresist removal are performed, thereby forming a nano-channel.
Next, a negative photoresist is spin coated on the substrate, then the nano-channels are aligned in an ultraviolet lithography machine, subjected to alignment exposure, then developed using a developing solution, then subjected to plasma etching, and then post-developed, thereby forming first and second micro-channels.
And then, spin-coating negative photoresist on the substrate, aligning the first micrometer channel and the second micrometer channel in an ultraviolet photoetching machine respectively, performing alignment exposure, then developing by using a developing solution, performing plasma etching, and performing post-development, thereby forming a first liquid storage pool and a second liquid storage pool.
Thereafter, a chromium metal layer is formed on the bottom and sidewalls of the nanochannel and on the surface of the substrate on one or both sides of the nanochannel by physical vapor deposition.
Next, a silicon dioxide layer is formed on the chromium metal layer by chemical vapor deposition.
And then, removing part of the silicon dioxide layer by adopting the combination of photoetching and etching, so that the metal layer of the corresponding part is exposed, and forming a grid control electrode pattern.
And then, the first electrode and the second electrode are respectively arranged in the first liquid storage tank and the second liquid storage tank.
Finally, the cured PDMS was aligned and sealed over all channels and all reservoirs, with small holes in the cured PDMS at positions corresponding to the reservoirs for priming.
The present invention is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present invention are intended to be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. An interface-type nanofluid memristor, comprising:
a substrate;
a nano-channel disposed on top of the substrate;
the metal layer covers the bottom and the side wall of the nano channel and covers the surface of the substrate positioned at one side or two sides of the nano channel, and the metal layer is a gate control electrode; and
and the silicon dioxide layer covers part of the surface of the metal layer.
2. The interface-type nanofluidic memristor of claim 1, further comprising: the first micro-channel is arranged on the top of the substrate and is communicated with one end of the nano-channel; and a second micro-channel arranged on the top of the substrate and communicated with the other end of the nano-channel.
3. The interface-type nanofluidic memristor of claim 2, wherein the first microchannel is provided with a first liquid reservoir in communication therewith for filling the nanochannel with a first liquid; the second micro-channel is provided with a second liquid storage tank communicated with the second micro-channel and used for filling second liquid into the nano-channel.
4. The interface-type nanofluid memristor according to claim 1, wherein the two ends of the nanochannel are provided with a first liquid storage tank and a second liquid storage tank communicated with the nanochannel, and the first liquid and the second liquid are filled into the nanochannel.
5. The interface-type nanofluidic memristor of any one of claims 1-4, wherein the metal layer is chromium metal, titanium metal, nickel metal, or platinum metal.
6. The interface-type nanofluidic memristor of any one of claims 1-4, wherein the substrate is a silicon substrate or a polydimethylsiloxane substrate.
7. The interface-type nanofluidic memristor of claim 3 or 4, wherein the first liquid is an organic weak electrolyte; the second liquid is a strong electrolyte solution; the first liquid and the second liquid are immiscible with each other.
8. The method for preparing the interface-type nanofluidic memristor according to any one of claims 1 to 7, comprising:
providing a substrate;
forming a nano-channel on top of the substrate;
forming a metal layer on the bottom and side walls of the nano-channel and on the surface of the substrate on one or both sides of the nano-channel;
forming a silicon dioxide layer on the metal layer; and
and removing part of the silicon dioxide layer, thereby exposing the corresponding part of the metal layer.
9. The method of manufacturing according to claim 8, further comprising: a combination of photolithography and etching is used to form a first microchannel and a second microchannel at both ends of the nanochannel.
10. The method of manufacturing according to claim 9, further comprising: a combination of photolithography and etching is utilized to form first and second reservoirs in communication with the first and second microchannels, respectively.
Priority Applications (1)
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| CN111106239A (en) * | 2019-12-19 | 2020-05-05 | 华中科技大学 | Complementary structure synaptic device based on nanofluid interface type memristor and preparation thereof |
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| CN111106239A (en) * | 2019-12-19 | 2020-05-05 | 华中科技大学 | Complementary structure synaptic device based on nanofluid interface type memristor and preparation thereof |
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