CN113948459A - Method for debonding SiC wafer on silicon substrate - Google Patents

Method for debonding SiC wafer on silicon substrate Download PDF

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Publication number
CN113948459A
CN113948459A CN202111119932.4A CN202111119932A CN113948459A CN 113948459 A CN113948459 A CN 113948459A CN 202111119932 A CN202111119932 A CN 202111119932A CN 113948459 A CN113948459 A CN 113948459A
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China
Prior art keywords
silicon substrate
sic
debonding
sic wafer
etching
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CN202111119932.4A
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Chinese (zh)
Inventor
严立巍
符德荣
李景贤
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Zhejiang Tongxinqi Technology Co ltd
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Zhejiang Tongxinqi Technology Co ltd
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Priority to CN202111119932.4A priority Critical patent/CN113948459A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
    • H01L21/7813—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate leaving a reusable substrate, e.g. epitaxial lift off

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)

Abstract

The invention provides a method for debonding a SiC wafer on a silicon substrate. The method comprises the following steps: s100: turning over the silicon substrate bonded with the SiC pieces, so that the SiC pieces face the graphite tray and are embedded into the graphite tray; s200: spraying etching solution to the silicon substrate to enable the SiC pieces and the silicon substrate to be bonded; s300: the silicon substrate after debonding was removed and pieces of SiC were left in the graphite tray. According to the method for debonding and bonding the SiC piece on the silicon substrate, the SiC piece is aligned and embedded into the graphite plate, the high-temperature resistance of the graphite plate is utilized, subsequent processes such as high-temperature annealing and the like for the SiC piece are facilitated, besides, debonding is performed in a chemical etching mode through the etching liquid, the surface damage to the SiC piece is avoided, and the yield of SiC devices is improved.

Description

Method for debonding SiC wafer on silicon substrate
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for debonding and bonding a SiC wafer on a silicon substrate.
Background
Semiconductor materials can be classified into elementary semiconductors such as semiconductors formed of silicon (Si), germanium (Ge), and the like, and compound semiconductors such as gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and the like. While semiconductors have been mainly changed in the third generation in the past, gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC) semiconductors, which are representative of the second and third generation semiconductors, are much more excellent in high-frequency performance and high-temperature performance than the first generation semiconductors, and are more expensive to manufacture, and are therefore new and expensive in semiconductors.
The compound semiconductor can show excellent performance on ultrahigh voltage (8000V) IGBT and ultrahigh frequency (300 KHz) MOSFET elements, but the current mass production technology of the crystal growth material can only limit the substrate size to 6 inches and below 6 inches, and is incompatible with the 8 inch/12 inch process of the existing silicon wafer. Because most of the processing processes are similar, if the sizes are consistent, SiC with 6 inches and below 6 inches can be attached to a silicon wafer with 8 inches/12 inches by bonding and other technologies, and mass production can be implemented by embedding a few processing equipment special for the SiC or GaN process in a mass production line, which is much more efficient than that of a newly-established small-sized SiC or GaN production line.
However, since a process for SiC is different from a process for silicon in manufacturing a semiconductor device, for example, in some processes, the SiC device needs to undergo a high temperature step of more than 1200 ℃, and silicon cannot withstand the temperature, it is a problem to be solved how to release the silicon wafer from the SiC bonded thereto and smoothly pass through a special step such as a high temperature step when performing a specific step.
Disclosure of Invention
The invention provides a method for debonding a SiC piece on a silicon substrate, aiming at solving the technical problem of how to debond the permanent bonding of the silicon substrate and the SiC piece bonded on the silicon substrate.
The method for debonding the SiC wafer on the silicon substrate according to the embodiment of the invention comprises the following steps:
turning over the silicon substrate bonded with the plurality of SiC pieces, so that the SiC pieces face a graphite tray and are embedded into the graphite tray;
spraying etching liquid to the silicon substrate to enable a plurality of SiC pieces to be bonded with the silicon substrate;
removing the silicon substrate after the bonding is released, and keeping a plurality of pieces of SiC on the graphite tray.
According to the method for debonding the SiC piece on the silicon substrate, the SiC piece is aligned and embedded into the graphite plate, the high-temperature resistance of the graphite plate is utilized, subsequent processes such as high-temperature annealing and the like for the SiC piece are facilitated, in addition, debonding is performed in a chemical etching mode through the etching liquid, the surface damage to the SiC piece is avoided, and the yield of SiC devices is improved.
According to some embodiments of the invention, the bonding surface of the silicon substrate has a plurality of receiving grooves, and a plurality of the SiC wafers pass through SiO on the bottom walls of the receiving grooves2And is bonded in the corresponding accommodating groove.
In some embodiments of the invention, an upper surface of the SiC wafer bonded to the receiving groove is higher than the bonding surface of the silicon substrate.
According to some embodiments of the invention, a plurality of uniformly distributed and penetrating SiO are prepared on the silicon substrate before the etching solution is sprayed2So that the etching solution flows to the SiO through the etching hole2Etching to remove the SiO2。
In some embodiments of the present invention, the diameter of the etch holes is not less than 100 μm.
According to some embodiments of the present invention, the graphite tray has a plurality of placing grooves having a predetermined depth and a predetermined angle, and the plurality of placing grooves correspond to the plurality of SiC pieces one to one.
In some embodiments of the present invention, after the SiC chip is fitted into the corresponding placement groove, the SiC chip is at least partially exposed from the placement groove to provide a gap between the silicon substrate and the graphite tray.
According to some embodiments of the invention, the etching liquid is hydrofluoric acid.
In some embodiments of the invention, the silicon substrate has a size of 8 inches or 12 inches, and the plurality of SiC tiles on the silicon substrate have a size in a range of: 2 cun to 6 cun.
According to some embodiments of the invention, the silicon substrate is removed in a direction perpendicular to the silicon substrate using a chuck or vacuum suction after debonding is completed.
Drawings
FIG. 1 is a schematic flow diagram of a method for debonding a SiC wafer on a silicon substrate according to an embodiment of the present invention;
FIG. 2 is a schematic flow diagram of some embodiments of a method for debonding a SiC wafer on a silicon substrate in accordance with embodiments of the present invention;
FIG. 3 is a schematic view of a silicon substrate with a SiC piece bonded thereto prior to debonding according to a method of debonding a SiC piece on a silicon substrate in accordance with an embodiment of the present invention;
fig. 4 is a cross-sectional view of a wafer prepared in step S100 of the method of debonding a SiC wafer on a silicon substrate according to an embodiment of the present invention;
fig. 5 is a cross-sectional view of a wafer prepared at step S300 of the method of debonding a SiC wafer on a silicon substrate according to an embodiment of the present invention;
fig. 6 is a schematic structural view of a graphite tray for a method of debonding a SiC wafer on a silicon substrate according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of a silicon substrate in some embodiments of a method of debonding a SiC wafer on a silicon substrate according to embodiments of the present invention;
FIG. 8 is a schematic view of a silicon substrate with a SiC piece bonded thereto prior to debonding in some embodiments of a method of debonding a SiC piece on a silicon substrate in accordance with an embodiment of the present invention;
fig. 9 is a schematic structural view of the silicon substrate prepared through step S150 of the method for debonding a SiC wafer on the silicon substrate according to the embodiment of the present invention.
Reference numerals:
silicon substrate 10, bonding surface 11, receiving groove 12, SiO 213, etching the holes 14, etching the holes,
the SiC chip 20 is a silicon carbide chip that,
graphite tray 30, placing groove 31.
Detailed Description
To further explain the technical means and effects of the present invention adopted to achieve the intended purpose, the present invention will be described in detail with reference to the accompanying drawings and preferred embodiments.
As shown in fig. 1 to 5, a method of debonding a SiC wafer on a silicon substrate according to an embodiment of the present invention includes:
s100: the silicon substrate bonded with the SiC pieces is turned over so that the SiC pieces face the graphite tray and are embedded in the graphite tray.
S200: and spraying etching solution to the silicon substrate to debond the plurality of SiC pieces from the silicon substrate.
S300: the silicon substrate after debonding was removed and pieces of SiC were left in the graphite tray.
According to the method for debonding the SiC piece on the silicon substrate, the SiC piece 20 is aligned and embedded into the graphite plate, the high-temperature resistance of the graphite plate is utilized, subsequent processes such as high-temperature annealing and the like for the SiC piece 20 are facilitated, in addition, debonding is performed in a chemical etching mode through the etching liquid, the surface damage to the SiC piece 20 is avoided, and the yield of SiC devices is improved.
As shown in fig. 7, according to some embodiments of the present invention, bonding surface 11 of silicon substrate 10 has a plurality of receiving grooves 12, and a plurality of SiC wafers 20 pass through SiO on bottom walls of receiving grooves 12213 are keyed to the corresponding housing grooves 12.
As shown in fig. 8, in some embodiments of the present invention, the upper surface of the SiC chip 20 bonded to the receiving groove 12 is higher than the bonding surface 11 of the silicon substrate 10.
It should be noted that the upper surface of the SiC chip 20 is higher than the bonding surface 11, so as to be in contact with the silicon substrate 10 in the previous process and affect the processing of the upper surface of the SiC chip, and meanwhile, the upper surface of the SiC chip 20 is higher than the bonding surface 11 of the silicon substrate 10 so as to avoid interference between the silicon substrate 10 and the graphite tray 30 when the SiC chip 20 is debonded from the silicon substrate 10 and transferred to the graphite tray 30, so as to avoid the problem that the SiC chip 20 cannot be aligned correctly and embedded in the graphite tray 30 in the debonding process.
As shown in fig. 2 and 9, according to some embodiments of the present invention, before step S200, the method further includes:
s150: preparing a plurality of uniformly distributed SiO penetrating through the silicon substrate2So that the etching solution flows to SiO through the etching hole2Etching to remove SiO2. The present invention preferably processes the silicon substrate 10 by a laser process or dry etching (plasma etching) or the like to form the above-mentioned etching holes 14, and the etching liquid flows to the SiO through the etching holes 14 by spraying to the opposite surface of the silicon substrate 10 to which the SiC chip 20 is bonded213. In addition, theThe invention preferably uses SiO under the action of the etching solution2The etching selection ratio of 13 with respect to the silicon substrate 10 ranges from 500 to 1000.
As shown in fig. 9, in some embodiments of the present invention, the diameter of the etch holes 14 is not less than 100 μm.
As shown in fig. 6, according to some embodiments of the present invention, the graphite tray 30 has a plurality of placing grooves 31 having a predetermined depth and a predetermined angle, and the plurality of placing grooves 31 correspond one-to-one to the plurality of SiC sheets 20.
The number of the placing grooves 31 is the same as that of the accommodating grooves 12, and the placing grooves are arranged in a one-to-one correspondence manner, and the bottom surfaces of the placing grooves 31 need to reach a preset flatness, so that the SiC pieces 20 can be accurately placed, and flatness meeting technological requirements is provided for subsequent processing steps of processing the SiC pieces 20.
In addition, in the conventional processing technology of the SiC wafer 20, the edge of the SiC wafer 20 generally needs to be ground to form a chamfer, so that damage caused by stress at the edge can be prevented, and the flatness of the epitaxial layer and the photoresist at the edge of the SiC wafer 20 can be increased. As shown in fig. 5, the included angle between the side surface and the bottom surface of the placing groove 31 needs to be adapted to the edge angle of the SiC chip 20 to facilitate the subsequent step, i.e., the preset angle needs to be set according to the edge shape of the SiC chip 20.
As shown in fig. 5, in some embodiments of the present invention, after SiC chip 20 is fitted into corresponding placement groove 31, SiC chip 20 is at least partially exposed from placement groove 31 so that there is a gap between silicon substrate 10 and graphite tray 30.
According to some embodiments of the invention, the etching liquid is hydrofluoric acid. Specifically, the preferred hydrofluoric acid concentration range of the present invention is 1% to 20%, and the etching temperature range is 20 ℃ to 40 ℃.
In some embodiments of the invention, silicon substrate 10 has dimensions of 8 inches or 12 inches, and the plurality of SiC tiles 20 on silicon substrate 10 have dimensions in the range of: 2 cun to 6 cun.
According to some embodiments of the invention, it is characterized in that after the debonding is completed, the silicon substrate 10 is removed in a direction perpendicular to the silicon substrate 10 using a chuck or vacuum suction.
According to the method for debonding the SiC piece on the silicon substrate, the SiC piece 20 is aligned and embedded into the graphite plate, the high-temperature resistance of the graphite plate is utilized, subsequent processes such as high-temperature annealing and the like for the SiC piece 20 are facilitated, in addition, debonding is performed in a chemical etching mode through the etching liquid, the surface damage to the SiC piece 20 is avoided, and the yield of SiC devices is improved.
While the invention has been described in connection with specific embodiments thereof, it is to be understood that it is intended by the appended drawings and description that the invention may be embodied in other specific forms without departing from the spirit or scope of the invention.

Claims (10)

1. A method of debonding a SiC wafer from a silicon substrate, the method for debonding a silicon substrate having a plurality of SiC wafers bonded thereto, the method comprising:
turning over the silicon substrate bonded with the plurality of SiC pieces, so that the SiC pieces face a graphite tray and are embedded into the graphite tray;
spraying etching liquid to the silicon substrate to enable a plurality of SiC pieces to be bonded with the silicon substrate;
removing the silicon substrate after the bonding is released, and keeping a plurality of pieces of SiC on the graphite tray.
2. The method of claim 1, wherein the bonding surface of the silicon substrate has a plurality of receiving grooves, and a plurality of SiC wafers pass through SiO on the bottom walls of the receiving grooves2And is bonded in the corresponding accommodating groove.
3. The method of debonding a SiC wafer from a silicon substrate according to claim 2, wherein the upper surface of the SiC wafer bonded to the receiving cavity is higher than the bonding surface of the silicon substrate.
4. The method of debonding a SiC wafer on a silicon substrate according to claim 2, characterized in that the etching is sprayed onBefore etching liquid, preparing a plurality of uniformly distributed SiO-penetrating silicon substrates2So that the etching solution flows to the SiO through the etching hole2Etching to remove the SiO2。
5. The method of debonding a SiC wafer on a silicon substrate according to claim 4, characterized in that the diameter of the etched holes is not less than 100 μ ι η.
6. The method of debonding SiC wafers from a silicon substrate according to claim 1, wherein the graphite tray has a plurality of placement grooves with predetermined depths and predetermined angles, the plurality of placement grooves corresponding one-to-one to a plurality of SiC wafers.
7. The method of debonding a SiC wafer from a silicon substrate according to claim 6, wherein after the SiC wafer is embedded in the corresponding placement groove, the SiC wafer is at least partially exposed from the placement groove to provide a gap between the silicon substrate and the graphite tray.
8. The method of debonding a SiC wafer from a silicon substrate according to claim 1, wherein the etching solution is hydrofluoric acid.
9. The method of debonding a SiC wafer from a silicon substrate of claim 1, wherein the silicon substrate has a size of 8 inches or 12 inches, and the plurality of SiC wafers on the silicon substrate have a size range of: 2 cun to 6 cun.
10. The method of debonding a SiC wafer on a silicon substrate according to claim 1, wherein after debonding is complete, the silicon substrate is removed in a direction perpendicular to the silicon substrate using a suction cup or vacuum suction.
CN202111119932.4A 2021-09-24 2021-09-24 Method for debonding SiC wafer on silicon substrate Pending CN113948459A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111119932.4A CN113948459A (en) 2021-09-24 2021-09-24 Method for debonding SiC wafer on silicon substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111119932.4A CN113948459A (en) 2021-09-24 2021-09-24 Method for debonding SiC wafer on silicon substrate

Publications (1)

Publication Number Publication Date
CN113948459A true CN113948459A (en) 2022-01-18

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