CN113946536B - I2C protocol circuit of NVMe hard disk and I2C environment control method - Google Patents

I2C protocol circuit of NVMe hard disk and I2C environment control method Download PDF

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CN113946536B
CN113946536B CN202111558231.0A CN202111558231A CN113946536B CN 113946536 B CN113946536 B CN 113946536B CN 202111558231 A CN202111558231 A CN 202111558231A CN 113946536 B CN113946536 B CN 113946536B
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pull
selection unit
channel selection
channel
channel selector
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CN113946536A (en
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刘振
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016Inter-integrated circuit (I2C)

Abstract

The application discloses I2C protocol circuit and I2C environmental control method of NVMe hard disk, this I2C protocol circuit includes: the device comprises a BMC, a plurality of pull-up power supplies, a plurality of pull-up resistors, an isolation unit, a first channel selection unit and a second channel selection unit, wherein an input signal end of the isolation unit is connected with the BMC, an input power end is connected with a preset power supply, an output power end is connected with any pull-up power supply through the first channel selection unit, an output signal end is connected with any pull-up resistor and any pull-up power supply through the second channel selection unit, or the connection with all pull-up resistors and all pull-up power supplies is disconnected through the second channel selection unit, and the output signal end is further connected with the NVMe hard disk. In the application, the I2C protocol circuit flexibly selects the pull-up power supply and the pull-up resistor connected with the isolation unit through the first channel selection unit and the second channel selection unit, and provides a plurality of I2C protocol circuits which are flexibly adaptive and reliably communicate for the NVMe hard disk.

Description

I2C protocol circuit of NVMe hard disk and I2C environment control method
Technical Field
The invention relates to the field of hard disk interfaces, in particular to an I2C protocol circuit of an NVMe hard disk and an I2C environment control method.
Background
Currently, with the rapid development of related technologies such as edge computing, environment diversity puts new requirements on the temperature applicability of edge server hardware systems. Aiming at the design requirement that the working temperature is between-40 ℃ and 85 ℃, manufacturers make NVMe (Non-Volatile Memory host controller interface specification)) hard disks which are applicable to a wide temperature range. However, because the NVMe hard disks are designed independently by manufacturers and may not meet the m.2 design specification, NVMe hard disks of different brands correspond to different pull-up power supplies and pull-up resistors, a hard disk interface on a server only has one constant I2C (Inter-Integrated Circuit, two-wire serial bus) protocol Circuit, and is difficult to adapt to multiple types of NVMe hard disks, and once the two are not adapted, the conditions of system leakage, I2C information abnormal reading and the like occur.
Therefore, how to provide a solution to the above technical problems is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present invention is directed to provide an I2C protocol circuit and an I2C environment control method for NVMe hard disks with flexible adaptation. The specific scheme is as follows:
an I2C protocol circuit of NVMe hard disk, comprising: BMC, a plurality of pull-up power supplies, a plurality of pull-up resistors, isolation unit, first channel selection unit and second channel selection unit, wherein:
the input signal end of the isolation unit is connected with the BMC;
the input power end of the isolation unit is connected with a preset power supply;
an output power supply end of the isolation unit is connected with any pull-up power supply through the first channel selection unit;
the output signal end of the isolation unit is connected with any pull-up resistor and any pull-up power supply through the second channel selection unit, or is disconnected with all the pull-up resistors and all the pull-up power supplies through the second channel selection unit;
and the output signal end of the isolation unit is also connected with the NVMe hard disk.
Preferably, a plurality of input terminals of the first channel selection unit are connected to the plurality of pull-up power sources one by one, and an output terminal of the first channel selection unit is connected to an output power source terminal of the isolation unit.
Preferably, the first ends of all the pull-up resistors are connected with the output end of the first channel selection unit;
second ends of all the pull-up resistors are respectively connected with the plurality of input ends of the second channel selection unit one by one;
and the output end of the second channel selection unit is connected with the output signal end of the isolation unit.
Preferably, the second channel selection unit further includes a null input terminal.
Preferably, the second channel selection unit is a channel selector;
the channel selector includes: the input end of the air connection and the input ends are connected with the second ends of the pull-up resistors one by one.
Preferably, the second channel selection unit includes a first channel selector and a second channel selector;
a plurality of input ends of the first channel selector are connected with second ends of the pull-up resistors one by one;
the first input end of the second channel selector is connected with the output end of the first channel selector, the second input end of the second channel selector is in idle connection, and the output end of the second channel selector is connected with the output signal end of the isolation unit.
Preferably, the second channel selection unit includes a first channel selector and a second channel selector;
the first input end of the second channel selector is connected with the output end of the first channel selection unit, the second input end of the second channel selector is in idle connection, and the output end of the second channel selector is connected with the first ends of all the pull-up resistors;
and a plurality of input ends of the first channel selector are connected with second ends of the pull-up resistors one by one, and output ends of the first channel selector are connected with output signal ends of the isolation units.
Preferably, the second channel selection unit includes a third channel selector and a fourth channel selector;
all the pull-up power supplies are respectively connected with the plurality of input ends of the third channel selector one by one;
the output end of the third channel selector is connected with the first ends of all the pull-up resistors;
second ends of all the pull-up resistors are respectively connected with the plurality of input ends of the fourth channel selector one by one;
the output end of the fourth channel selector is connected with the output signal end of the isolation unit;
the third channel selector further comprises a null-connect input, and/or the fourth channel selector further comprises a null-connect input.
Preferably, the BMC is used to:
acquiring working environment information of the NVMe hard disk;
and selecting the conduction channels of the first channel selection unit and the second channel selection unit according to the working environment information, so that an output power supply end of the isolation unit is connected with the pull-up power supply corresponding to the working environment information, and an output signal end of the isolation unit is connected with the pull-up resistor corresponding to the working environment information or is not connected with the pull-up resistor.
Correspondingly, the application also discloses an I2C environment control method of the NVMe hard disk, which is applied to the BMC of the I2C protocol circuit of any one of the NVMe hard disks, and the I2C environment control method includes:
acquiring working environment information of the NVMe hard disk;
and selecting the conduction channels of the first channel selection unit and the second channel selection unit according to the working environment information so that an output power supply end of the isolation unit is connected with a pull-up power supply corresponding to the working environment information, and an output signal end of the isolation unit is connected with a pull-up resistor corresponding to the working environment information or is not connected with the pull-up resistor.
The application discloses I2C protocol circuit of NVMe hard disk includes: BMC, a plurality of pull-up power supplies, a plurality of pull-up resistors, isolation unit, first channel selection unit and second channel selection unit, wherein: the input signal end of the isolation unit is connected with the BMC; the input power end of the isolation unit is connected with a preset power supply; an output power supply end of the isolation unit is connected with any pull-up power supply through the first channel selection unit; the output signal end of the isolation unit is connected with any pull-up resistor and any pull-up power supply through the second channel selection unit, or is disconnected with all the pull-up resistors and all the pull-up power supplies through the second channel selection unit; and the output signal end of the isolation unit is also connected with the NVMe hard disk. In the I2C protocol circuit, when the communication relation between BMC and NVMe hard disk is established through the isolation unit, the pull-up power supply and the pull-up resistor of the isolation unit can be flexibly selected through the first channel selection unit and the second channel selection unit, so that multiple I2C protocol circuits with flexible adaptation and reliable communication are provided for the NVMe hard disk.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a structural distribution diagram of an I2C protocol circuit of an NVMe hard disk according to an embodiment of the present invention;
fig. 2 is a structural distribution diagram of an I2C protocol circuit of a specific NVMe hard disk according to an embodiment of the present invention;
fig. 3 is a structural distribution diagram of an I2C protocol circuit of a specific NVMe hard disk according to an embodiment of the present invention;
fig. 4 is a structural distribution diagram of an I2C protocol circuit of a specific NVMe hard disk according to an embodiment of the present invention;
fig. 5 is a structural distribution diagram of an I2C protocol circuit of a specific NVMe hard disk according to an embodiment of the present invention;
fig. 6 is a structural distribution diagram of an I2C protocol circuit of a specific NVMe hard disk according to an embodiment of the present invention;
fig. 7 is a structural distribution diagram of an I2C protocol circuit of a specific NVMe hard disk according to an embodiment of the present invention;
fig. 8 is a flowchart illustrating steps of a specific I2C environment control method for NVMe hard disks according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Because the NVMe hard disks adaptive to the wide temperature range are independently designed by manufacturers and may not meet the M.2 design specification, the NVMe hard disks of different brands correspond to different pull-up power supplies and pull-up resistors, a hard disk interface on a server only has one constant I2C protocol circuit, the NVMe hard disks are difficult to adapt to, and once the NVMe hard disks are not adapted to the NVMe hard disks, the conditions of system electric leakage, abnormal reading of I2C information and the like can occur.
In the I2C protocol circuit, when the communication relation between BMC and NVMe hard disk is established through the isolation unit, the pull-up power supply and the pull-up resistor of the isolation unit can be flexibly selected through the first channel selection unit and the second channel selection unit, so that multiple I2C protocol circuits with flexible adaptation and reliable communication are provided for the NVMe hard disk.
The embodiment of the invention discloses an I2C protocol circuit of an NVMe hard disk, which comprises the following steps: BMC 1, a plurality of pull-up power sources V, a plurality of pull-up resistors R, an isolation unit 2, a first channel selection unit 3 and a second channel selection unit 4, wherein:
the input signal end of the isolation unit 2 is connected with the BMC 1;
the input power end of the isolation unit 2 is connected with a preset power supply;
the output power end of the isolation unit 2 is connected with any one of the pull-up power supplies V through the first channel selection unit 3;
the output signal end of the isolation unit 2 is connected with any one of the pull-up resistors R and any one of the pull-up power supplies V through the second channel selection unit 4, or is disconnected with all the pull-up resistors R and all the pull-up power supplies V through the second channel selection unit 4;
and the output signal end of the isolation unit 2 is also connected with an NVMe hard disk 5.
It can be understood that the main role of the isolation unit 2 is to establish a communication relationship between the BMC 1 (Baseboard Management Controller) and the NVMe hard disk 5, and simultaneously ensure that the electrical environment between the two is isolated from interference. Specifically, at the BMC 1 side, an input signal terminal of the isolation unit 2 is connected to the BMC 1, and an input power terminal is connected to a preset power supply, and further, according to a control requirement of the BMC 1, the input signal terminal may be further connected to a pull-up resistor, as shown in fig. 1, when the BMC 1 in the server motherboard communicates, the pull-up resistor is P3V3 STBY, and the pull-up resistor is 4.7k Ω. Similarly, on the NVMe hard disk 5 side, the output power terminal of the isolation unit 2 needs to be matched with a pull-up power source V, and a pull-up resistor R is cancelled or matched with a certain pull-up resistor R at the output signal terminal according to the situation, at this time, the matching of the specific pull-up power source V and pull-up resistor R is realized through the first channel selection unit 3 and the second channel selection unit 4, the matching of the specific pull-up power source V and pull-up resistor R is determined according to the model of the NVMe hard disk 5, usually, the BMC 1 acquires the working environment information of the NVMe hard disk 5, and then the channel states of the first channel selection unit 3 and the second channel selection unit 4 are controlled.
Therefore, BMC 1 in this embodiment is used to: acquiring working environment information of the NVMe hard disk 5; and selecting the conduction channels of the first channel selecting unit 3 and the second channel selecting unit 4 according to the working environment information, so that an output power supply end of the isolating unit 2 is connected with the pull-up power supply V corresponding to the working environment information, and an output signal end of the isolating unit 2 is connected with the pull-up resistor R corresponding to the working environment information or is not connected with the pull-up resistor R.
It can be understood that when the BMC 1 acquires the working environment information of the NVMe hard disk, the model of the NVMe hard disk 5 is generally acquired through a BIOS (Basic Input Output System), and a working environment information table corresponding to various models is prestored in the BMC 1, from which the working environment information of the current NVMe hard disk 5 is determined.
In the I2C protocol circuit, when establishing the communication relation of BMC and NVMe hard disk through the isolation unit, the pull-up power supply and the pull-up resistor of the isolation unit can be flexibly selected through the first channel selection unit and the second channel selection unit, thereby providing a plurality of flexibly adaptive I2C protocol circuits for the NVMe hard disk.
The embodiment of the invention discloses a specific I2C protocol circuit of an NVMe hard disk, and compared with the previous embodiment, the embodiment further explains and optimizes the technical scheme.
Specifically, a plurality of input terminals of the first channel selecting unit 3 are connected to the plurality of pull-up power sources V one by one, and an output terminal is connected to an output power source terminal of the isolating unit 2.
It can be understood that the first channel selection unit 3 is generally implemented by a channel selector MUX01, wherein a plurality of input terminals of the MUX01 are connected to a plurality of pull-up power sources V one by one, and an output terminal of the MUX is connected to an output power terminal of the isolation unit 2, taking two pull-up power sources P3V3 and P1V8 as examples, and the channel selector MUX01 is a two-channel selector, when the MUX01 receives a control signal of BMC 1, the input terminal and the output terminal corresponding to the control signal in the MUX01 are controlled to be conducted, so as to implement connection between the pull-up power source V corresponding to the control signal and the output power terminal of the isolation unit 2.
In general, different NVMe hard disks 5 have two situations during I2C communication, one is not connected to the pull-up resistor R, the other is to connect one end of the pull-up resistor R with a corresponding resistance value to the output signal end of the isolation unit 2, and the other end of the connected pull-up resistor R is connected to the connected pull-up power source V. Furthermore, it is known that the second channel selecting unit 4 is used to select a pull-up resistor R and a pull-up power source V to connect with the output signal end of the isolating unit 2, and therefore, the implementation of the second channel selecting unit 4 in this embodiment mainly includes two ideas, one is that the whole second channel selecting unit 4 and all pull-up resistors R are connected to the output end of the first channel selecting unit 3 as a whole to determine the connected pull-up power source V, and then according to the received control signal of the BMC 1, the internal channel of the second channel selecting unit 4 is controlled to be connected to the pull-up resistor R with the corresponding resistance value; secondly, a circuit completely independent of the first channel selection unit 3 is arranged, the selection of the pull-up power supply V is ensured to be synchronous with the first channel selection unit 3, and a specific circuit connection relation is set.
Specifically, the embodiment is implemented by taking two pull-up resistors 4.7k Ω and 10k Ω as an example, according to a first idea, the I2C protocol circuit has the following implementation manners:
if the pull-up resistors R are located between the first channel selection unit 3 and the second channel selection unit 4, namely the first ends of all the pull-up resistors R are connected with the output end of the first channel selection unit 3, and the second ends of all the pull-up resistors R are respectively connected with the plurality of input ends of the second channel selection unit 4 one by one; the output end of the second channel selection unit 4 is connected with the output signal end of the isolation unit 2.
Further, the second channel selection unit 4 further includes a blank input terminal for use in the case that the NVMe hard disk 5 does not need the pull-up resistor R.
In this case, as shown in fig. 2, the second channel selecting unit 4 is a channel selector MUX 02; the channel selector includes: the pull-up resistor R comprises an input end which is connected with the air, and a plurality of input ends which are connected with second ends of the pull-up resistors R one by one.
Alternatively, as shown in fig. 3, the second channel selecting unit 4 includes a first channel selector MUX1 and a second channel selector MUX 2; a plurality of input terminals of the first channel selector MUX1 are connected to second terminals of the pull-up resistors R one by one; a first input end of the second channel selector MUX2 is connected to an output end of the first channel selector MUX1, a second input end is connected to the ground, and an output end is connected to an output signal end of the isolation unit 2.
If the pull-up resistor R is located inside the second channel selection unit 4, one implementation is shown in FIG. 4: the second channel selection unit 4 includes a first channel selector MUX1 and a second channel selector MUX 2; a first input end of the second channel selector MUX2 is connected with an output end of the first channel selection unit 3, a second input end of the second channel selector MUX2 is connected in a null mode, and an output end of the second channel selector MUX2 is connected with first ends of all the pull-up resistors R; a plurality of input terminals of the first channel selector MUX1 are connected to second terminals of the plurality of pull-up resistors R one by one, and an output terminal thereof is connected to an output signal terminal of the isolation unit 2.
Considering another idea, when the second channel selection unit 4 selects the pull-up power source V independently from the first channel selection unit 3, one implementation is shown in fig. 5, where the second channel selection unit 4 includes a third channel selector MUX3 and a fourth channel selector MUX 4; all the pull-up power sources V are respectively connected to a plurality of input ends of the third channel selector MUX3 one by one; the output end of the third channel selector MUX3 is connected with the first ends of all the pull-up resistors R; second ends of all the pull-up resistors R are respectively connected with a plurality of input ends of the fourth channel selector MUX4 one by one; the output end of the fourth channel selector MUX4 is connected with the output signal end of the isolation unit; the third channel selector MUX3 may further include a dead-end input, and/or the fourth channel selector MUX4 may further include a dead-end input. Fig. 5 is an example of the third channel selector MUX3 including a dead-end input, and in addition, the third channel selector MUX3 and the fourth channel selector MUX4 may be implemented with only one channel selector including a dead-end input, or both channels may include a dead-end input, which is not limited herein.
In another mode, as shown in fig. 6, the first channel selecting unit 3 is a four-channel input and two-channel output synchronous selector MUX0, and the second channel selecting unit 4 includes MUX5, MUX6 and MUX7, wherein MUX5 and MUX6 are two-channel selectors, one input end of each two-channel selector is connected to a corresponding pull-up power source V, the other input end is connected to the ground, the output end is connected to the input end of MUX0, the first ends of all pull-up resistors R are connected to the second output end of MUX0, the second ends of pull-up resistors R are connected to the input ends of MUX7, and the output end of MUX7 is connected to the output signal end of the isolating unit 2.
It is understood that the above examples in this embodiment specifically describe the positional relationship between the channel selector or the second channel selecting unit 4 and the pull-up resistor R, but actually, the channel selector with the pull-up resistor R connected to the lower level is taken as an integral module, which is outlined by a dashed line in the figure, the input and output of the integral module can be inverted, and the corresponding pull-up resistor R can be ensured to enter the channel by controlling the conducting channel in the channel selector. As shown in fig. 7, is the flip scheme of fig. 2. However, it should be noted that the interface that is originally idle is no longer connected to the circuit.
It will be appreciated that an empty port may not be present in the channel switch, and that the second channel selection unit 4 may simply disconnect all channels without pulling up resistors.
Therefore, in addition to the above-described circuit connection scheme, any scheme that can realize that a specific pull-up resistor R is connected to the pull-up power source V and the output signal terminal of the isolation unit 2 through a channel selector falls within the protection scope of the present application.
Correspondingly, the embodiment of the present application further discloses an I2C environment control method for NVMe hard disks, which is applied to the BMC of the I2C protocol circuit of any one of the NVMe hard disks, and as shown in fig. 8, the I2C environment control method includes:
s1: acquiring working environment information of the NVMe hard disk;
s2: and selecting the conduction channels of the first channel selection unit and the second channel selection unit according to the working environment information so that an output power supply end of the isolation unit is connected with a pull-up power supply corresponding to the working environment information, and an output signal end of the isolation unit is connected with a pull-up resistor corresponding to the working environment information or not connected with the pull-up resistor.
In the I2C protocol circuit, when the communication relation between BMC and NVMe hard disk is established through the isolation unit, the pull-up power supply and the pull-up resistor of the isolation unit can be flexibly selected through the first channel selection unit and the second channel selection unit, so that multiple I2C protocol circuits with flexible adaptation and reliable communication are provided for the NVMe hard disk.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The I2C protocol circuit and the I2C environment control method of the NVMe hard disk provided by the present invention are introduced in detail, and a specific example is applied in the present document to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims (10)

1. An I2C protocol circuit of NVMe hard disk, comprising: BMC, a plurality of pull-up power supplies, a plurality of pull-up resistors, isolation unit, first channel selection unit and second channel selection unit, wherein:
the input signal end of the isolation unit is connected with the BMC;
the input power end of the isolation unit is connected with a preset power supply;
an output power supply end of the isolation unit is connected with any pull-up power supply through the first channel selection unit;
the output signal end of the isolation unit is connected with any pull-up resistor through the second channel selection unit and then connected with any pull-up power supply, or is disconnected with all the pull-up resistors and all the pull-up power supplies through the second channel selection unit;
and the output signal end of the isolation unit is also connected with the NVMe hard disk.
2. The I2C protocol circuit of claim 1, wherein a plurality of input terminals of the first channel selection unit are connected to a plurality of the pull-up power supplies one by one, and output terminals are connected to an output power supply terminal of the isolation unit.
3. The I2C protocol circuit of claim 2,
the first ends of all the pull-up resistors are connected with the output end of the first channel selection unit;
second ends of all the pull-up resistors are respectively connected with the plurality of input ends of the second channel selection unit one by one;
and the output end of the second channel selection unit is connected with the output signal end of the isolation unit.
4. The I2C protocol circuit of claim 3, wherein the second channel selection unit further comprises a null input.
5. The I2C protocol circuit of claim 4, wherein the second channel selection unit is a channel selector;
the channel selector includes: the input end of the air connection and the input ends are connected with the second ends of the pull-up resistors one by one.
6. The I2C protocol circuit of claim 4, wherein the second channel selection unit comprises a first channel selector and a second channel selector;
a plurality of input ends of the first channel selector are connected with second ends of the pull-up resistors one by one;
the first input end of the second channel selector is connected with the output end of the first channel selector, the second input end of the second channel selector is in idle connection, and the output end of the second channel selector is connected with the output signal end of the isolation unit.
7. The I2C protocol circuit of claim 2, wherein the second channel selection unit comprises a first channel selector and a second channel selector;
the first input end of the second channel selector is connected with the output end of the first channel selection unit, the second input end of the second channel selector is in idle connection, and the output end of the second channel selector is connected with the first ends of all the pull-up resistors;
and a plurality of input ends of the first channel selector are connected with second ends of the pull-up resistors one by one, and output ends of the first channel selector are connected with output signal ends of the isolation units.
8. The I2C protocol circuit of claim 2, wherein the second channel selection unit comprises a third channel selector and a fourth channel selector;
all the pull-up power supplies are respectively connected with the plurality of input ends of the third channel selector one by one;
the output end of the third channel selector is connected with the first ends of all the pull-up resistors;
second ends of all the pull-up resistors are respectively connected with the plurality of input ends of the fourth channel selector one by one;
the output end of the fourth channel selector is connected with the output signal end of the isolation unit;
the third channel selector further comprises a null-connect input, and/or the fourth channel selector further comprises a null-connect input.
9. The I2C protocol circuit of any one of claims 1-8, wherein the BMC is configured to:
acquiring working environment information of the NVMe hard disk;
and selecting the conduction channels of the first channel selection unit and the second channel selection unit according to the working environment information, so that an output power supply end of the isolation unit is connected with the pull-up power supply corresponding to the working environment information, and an output signal end of the isolation unit is connected with the pull-up resistor corresponding to the working environment information or is not connected with the pull-up resistor.
10. An I2C environment control method for NVMe hard disks, which is applied to the BMC of the I2C protocol circuit of the NVMe hard disks of any one of claims 1 to 9, the I2C environment control method comprising:
acquiring working environment information of the NVMe hard disk;
and selecting the conduction channels of the first channel selection unit and the second channel selection unit according to the working environment information so that an output power supply end of the isolation unit is connected with a pull-up power supply corresponding to the working environment information, and an output signal end of the isolation unit is connected with a pull-up resistor corresponding to the working environment information or is not connected with the pull-up resistor.
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Publication number Priority date Publication date Assignee Title
CN112954492A (en) * 2021-01-26 2021-06-11 北京源启先进微电子有限公司 Selection device applied to multiplexer and multiplexer

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CN107390575B (en) * 2017-07-12 2019-06-28 郑州云海信息技术有限公司 A kind of configurable low speed PAD, there is the restructural interface BMC chip of intelligence
CN112347009A (en) * 2020-09-24 2021-02-09 天津市英贝特航天科技有限公司 Device for realizing hard disk storage shared by multiple processors
CN215219687U (en) * 2021-05-20 2021-12-17 山东英信计算机技术有限公司 ROT connector and Dediprog connector multiplexing automatic switching device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112954492A (en) * 2021-01-26 2021-06-11 北京源启先进微电子有限公司 Selection device applied to multiplexer and multiplexer

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