CN113945286B

CN113945286B - Preparation method of CMOS infrared detector with solid column and infrared detector

Info

Publication number: CN113945286B
Application number: CN202111191849.8A
Authority: CN
Inventors: 翟光杰; 武佩; 潘辉; 翟光强
Original assignee: Beijing North Gaoye Technology Co ltd
Current assignee: Beijing North Gaoye Technology Co ltd
Priority date: 2021-10-13
Filing date: 2021-10-13
Publication date: 2023-01-10
Anticipated expiration: 2041-10-13
Also published as: CN113945286A

Abstract

The invention relates to a preparation method of a CMOS infrared detector with a solid column and the infrared detector, wherein the preparation method comprises the steps of preparing a CMOS measuring circuit system and a CMOS infrared sensing structure by adopting a CMOS process; preparing a CMOS infrared sensing structure comprises preparing a first metal interconnection layer on top metal of a CMOS measurement circuit system by adopting an RDL (remote description language) process or taking the top metal of the CMOS measurement circuit system as the first metal interconnection layer; preparing a first interconnection column by adopting a through hole process and a CMP (chemical mechanical polishing) planarization process; depositing a second metal interconnection layer over the first interconnection pillar to form a beam structure; depositing a third metal interconnection layer to form a second interconnection column; a fourth metal interconnect layer and a second dielectric layer are deposited to form an absorber plate. By the technical scheme, the problems of low performance, low pixel scale, low yield and poor consistency of the traditional MEMS process infrared detector are solved, and the performance of the infrared detector is optimized.

Description

Preparation method of CMOS infrared detector with solid column and infrared detector

Technical Field

The invention relates to the technical field of infrared detection, in particular to a preparation method of a CMOS infrared detector with solid columns and the infrared detector.

Background

The fields of monitoring markets, vehicle and auxiliary markets, home markets, intelligent manufacturing markets, mobile phone applications and the like have strong demands on uncooled high-performance chips, certain requirements are provided for the performance of the chips, the performance consistency and the product price, the potential demands of more than one hundred million chips are predicted every year, and the current process scheme and architecture cannot meet the market demands.

At present, an infrared detector adopts a mode of combining a measuring circuit and an infrared sensing structure, the measuring circuit is prepared by adopting a Complementary Metal-Oxide-Semiconductor (CMOS) process, and the infrared sensing structure is prepared by adopting a Micro-Electro-Mechanical System (MEMS) process, so that the following problems are caused:

(1) The infrared sensing structure is prepared by adopting an MEMS (micro-electromechanical systems) process, polyimide is used as a sacrificial layer, and the infrared sensing structure is incompatible with a CMOS (complementary metal oxide semiconductor) process.

(2) Polyimide is used as a sacrificial layer, so that the problem that the vacuum degree of a detector chip is influenced due to incomplete release exists, the growth temperature of a subsequent film is limited, and the selection of materials is not facilitated.

(3) Polyimide can cause the height of the resonant cavity to be inconsistent, and the working dominant wavelength is difficult to ensure.

(4) The control of the MEMS process is far worse than that of the CMOS process, and the performance consistency and the detection performance of the chip are restricted.

(5) MEMS has low productivity, low yield and high cost, and can not realize large-scale batch production.

(6) The existing process capability of the MEMS is not enough to support the preparation of a higher-performance detector, nor is it enough to support a smaller line width and a thinner film thickness, which is not favorable for realizing the miniaturization of a chip.

Disclosure of Invention

In order to solve the technical problems or at least partially solve the technical problems, the invention provides a preparation method of a CMOS infrared detector with a solid column and the infrared detector, which solve the problems of low performance, low pixel scale, low yield and poor consistency of the traditional MEMS process infrared detector and optimize the performance of the infrared detector.

In a first aspect, the present invention provides a method for manufacturing a CMOS infrared detector having a solid pillar, including:

providing a substrate;

preparing a CMOS measuring circuit system on the substrate by adopting a CMOS process;

directly preparing a CMOS infrared sensing structure on the CMOS measuring circuit system by adopting a CMOS process;

the CMOS infrared sensing structure is directly prepared on the CMOS measuring circuit system by adopting a CMOS process, and comprises the following steps:

step 1, preparing a first metal interconnection layer on top metal of the CMOS measuring circuit system by adopting an RDL (remote description language) process; or, the top metal of the CMOS measuring circuit system is used as a first metal interconnection layer; wherein the first metal interconnection layer is a reflective layer;

step 2, depositing a first dielectric layer; wherein the first dielectric layer is a closed release isolation layer;

step 3, depositing a first sacrificial layer on the first dielectric layer;

step 4, preparing a first interconnection column by adopting a through hole process and a CMP (chemical mechanical polishing) planarization process;

step 5, depositing a second metal interconnection layer above the first interconnection column, and etching the second metal interconnection layer to form a first patterned electrode structure so as to form a beam structure;

step 6, depositing a third metal interconnection layer, and etching the third metal interconnection layer to form a second interconnection column;

step 7, depositing to form a second sacrificial layer;

step 8, depositing a fourth metal interconnection layer and a second dielectric layer, and etching the fourth metal interconnection layer to form a second patterned electrode structure so as to form an absorption plate; the second dielectric layer is a heat sensitive dielectric layer.

In a second aspect, an embodiment of the present invention further provides an infrared detector, which is manufactured by the method for manufacturing a CMOS infrared detector having a solid pillar according to the first aspect, and the infrared detector includes:

the CMOS measurement circuitry and the CMOS infrared sensing structure;

at least one layer of the closed release isolation layer is arranged above the CMOS measuring circuit system;

the CMOS manufacturing process of the CMOS infrared sensing structure comprises a metal interconnection process, a through hole process, an IMD (in-mold decoration) process and an RDL (remote description language) process, wherein the CMOS infrared sensing structure comprises at least three metal interconnection layers, at least four dielectric layers and a plurality of interconnection through holes, the metal interconnection layers at least comprise a reflecting layer and two electrode layers, and the dielectric layers at least comprise one closed release isolation layer, two sacrificial layers and a heat sensitive dielectric layer; the thermal sensitive medium layer is used for converting temperature change corresponding to infrared radiation absorbed by the thermal sensitive medium layer into resistance change, and further converting an infrared target signal into a signal capable of realizing electric reading through the CMOS measuring circuit system;

the CMOS infrared sensing structure comprises a resonant cavity formed by the reflecting layer and the heat sensitive medium layer and a suspended micro-bridge structure for controlling heat transfer, the suspended micro-bridge structure comprises at least one layer of beam structure and at least one layer of absorption plate, and the beam structure is positioned on one side of the absorption plate close to or far away from the CMOS measuring circuit system;

the first interconnection column is arranged between the reflecting layer and the beam structure and is directly and electrically connected with the supporting base in the reflecting layer and the corresponding beam structure, and the beam structure is electrically connected with the CMOS measuring circuit system through the first interconnection column and the supporting base;

the absorption plate is electrically connected with the beam structure through the second interconnection column, the second interconnection column is directly electrically connected with the corresponding absorption plate and the corresponding beam structure, and the absorption plate is used for converting infrared signals into electric signals and is electrically connected with the corresponding first interconnection column through the second interconnection column and the corresponding beam structure.

Compared with the prior art, the technical scheme provided by the embodiment of the invention has the following advantages:

the embodiment of the invention realizes the integrated preparation of the CMOS measuring circuit system and the CMOS infrared sensing structure on the CMOS production line by utilizing the CMOS process, compared with the MEMS process, the CMOS has no process compatibility problem, the technical difficulty of the MEMS process is solved, the transportation cost can be reduced by adopting the CMOS process production line process to prepare the infrared detector, and the risk caused by the problems of transportation and the like is reduced; the infrared detector prepared by the integrated CMOS process can realize the aims of high yield, low cost, high yield and large-scale integrated production of chips, and provides a wider application market for the infrared detector; the infrared detector based on the CMOS process can realize smaller size and thinner film thickness, so that the infrared detector has larger duty ratio, lower thermal conductivity and smaller thermal capacity, and the infrared detector has higher detection sensitivity, longer detection distance and better detection performance; the infrared detector based on the CMOS process can make the pixel size of the detector smaller, realize smaller chip area under the same array pixel, and is more beneficial to realizing the miniaturization of a chip; the infrared detector based on the CMOS process has the advantages of mature process production line, higher process control precision, better design requirement achievement, better product consistency, better circuit adjustment performance and better industrial batch production.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.

Fig. 1 is a schematic flowchart of a method for manufacturing a CMOS infrared detector having solid pillars according to an embodiment of the present invention;

FIG. 2 is a schematic perspective view of an infrared detector pixel provided in an embodiment of the present invention;

fig. 3 is a schematic flow chart of a method for manufacturing a CMOS infrared sensing structure according to an embodiment of the present invention;

fig. 4a to 4e are schematic structural diagrams corresponding to a process of manufacturing a first metal interconnection layer according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram corresponding to another manufacturing process of a first metal interconnection layer according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram corresponding to a process for preparing a first dielectric layer according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram corresponding to another process for preparing a first dielectric layer according to an embodiment of the present invention;

fig. 8a to 8b are schematic structural diagrams corresponding to another process for preparing a first dielectric layer according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram corresponding to a process of preparing a first sacrificial layer according to an embodiment of the present invention;

FIGS. 10a-10b are schematic structural diagrams illustrating a first interconnect pillar according to an embodiment of the present invention;

FIGS. 11a-11c are schematic structural diagrams illustrating another alternative first interconnect pillar fabrication process in accordance with embodiments of the present invention;

FIGS. 12a-12d are schematic structural diagrams corresponding to another process for fabricating a first interconnect pillar according to an embodiment of the invention;

FIGS. 13a-13d are schematic structural diagrams corresponding to another process for fabricating a first interconnect pillar in accordance with an embodiment of the present invention;

FIGS. 14a-14b are schematic structural diagrams illustrating another alternative first interconnect pillar fabrication process according to embodiments of the present invention;

15a-15c are schematic structural diagrams corresponding to a process for manufacturing a beam structure according to an embodiment of the present invention;

FIGS. 16a-16c are schematic structural diagrams illustrating a second pillar according to an embodiment of the present invention;

fig. 17 is a schematic structural diagram of a second sacrificial layer according to a manufacturing process of the second sacrificial layer in an embodiment of the present invention;

FIGS. 18a-18c are schematic structural diagrams corresponding to another second sacrificial layer manufacturing process according to an embodiment of the disclosure;

FIGS. 19a-19b are schematic views showing the corresponding structure of the manufacturing process of an absorbent plate according to an embodiment of the present invention;

FIGS. 20a-20b are schematic views showing the structure of another absorbing plate according to an embodiment of the present invention;

FIGS. 21a-21d are schematic structural diagrams corresponding to another process for manufacturing an absorbent panel according to an embodiment of the present invention;

FIG. 22 is a schematic structural diagram illustrating another exemplary process for manufacturing an absorbent panel according to an embodiment of the present invention;

fig. 23 is a schematic cross-sectional structure diagram of an infrared detector pixel provided in an embodiment of the present invention;

FIG. 24 is a schematic cross-sectional view of another infrared detector pixel provided in accordance with an embodiment of the present invention;

fig. 25 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in an embodiment of the present invention;

fig. 26 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in an embodiment of the invention.

Detailed Description

In order that the above objects, features and advantages of the present invention may be more clearly understood, a solution of the present invention will be further described below. It should be noted that the embodiments and features of the embodiments of the present invention may be combined with each other without conflict.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those described herein; it is to be understood that the embodiments described in this specification are only some embodiments of the invention, and not all embodiments.

Fig. 1 is a schematic flow chart of a method for manufacturing a CMOS infrared detector having a solid pillar according to an embodiment of the present invention. The preparation method of the CMOS infrared detector with the solid column can be applied to application scenes needing to prepare the infrared detector. As shown in fig. 1, the method for manufacturing a CMOS infrared detector having solid pillars includes:

s101, providing a substrate.

Illustratively, the substrate may be a silicon substrate.

S102, preparing a CMOS measuring circuit system on the substrate by adopting a CMOS process.

Fig. 2 is a schematic three-dimensional structure diagram of an infrared detector pixel provided in an embodiment of the present invention. As shown in fig. 2, the CMOS measurement circuitry 1 is fabricated on a substrate (not shown in fig. 2) using a CMOS process, and the CMOS measurement circuitry 1 may include transistors, resistors, and capacitors.

In some embodiments, the CMOS measurement circuitry 1 is fabricated on the substrate using a CMOS process, and the process layers in the CMOS measurement circuitry 1 may be fabricated using an oxidation process, a deposition process, and a doping process, the regions may be located using a photolithography process to transfer the digitized pattern to the CMOS measurement circuitry 1, and the material in the set regions in the CMOS measurement circuitry 1 may be removed using an etching process.

Specifically, the oxidation process refers to the oxidation growth of a silicon oxide film of a desired thickness in the CMOS measurement circuit system 1 by oxidizing a silicon substrate under a high temperature, oxygen or moisture atmosphere. The Deposition process refers to growing a metal layer or a dielectric material layer in the CMOS measurement circuit system 1 by using a CVD (Chemical Vapor Deposition) process or a PVD (Physical Vapor Deposition) process, for example, a silicon oxide film or a silicon nitride film in the CMOS measurement circuit system 1 may be grown by using LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition), and a metal film such as aluminum, titanium, or nickel may be prepared by using evaporation, sputtering, or ion plating. The doping process may be a diffusion doping process or an ion implantation doping process to dope certain amounts of other elements into selected regions of the silicon substrate in the CMOS measurement circuitry 1 to change the conductivity type, resistivity or form PN junctions of the semiconductor.

The lithography process is used to locate the zones on the wafer surface and within the wafer to produce the required patterns and dimensions to effect the transfer of the digitised pattern to the wafer, i.e. to the CMOS measurement circuitry 1. The etching process includes a wet etching process and a dry etching process, and a suitable method and a suitable etching liquid or etching gas can be adopted to perform surface uniform removal or selective partial removal according to the thicknesses of the dielectric layer and the metal layer to be etched, that is, the material in a set area in the CMOS measurement circuit system 1 can be removed by adopting the etching process. It should be noted that, the embodiment of the present invention does not specifically limit the specific etching process, and the matching etching process may be selected according to the thin film material to be etched.

And S103, directly preparing the CMOS infrared sensing structure on the CMOS measuring circuit system by adopting a CMOS process.

Specifically, the infrared detector comprises a plurality of infrared detector pixels arranged in an array, as shown in fig. 2, the infrared detector pixels based on the CMOS process comprise a CMOS measurement circuit system 1 and a CMOS infrared sensing structure 2, and the CMOS infrared sensing structure 2 is directly prepared on the CMOS measurement circuit system 1 by using the CMOS process, that is, both the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are prepared by using the CMOS process.

Specifically, the CMOS infrared sensing structure 2 is used for converting an external infrared signal into an electric signal and transmitting the electric signal to the CMOS measuring circuit system 1, and the CMOS measuring circuit system 1 reflects temperature information of a corresponding infrared signal according to the received electric signal, so that the temperature detection function of the infrared detector is realized. The CMOS measuring circuit system 1 and the CMOS infrared sensing structure 2 are both prepared by using a CMOS process, and the CMOS infrared sensing structure 2 is directly prepared on the CMOS measuring circuit system 1, namely, the CMOS measuring circuit system 1 is prepared by adopting the CMOS process, and then the CMOS infrared sensing structure 2 is continuously prepared by utilizing the CMOS process by utilizing parameters of various processes compatible with a CMOS production line and the production line.

Therefore, the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are integrally prepared on the CMOS production line by utilizing the CMOS process, compared with the MEMS process, the CMOS process does not have the process compatibility problem, the technical difficulty of the MEMS process is solved, the transportation cost can be reduced by adopting the CMOS production line process to prepare the infrared detector, and the risk caused by the transportation problem and the like is reduced; the infrared detector prepared by the integrated CMOS process can realize the aims of high yield, low cost, high yield and large-scale integrated production of chips, and provides a wider application market for the infrared detector; the infrared detector based on the CMOS process can realize smaller size and thinner film thickness, so that the infrared detector has larger duty ratio, lower thermal conductivity and smaller thermal capacity, and the infrared detector has higher detection sensitivity, longer detection distance and better detection performance; the infrared detector based on the CMOS process can make the pixel size of the detector smaller, realize smaller chip area under the same array pixel, and is more beneficial to realizing the miniaturization of a chip; the infrared detector based on the CMOS process has the advantages of mature process production line, higher process control precision, better design requirement achievement, better product consistency, better circuit adjustment performance and more benefit to industrialized batch production.

Fig. 3 is a schematic flow chart of a method for manufacturing a CMOS infrared sensing structure according to an embodiment of the present invention. The preparation method of the CMOS infrared sensing structure can be applied to application scenes in which the CMOS infrared sensing structure in an infrared detector needs to be prepared. As shown in fig. 3, the method for manufacturing a CMOS infrared sensing structure, that is, the CMOS infrared sensing structure is directly manufactured on a CMOS measurement circuit system by using a CMOS process, includes:

s1, preparing a first metal interconnection layer on top metal of a CMOS measuring circuit system by using an RDL (remote description language) process; or, the top metal of the CMOS measuring circuit system is used as a first metal interconnection layer; wherein the first metal interconnection layer is a reflective layer.

Fig. 4a to 4e are schematic structural diagrams corresponding to a manufacturing process of a first metal interconnection layer according to an embodiment of the present invention. As shown in fig. 4a-4e, a first metal interconnection layer 4 may be prepared on the top metal 3 of the CMOS measurement circuit system 1 by using an RDL process, which is a redistribution layer process, specifically, a layer of metal is re-distributed on the top metal 3 of the circuit and is electrically connected to the top metal 3 of the circuit, for example, a tungsten pillar or a copper pillar, a reflective layer in an infrared detector may be prepared on the top metal 3 of the CMOS measurement circuit system 1 by using an RDL process, a reflective plate 41 in the reflective layer is used for reflecting infrared rays, and a supporting pedestal 42 in the reflective layer is electrically connected to the top metal 3 of the CMOS measurement circuit system 1.

The first metal interconnection layer 4 is prepared on the top metal 3 of the CMOS measurement circuit system 1 by using RDL process, as shown in fig. 4a, a first insulating layer 13 is first deposited on the CMOS measurement circuit system 1, and the surface of the first insulating layer 13 is processed by using CMP (Chemical Mechanical Polishing) process to planarize the upper surface of the first insulating layer 13, so as to optimize the planarization degree of the subsequently formed film layer.

As shown in fig. 4b, a first via 14 is etched on the planarized first insulating layer 13, for example, a plurality of first vias 14 may be etched on the first insulating layer 13, and the finally formed first metal interconnection layer 4, i.e., the reflective layer, includes a supporting pedestal 42, where the supporting pedestal 42 needs to be electrically connected to a corresponding metal structure in the CMOS measurement circuit system 1, so that as shown in fig. 4b, a plurality of first vias 14 may be etched corresponding to the position of the metal structure in the CMOS measurement circuit system 1 that needs to be electrically connected to the supporting pedestal 42.

Tungsten metal is deposited to fill the first via hole 14 using a PVD process, or copper metal is deposited to fill the first via hole 14 using an Electro Chemical Plating (ECP) process. In some embodiments, as shown in fig. 4c, before depositing metal to fill the first via hole 14, an adhesion layer 141 may be deposited in the first via hole 14, a material of the adhesion layer 141 may include at least one of titanium, titanium nitride, tantalum, or tantalum nitride, as shown in fig. 4d, and then metal tungsten is deposited by PVD process to fill the first via hole 14 to form the metal pillar 142. For example, the finally formed adhesion layer 141 may cover the entire infrared detector pixel area as shown in fig. 4c, and the finally formed adhesion layer 141 may also cover only the bottom and the sidewall of the first through hole 14 as shown in fig. 4 d.

Specifically, the adhesion layer 141 can enhance the connection performance between the metal pillar 142 in the first through hole 14 and the CMOS measurement circuit system 1, including the mechanical connection performance of the enhancer, improve the structural stability, and also include the electrical connection performance of the enhancer, reduce the contact resistance, reduce the loss during the transmission of the electrical signal, and improve the infrared detection performance of the infrared detector. In addition, the adhesion layer 141 is arranged to surround the metal column 142 in the first through hole 14, so that the contact area between the adhesion layer 141 and the metal column 142 in the first through hole 14 can be increased, which is equivalent to widening a transmission channel of an electrical signal, and reducing the transmission resistance of the metal column 142 in the first through hole 14, thereby further reducing the transmission loss of the electrical signal and improving the infrared detection performance of the infrared detector.

As shown in fig. 4d, after the metal tungsten is deposited by using a PVD process to fill the first via 14 to form the metal pillar 142, the surface of the first via 14 is processed by using a CMP process to planarize the metal pillar 142 in the first via 14 and the surface of the surrounding dielectric layer, in preparation for the subsequent formation of the first metal interconnection layer 4.

As shown in fig. 4e, a metal layer is then deposited on the surface of the first via 14, and the metal layer is etched to form the first metal interconnect layer 4, i.e. to form the reflective layer. Specifically, the reflective layer 4 includes a reflective plate 41 and a support base 42, the reflective plate 41 and two support bases 42 located at both sides of the reflective plate 41 are shown in fig. 4e, and the metal layer is etched to form the patterned reflective plate 41 and the support bases 42. A part of the reflective layer 4 serves as a dielectric medium for electrically connecting the subsequently formed first interconnection column with the CMOS measurement circuit system 1, that is, the supporting base 42, and the reflective plate 41 serves to reflect infrared rays to the heat sensitive medium layer in the CMOS infrared sensor structure, and cooperates with the resonant cavity formed between the reflective layer and the heat sensitive medium layer to realize secondary absorption of infrared rays, so as to improve the infrared absorption rate of the infrared detector and optimize the infrared detection performance of the infrared detector.

Fig. 5 is a schematic structural diagram corresponding to another manufacturing process of a first metal interconnection layer according to an embodiment of the present invention. As shown in fig. 5, the top metal 3 of the CMOS measurement circuitry 1 may also be used as the first metal interconnection layer 4, and the top metal 3 of the CMOS measurement circuitry 1 may also be etched to form a reflective plate 41 and a supporting base 42, where the reflective plate 41 and two supporting bases 42 on both sides of the reflective plate 41 are shown in fig. 5. The top insulating layer, i.e. the first insulating layer 13, of the CMOS measurement circuit system 1 is used to cover the top metal 3 of the CMOS measurement circuit system 1, and the CMP process is used to process the surface of the CMOS measurement circuit system 1, i.e. the upper surface of the top insulating layer 13 of the CMOS measurement circuit system 1, so as to planarize the upper surface of the top insulating layer 13 of the CMOS measurement circuit system 1, thereby optimizing the planarization degree of the subsequently formed film layer.

S2, depositing a first dielectric layer; wherein, the first dielectric layer is a closed release isolation layer.

Fig. 6 is a schematic structural diagram corresponding to a process for preparing a first dielectric layer according to an embodiment of the present invention, and fig. 7 is a schematic structural diagram corresponding to a process for preparing another first dielectric layer according to an embodiment of the present invention. Referring to fig. 6 and 7, the structure shown in fig. 6 corresponds to the structure shown in fig. 4a to 4e, and the structure shown in fig. 7 corresponds to the structure shown in fig. 5, step 2 may be performed after step 1, that is, first, a first metal interconnection layer 4, that is, a reflective layer is formed, and then, a first dielectric layer 5 is formed on the first metal interconnection layer 4, for example, a CVD process may be used to deposit the first dielectric layer 5, that is, a hermetic release isolation layer, on the first metal interconnection layer 4. In addition, for the structures shown in fig. 5 and 7, the first dielectric layer 5 is formed on the reflective layer, and the first dielectric layer 5 may be formed on the top insulating layer 13 of the CMOS measurement circuitry 1.

Fig. 8a to 8b are schematic structural diagrams corresponding to another process for preparing a first dielectric layer according to an embodiment of the present invention. As shown in fig. 8a-8b, when step 1 is to prepare a first metal interconnection layer 4 on a top metal 3 of a CMOS measurement circuit system 1 by using an RDL process, corresponding to the structure shown in fig. 4a-4e, step 2 may be performed before step 1, that is, a first dielectric layer 5 is formed first, and then the first metal interconnection layer 4 is formed on the first dielectric layer 5. Specifically, as shown in fig. 8a, the surface of the CMOS measurement circuitry 1 may be processed by a CMP process, for example, the upper surface of the top insulating layer 13 of the CMOS measurement circuitry 1 may be processed by a CMP process. As shown in fig. 8b, a first dielectric layer 5 is deposited on the surface of the CMOS measurement circuitry 1 by using a CVD process, for example, the first dielectric layer 5 is deposited on the surface of the top insulating layer 13 of the CMOS measurement circuitry 1 by using a CVD process, and then the steps shown in fig. 4a to fig. 4e are performed on the first dielectric layer 5 to form the first metal interconnection layer 4. Therefore, since the first metal interconnection layer 4, i.e., the reflection layer, realizes the reflection of infrared light on the first dielectric layer 5, i.e., the upper side of the closed release isolation layer, so as to realize the secondary absorption of the heat-sensitive dielectric layer on the infrared light, the structure shown in fig. 8a-8b is provided with the closed release isolation layer below the reflection layer, so that the infrared reflection effect of the reflection layer is not influenced no matter how the thickness of the closed isolation layer is set.

Illustratively, the material constituting the first dielectric layer 5 includes at least one of silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, silicon germanium, amorphous carbon or aluminum oxide, and the first dielectric layer 5 is used for protecting the CMOS measurement circuitry 1 from process effects during the release etching process for fabricating the CMOS infrared sensing structure 2.

And S3, depositing a first sacrificial layer on the first dielectric layer.

Fig. 9 is a schematic structural diagram corresponding to a manufacturing process of a first sacrificial layer according to an embodiment of the present invention. As shown in fig. 9, a first sacrificial layer 6 is deposited on the first dielectric layer 5 and a CMP process is performed on the upper surface of the first sacrificial layer 6 to optimize the planarization degree of the film layer above the first sacrificial layer 6, and the preparation process shown in fig. 9 is applicable to the structure shown in fig. 7 and fig. 8a-8 b.

In some embodiments, the first sacrificial layer 6 may be composed of silicon oxide prepared using a thermal oxidation process or a CVD process. Specifically, the infrared detector takes silicon oxide as a sacrificial layer, the silicon oxide is completely compatible with a CMOS (complementary metal oxide semiconductor) process, the preparation process is simple and easy to control, the CMOS process does not have the problem that the vacuum degree of a detector chip is influenced due to incomplete release of polyimide of the sacrificial layer, the subsequent film growth temperature is not limited by the material of the sacrificial layer, the multilayer process design of the sacrificial layer can be realized, the process is not limited, the sacrificial layer can be easily utilized to realize planarization, and the process difficulty and possible risks are reduced.

And S4, preparing the first interconnection column by adopting a through hole process and a CMP (chemical mechanical polishing) planarization process.

FIGS. 10a-10b are schematic structural diagrams corresponding to a first interconnection column fabrication process according to an embodiment of the invention. The first interconnection pillar 7 is prepared using a via process, and the first sacrificial layer 6 may be etched to form a pillar-shaped via hole 16 as shown in fig. 10a, for example, the first sacrificial layer 6 and the first dielectric layer 5 may be etched to form a pillar-shaped via hole 16 to expose the support pedestal 42. As shown in fig. 10b, metal tungsten or metal copper is deposited within the pillar via 16 and CMP planarized to form the first interconnection pillar 7, and the solid metal structure 71 constituting the first interconnection pillar 7 is electrically connected to the corresponding support pedestal 42. Specifically, the infrared detector is provided with the first interconnection column 7 which is composed of the solid metal structure 71, the side wall of the solid metal structure 71 is in contact with the first sacrificial layer 6, and the material of the solid metal structure 71 which constitutes the first interconnection column 7 comprises at least one of tungsten or copper, so that the preparation process of the first interconnection column 7 is simple and easy to realize, and the preparation difficulty of the whole infrared detector is favorably reduced.

FIGS. 11a-11c are schematic structural diagrams illustrating another alternative first pillar interconnect fabrication process according to embodiments of the present invention. The first interconnection stud 7 is prepared by a via process, and as shown in fig. 11a, the first sacrificial layer 6 may be etched to form a columnar via 16, for example, the first sacrificial layer 6 and the first dielectric layer 5 may be etched to form a columnar via 16, to expose the support pedestal 42. As shown in fig. 11b, the adhesion layer 17 is deposited in the pillar-shaped via 16, the adhesion layer 17 is electrically connected to the corresponding support pedestal 42, and the material of the adhesion layer 17 includes at least one of titanium, titanium nitride, tantalum, or tantalum nitride. As shown in fig. 11c, metal tungsten or metal copper is deposited on the adhesion layer 17 of the pillar via 16 and CMP-planarized to form the first interconnection pillar 7.

Specifically, the infrared detector may be disposed such that the side wall of the solid metal structure 71 and the surface adjacent to the CMOS measurement circuitry 1 are coated with at least one adhesion layer 17, and fig. 11a to 11c are exemplarily disposed such that the side wall of the solid metal structure 71 and the surface adjacent to the CMOS measurement circuitry 1 are coated with one adhesion layer 17. The adhesion layer 17 is used for enhancing the connection performance between the first interconnection column 7 and the support base 42, and comprises the mechanical connection performance of an enhancer and the structural stability, and also comprises the electrical connection performance of the enhancer, so that the contact resistance is reduced, the loss in the electrical signal transmission process is reduced, and the infrared detection performance of the infrared detector is improved, and the adhesion layer 17 is arranged to surround the side surface of the solid metal structure 71, so that the contact area between the adhesion layer 17 and the solid metal structure 71 can be increased, namely, the transmission channel of the electrical signal is widened, and the transmission resistance of the first interconnection column 7 is reduced, so that the electrical signal transmission loss is further reduced, and the infrared detection performance of the infrared detector is improved. For example, the adhesion layer 17 covering the solid metal structure 71 may be an electrode layer in the beam structure 31, or the adhesion layer 17 covering the solid metal structure 71 may be a separately fabricated film layer.

Fig. 12a-12d are schematic structural diagrams corresponding to another fabrication process of a first interconnection column according to an embodiment of the present invention. The first interconnection stud 7 is prepared using a via process, and the first sacrificial layer 6 may be etched to form a columnar via 16, as shown in fig. 12a, for example, the first sacrificial layer 6 and the first dielectric layer 5 may be etched to form a columnar via 16 to expose the support pedestal 42. As shown in fig. 12b, a thin second insulating layer 18 is deposited in the pillar via 16 by CVD, the material of the second insulating layer 18 includes at least one of sic, sin, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, silicon germanium, amorphous carbon, or alumina, and the second insulating layer 18 is etched to form a second via 19 to expose the support pedestal 42. As shown in fig. 12c, metal tungsten or metal copper is deposited in the second via hole 19 and CMP planarized to form the first interconnection pillar 7.

Alternatively, as shown in fig. 12b, the second insulating layer 18 is deposited in the pillar-shaped via hole 16 by using a CVD process and the second insulating layer 18 is etched to form the second via hole 19 so as to expose the supporting pedestal 42, or as shown in fig. 12d, the pillar-shaped via hole 16 is filled with the second insulating layer 18, and then the second insulating layer 18 is etched to form the second via hole 19 shown in fig. 12b, and the structure of the finally formed first interconnection pillar 7 is still as shown in fig. 12 c.

Specifically, the sidewalls of solid metal structure 71 are clad with at least one layer of second insulating layer 18, and solid metal structure 71 is disposed in contact with one layer of second insulating layer 18, fig. 12a-12d exemplarily provide that the sidewalls of solid metal structure 71 are clad with one layer of second insulating layer 18 and solid metal structure 71 is disposed in contact with this second insulating layer 18, and the material constituting solid metal structure 71 includes at least one of tungsten or copper. Specifically, at least one layer of the second insulating layer 18 of the solid metal structure 71 can play a role of electrical insulation, and when the solid metal structure 71 is protected by the second insulating layer 18 to avoid the solid metal structure 71 from being corroded by external materials, the second insulating layer 18 can serve as an auxiliary supporting structure of the first interconnection column 7, and the auxiliary supporting structure and the solid metal structure 71 jointly support a suspended micro-bridge structure located above the first interconnection column 7, so that the mechanical stability of the first interconnection column 7 is improved, and the structural stability of the infrared sensor is improved.

In addition, the material of the second insulating layer 18 forming the first interconnection pillars 7 includes at least one of silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, silicon germanium, amorphous carbon, or aluminum oxide, and none of the above materials is corroded by the gas-phase hydrogen fluoride, carbon tetrafluoride, or trifluoromethane, so that the second insulating layer 18 covering the solid metal structure 71 is not corroded when the sacrificial layer is corroded by the gas-phase hydrogen fluoride, carbon tetrafluoride, or trifluoromethane in the subsequent process steps. Illustratively, the second insulating layer 18 covering the solid metal structure 71 may be a supporting layer in the beam structure 31, or may be a dielectric layer separately fabricated, or the second insulating layer 18 covering the solid metal structure 71 may be a passivation layer on the uppermost layer in the beam structure 31.

FIGS. 13a-13d are schematic structural diagrams illustrating another alternative first pillar interconnect fabrication process according to embodiments of the present invention. The first interconnection stud 7 is prepared using a via process, and as shown in fig. 13a, the first sacrificial layer 6 is etched to form a stud via 16, for example, the first sacrificial layer 6 and the first dielectric layer 5 may be etched to form a stud via 16 to expose the support pedestal 42. As shown in fig. 13b, a CVD process is used to deposit a second insulating layer 18 in the pillar-shaped via 16, the material forming the second insulating layer 18 includes at least one of silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, silicon germanium, amorphous carbon, or aluminum oxide, and the second insulating layer 18 is etched to form a second via 19. As shown in fig. 13c, an adhesion layer 17 is deposited in the second via hole 19, and a material constituting the adhesion layer 17 includes at least one of titanium, titanium nitride, tantalum, or tantalum nitride. As shown in fig. 13d, metal tungsten or metal copper is deposited on the adhesion layer 17 of the second via hole 19 and CMP planarized to form the first interconnection pillar 7.

Specifically, the side wall of the solid metal structure 71 and the surface of the solid metal structure 71 close to the CMOS measurement circuit system 1 of the infrared detector are coated with at least one adhesion layer 17, fig. 13a to 13d exemplarily set the side wall of the solid metal structure 71 and the surface of the solid metal structure 71 close to the CMOS measurement circuit system 1 are coated with one adhesion layer 17, and the side wall of the adhesion layer 17 at the outermost periphery in the first interconnection column 7 far from the solid metal structure 71 is coated with the second insulation layer 18.

Specifically, the adhesion layer 17 is used for enhancing the connection performance between the first interconnection column 7 and the support base 42, and includes the mechanical connection performance of an enhancer, the structural stability is improved, the electrical connection performance of the enhancer is also included, the contact resistance is reduced, the loss in the electrical signal transmission process is reduced, the infrared detection performance of the infrared detector is improved, the adhesion layer 17 is arranged to surround the side face of the solid metal structure 71, the contact area between the adhesion layer 17 and the solid metal structure 71 can be increased, namely the transmission channel of the electrical signal is widened, the transmission resistance of the first interconnection column 7 is reduced, the electrical signal transmission loss is further reduced, and the infrared detection performance of the infrared detector is improved.

The side wall of the adhesion layer 17 on the outermost periphery in the first interconnection column 7, which is far away from the solid metal structure 71, is further coated with the second insulating layer 18, so that the adhesion layer 17 is utilized to enhance the connection performance between the first interconnection column 7 and the support base 42, and meanwhile, the second insulating layer 18 coating the side wall of the adhesion layer 17 plays a role in insulating protection, and the second insulating layer 18 can play a role in auxiliary support for the first interconnection column 7, so as to improve the structural stability and the infrared detection performance of the infrared detector.

Illustratively, the material that may be used to form the second insulating layer 18 may include at least one of silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, silicon germanium, amorphous carbon, or aluminum oxide, which are not corroded by the gas phase hydrogen fluoride, carbon tetrafluoride, or trifluoromethane, and thus the second insulating layer 18 that covers the adhesion layer 17 is not corroded when the sacrificial layer is corroded by the gas phase hydrogen fluoride, carbon tetrafluoride, or trifluoromethane in the subsequent process steps. For example, the adhesion layer 17 covering the solid metal structure 71 may be an electrode layer in the beam structure 31, the second insulation layer 18 covering the adhesion layer 17 may be a support layer in the beam structure 31, and the adhesion layer 17 covering the solid metal structure 71 and/or the second insulation layer 18 covering the adhesion layer 17 may also be a separately manufactured film layer, or the second insulation layer 18 covering the adhesion layer 17 may also be a passivation layer on the uppermost layer in the beam structure 31.

For example, the first adhesion layer 17 and/or the second insulation layer 18 described in the above embodiments may be formed by first forming an entire layer corresponding to the first adhesion layer 17 and/or the second insulation layer 18, and the effect after the CMP process may be that only the first adhesion layer 17 and/or the second insulation layer 18 is present in the through hole, or the CMP process may be performed until the first adhesion layer 17 and/or the second insulation layer 18 is reached.

In some embodiments, the CMOS infrared sensing structure 2 can be configured to include at least two first interconnection pillars 7, the first interconnection pillars 7 including at least one discrete interconnection pillar. FIGS. 14a-14b are schematic structural diagrams illustrating another alternative first interconnection column according to embodiments of the present invention. Corresponding to the fabrication process shown in fig. 12c, first interconnect pillar 7 may include a plurality of discrete interconnect pillars 20 as shown in fig. 14a, each discrete interconnect pillar 20 may include a solid metal structure 71 and a second insulating layer 18, and fig. 14a illustratively provides that first interconnect pillar 7 includes three discrete interconnect pillars 20. Corresponding to the fabrication process shown in fig. 12d, the first interconnect pillar 7 may include a plurality of discrete interconnect pillars 20 as shown in fig. 14b, and since the fabrication process shown in fig. 12d requires filling the second insulating layer 18 in the pillar via 16, then etching the second insulating layer 18 to form the second via 19, and finally forming the first interconnect pillar 7, in the structure shown in fig. 14b, different discrete interconnect pillars 20 may share the second insulating layer 18, and one solid metal structure 71 may be used as one discrete interconnect pillar 20. Thus, by providing first interconnect post 7 to include a plurality of discrete interconnect posts 20, the dimensions of each discrete interconnect post 20 are made smaller, making the fabrication process for first interconnect post 7 easier to implement.

It should be noted that, for the structures shown in fig. 10a to 10b, fig. 11a to 11c, and fig. 13a to 13d, the first interconnection column 7 may also be provided to include a plurality of discrete interconnection columns 20, which will not be described herein again.

In some embodiments, the first interconnection pillar 7 may include at least one layer of solid interconnection pillar, and the solid interconnection pillar has better mechanical stability, so that the support connection stability between the first interconnection pillar 7 and the beam structure 31 and the support base 42 is improved, and the structural stability of the infrared sensor pixel and the infrared detector including the infrared detector pixel is further improved. In addition, the resistance of the metal solid interconnection column is small, which is beneficial to reducing the signal loss in the process of carrying out electric signal transmission between the absorption plate 32 and the CMOS measurement circuit system 1, the infrared detection performance of the infrared detector is improved, and the size of the metal solid interconnection column is easier to accurately control, namely the solid interconnection column can realize the interconnection column with smaller size, which is beneficial to meeting the requirement of smaller chip size and realizing the miniaturization of the infrared detector.

And S5, depositing a second metal interconnection layer above the first interconnection column, and etching the second metal interconnection layer to form a first patterned electrode structure so as to form a beam structure.

Fig. 15a to 15c are schematic structural diagrams corresponding to a manufacturing process of a beam structure according to an embodiment of the present invention. As shown in fig. 15a, the third dielectric layer 21 is prepared by a CVD process, the third dielectric layer 21 is a supporting layer of the beam structure 31, and the material constituting the third dielectric layer 21 includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, aluminum oxide, or amorphous carbon. As shown in fig. 15b, a PVD process or a CVD process is used to prepare the second metal interconnection layer 8 on the third dielectric layer 21, and the second metal interconnection layer 8 is an electrode layer in the beam structure 31. As shown in fig. 15c, a CVD process is used to prepare the fourth dielectric layer 22 on the second metal interconnection layer 8, the fourth dielectric layer 22 is a passivation layer of the beam structure 31, and the material constituting the fourth dielectric layer 22 includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, aluminum oxide, or amorphous carbon. In addition, the fabrication process shown in fig. 15a-15c involves etching the fourth dielectric layer 22 to form a patterned dielectric layer, etching the second metal interconnect layer 8 to form a first patterned electrode structure and etching the third dielectric layer 21 to form a patterned dielectric layer to form the beam structure 31.

Illustratively, the third dielectric layer 21 may be deposited and the third dielectric layer 21 etched to expose the solid metal structures 71 in the first interconnect pillars 7, as shown in fig. 15a, the second metal interconnect layer 8 may be deposited and the second metal interconnect layer 8 may be etched to form the first patterned electrode structure, as shown in fig. 15b, and the fourth dielectric layer 22 may be deposited and the third dielectric layer 21 and the fourth dielectric layer 22 may be simultaneously etched to form the patterned passivation layer and the patterned support layer, as shown in fig. 15 c.

Specifically, as shown in fig. 15a to 15c, the beam structure 31 may be configured to include a third dielectric layer 21, a second metal interconnection layer 8, and a fourth dielectric layer 22, where the third dielectric layer 21 serves as a support layer of the beam structure 31, the support layer is configured to support a film layer located above the support layer after releasing the first sacrificial layer 6 below the support layer, a first patterned electrode structure in the second metal interconnection layer 8 is configured to transmit the converted ir detection electrical signal to the CMOS measurement circuit system 1 through the first interconnection pillar 7, and the fourth dielectric layer 22 serves as a passivation layer of the beam structure 31 to protect the first patterned electrode structure wrapped by the passivation layer from oxidation or corrosion.

In some embodiments, the beam structure 31 is formed, the second metal interconnection layer 8 is prepared by a PVD process or a CVD process, and the second metal interconnection layer 8 is etched to form the first patterned electrode structure, so as to form the beam structure 31. Specifically, it may be configured that the beam structure 31 only includes the second metal interconnection layer 8, that is, the beam structure 31 only includes an electrode layer, the first patterned electrode structure is located on the electrode layer, the first patterned electrode structure in the second metal interconnection layer 8 is configured to transmit the converted infrared detection electrical signal to the CMOS measurement circuit system 1 through the first interconnection column 7, taking the example that the infrared detector shown in fig. 2 includes two first interconnection columns 7, the two first interconnection columns 7 respectively transmit positive and negative signals of the infrared detection electrical signal, and the readout circuit in the CMOS measurement circuit system 1 implements non-contact infrared temperature detection through analysis of the acquired infrared detection electrical signal.

In some embodiments, the beam structure 31 is formed, the third dielectric layer 21 may be further prepared by using a CVD process, the third dielectric layer 21 is a support layer of the beam structure 31, a material constituting the third dielectric layer 21 includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, aluminum oxide, or amorphous carbon, the PVD process or the CVD process is then used to prepare the second metal interconnection layer 8 on the third dielectric layer 21, and the second metal interconnection layer 8 is etched to form the first patterned electrode structure, which further involves etching the third dielectric layer 21 to form the patterned dielectric layer to form the beam structure 31.

Specifically, the beam structure 31 may include a third dielectric layer 21 and a second metal interconnection layer 8, the second metal interconnection layer 8 is located above the third dielectric layer 21, the third dielectric layer 21 serves as a support layer of the beam structure 31, the support layer is configured to support a film layer located above the support layer after releasing the first sacrificial layer 6 below the support layer, and the first patterned electrode structure in the second metal interconnection layer 8 is configured to transmit the converted infrared detection electrical signal to the CMOS measurement circuit system 1 through the first interconnection column 7. Illustratively, the third dielectric layer 21 may be deposited and then the third dielectric layer 21 is etched to expose the solid metal structures 71 in the first interconnect pillar 7, then the second metal interconnect layer 8 is deposited, the second metal interconnect layer 8 is etched to form the first patterned electrode structure, and simultaneously the third dielectric layer 21 is etched to form the patterned support layer.

In some embodiments, the beam structure 31 is formed, and the second metal interconnection layer 8 may be further prepared by a PVD process or a CVD process, and then the fourth dielectric layer 22 is prepared on the second metal interconnection layer 8 by a CVD process, in which the fourth dielectric layer 22 is etched to form a patterned dielectric layer, the second metal interconnection layer 8 is etched to form a first patterned electrode structure to form the beam structure 31, the fourth dielectric layer 22 is a passivation layer of the beam structure 31, and a material constituting the fourth dielectric layer 22 includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, aluminum oxide, or amorphous carbon.

Specifically, the beam structure 31 may include the second metal interconnection layer 8 and the fourth dielectric layer 22, the fourth dielectric layer 22 is located above the second metal interconnection layer 8, the fourth dielectric layer 22 serves as a passivation layer of the beam structure 31, the passivation layer is used to protect the first patterned electrode structure wrapped by the passivation layer from being oxidized or corroded, and the first patterned electrode structure in the second metal interconnection layer 8 is used to transmit the converted infrared detection electric signal to the CMOS measurement circuit system 1 through the first interconnection column 7. Illustratively, the second metal interconnection layer 8 may be deposited and the second metal interconnection layer 8 may be etched to form the first patterned electrode structure, and the fourth dielectric layer 22 may be deposited on the second metal interconnection layer 8 and the fourth dielectric layer 22 may be etched to form the patterned passivation layer.

It should be noted that the preparation processes of the beam structure 31 described in the above embodiments can be understood with reference to fig. 15a to 15c, which are not repeated herein, and it is sufficient to ensure that the first patterned electrode structure in the finally formed beam structure 31 is electrically connected to the corresponding solid metal structure 71 in the first interconnection pillar 7.

Illustratively, the material that may be provided to constitute the second metal interconnect layer 8 includes at least one of titanium, titanium nitride, tantalum nitride, titanium tungsten alloy, nickel chromium alloy, nickel platinum alloy, nickel silicon alloy, nickel, chromium, platinum, tungsten, aluminum, or copper.

In some embodiments, after step 4, a PVD process or a CVD process may be further used to deposit a first reinforcing layer at a corresponding position of the first interconnection pillar 7 and/or the second interconnection pillar, and the first reinforcing layer may be deposited at a corresponding position of the first interconnection pillar 7, or the first reinforcing layer may be deposited at a corresponding position of the second interconnection pillar, or the first reinforcing layer may be deposited at a corresponding position of the first interconnection pillar 7 and a corresponding position of the second interconnection pillar, and the first reinforcing layer may be etched to form a reinforcing structure corresponding to the beam structure 31, and a material constituting the first reinforcing layer includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride, silicon carbonitride, silicon oxide, silicon, germanium, silicon, aluminum, copper, tungsten, gold, platinum, nickel, chromium, titanium-tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, or nickel-silicon alloy.

Fig. 15b and 15c exemplarily provide that the first reinforcing layer 29 is deposited at a corresponding position of the first interconnection pillar 7 and a corresponding position of the second interconnection pillar, and the first reinforcing layer 29 is etched to form a reinforcing structure corresponding to the beam structure 31, the corresponding position of the first interconnection pillar 7 may be directly above the first interconnection pillar 7, and the corresponding position of the second interconnection pillar may be directly below the second interconnection pillar, wherein the reinforcing structure 291 is provided at a corresponding position of the first interconnection pillar 7, and the reinforcing structure 292 is provided at a corresponding position of the second interconnection pillar.

Illustratively, the third dielectric layer 21 may be deposited and the third dielectric layer 21 etched to form a patterned dielectric layer, as shown in fig. 15a, the first reinforcement layer 29 may be deposited and the first reinforcement layer 29 may be etched on the third dielectric layer 21 to form patterned

reinforcement structures

291 and 292 corresponding to the first and

second interconnection pillars

7 and 7, as shown in fig. 15b, the second metal interconnection layer 8 may be deposited and the second metal interconnection layer 8 may be etched to form a first patterned electrode structure, and the fourth dielectric layer 22 may be deposited and the third dielectric layer 22 and the third dielectric layer 21 may be simultaneously etched on the second metal interconnection layer 8 to form a patterned support layer and a patterned passivation layer, as shown in fig. 15 c.

Specifically, the reinforcing structure 291 arranged corresponding to the first interconnecting column 7 can enhance the connection stability between the first interconnecting column 7 and the beam structure 31, the reinforcing structure 291 arranged corresponding to the first interconnecting column 7 includes an aggravated block structure, and the reinforcing structure 291 arranged corresponding to the first interconnecting column 7 can effectively enhance the mechanical stability between the first interconnecting column 7 and the beam structure 31, so as to improve the structural stability of the infrared detector pixel and the infrared detector including the infrared detector pixel. The reinforcing structure 292 disposed corresponding to the second interconnection post may pad up the first patterned electrode structure disposed corresponding to the location of the second interconnection post to optimize the electrical contact performance of the first patterned electrode structure with the second interconnection post in the beam structure 31.

For example, the reinforcing structure 291 disposed corresponding to the first interconnection column 7 may also be located between the second metal interconnection layer 8 and the fourth dielectric layer 22, or may also be located on a side of the fourth dielectric layer 22 away from the second metal interconnection layer 8 and disposed in contact with the fourth dielectric layer 22, which may both enhance the connection stability between the first interconnection column 7 and the beam structure 31, and the specific preparation process of the reinforcing structure 291 corresponding to the foregoing situation is not described herein again.

S6, depositing a third metal interconnection layer, and etching the third metal interconnection layer to form a second interconnection column.

FIGS. 16a-16c are schematic structural diagrams corresponding to a second interconnect pillar fabricating process according to an embodiment of the invention. As shown in fig. 16a, the fourth dielectric layer 22 is etched to expose the first patterned electrode structure in the beam structure 31. Then, as shown in fig. 16b, a third metal interconnection layer 53 may be deposited on the fourth dielectric layer 22, and the material constituting the third metal interconnection layer 53 includes metallic aluminum. The third metal interconnect layer 53 is then etched to form second interconnect pillars 10, the second interconnect pillars 10 being electrically connected to the first patterned electrode structures in the corresponding beam structures 31, as shown in fig. 16 c.

Specifically, the second interconnection column 10 of the infrared detector shown in fig. 16a to 16c is formed by the solid metal structure 101, the sidewall of the solid metal structure 101 is in contact with the second sacrificial layer 9, and the material of the solid metal structure 101 forming the second interconnection column 10 includes aluminum, so that the preparation process of the second interconnection column 10 is simple and easy to implement, and the preparation difficulty of the whole infrared detector is favorably reduced.

And S7, depositing to form a second sacrificial layer.

Fig. 17 is a schematic structural diagram corresponding to a process of preparing a second sacrificial layer according to an embodiment of the present invention. The second sacrificial layer 9 is deposited, as shown in fig. 17, the second sacrificial layer 9 is deposited, and the surface of the second sacrificial layer 9 is processed by a CMP process, the CMP process is stopped until the upper surface of the third metal interconnection layer 53 is reached, that is, after the CMP process processes the surface of the second sacrificial layer 9, the upper surface of the third metal interconnection layer 53 is flush with the upper surface of the second sacrificial layer 9, so as to optimize the planarization degree of the film layer above the second sacrificial layer 9.

In some embodiments, the second sacrificial layer 9 may be composed of silicon oxide prepared using a thermal oxidation process or a CVD process. Specifically, the infrared detector takes silicon oxide as a sacrificial layer, the silicon oxide is completely compatible with a CMOS (complementary metal oxide semiconductor) process, the preparation process is simple and easy to control, the CMOS process does not have the problem that the vacuum degree of a detector chip is influenced due to incomplete release of polyimide of the sacrificial layer, the subsequent film growth temperature is not limited by the material of the sacrificial layer, the multilayer process design of the sacrificial layer can be realized, the process is not limited, the sacrificial layer can be easily utilized to realize planarization, and the process difficulty and possible risks are reduced.

Fig. 18a to 18c are schematic structural diagrams corresponding to another preparation process of a second sacrificial layer according to an embodiment of the present invention. As shown in fig. 18a, immediately after step 6, after the third metal interconnection layer 53 is etched to form the second interconnection pillar 10, a CVD process is used to deposit a third insulation layer 54 on the second interconnection pillar 10, wherein the material constituting the third insulation layer 54 includes at least one of silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, silicon germanium, amorphous carbon or aluminum oxide, and illustratively, the entire third insulation layer 54 may be formed first, and then the third insulation layer 54 is etched to make the third insulation layer 54 cover only the solid metal structure 101. Then, as shown in fig. 18b, a second sacrificial layer 9 is deposited, i.e. the second sacrificial layer 9 is deposited on the third insulating layer 54, and the surface of the second sacrificial layer 9 is treated with a CMP process, which may be as shown in fig. 18b down to the third metal interconnect layer 53, or as shown in fig. 18c down to the upper surface of the third insulating layer 54.

Specifically, the sidewalls of the solid metal structure 101 are clad with at least one layer of the third insulating layer 54, and the solid metal structure 101 is disposed in contact with one layer of the third insulating layer 54, fig. 18a-18c exemplarily providing that the sidewalls of the solid metal structure 101 are clad with one layer of the third insulating layer 54 and the solid metal structure 101 is disposed in contact with the third insulating layer 54. Specifically, at least one third insulating layer 54 of the solid metal structure 101 may play an electrical insulating role, and when the solid metal structure 101 is protected by the third insulating layer 54 to avoid the solid metal structure 101 from being corroded by external materials, the third insulating layer 54 may serve as an auxiliary supporting structure of the second interconnection column 10, and the structure of the third insulating layer and the solid metal structure 101 are located above the second interconnection column 10 together, which is beneficial to improving the mechanical stability of the second interconnection column 10, so as to improve the structural stability of the infrared sensor.

In addition, the third insulating layer 54 constituting the second interconnection pillar 10 is made of at least one material selected from the group consisting of silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, silicon germanium, amorphous carbon, and aluminum oxide, which are not corroded by gas-phase hydrogen fluoride, carbon tetrafluoride, and trifluoromethane, so that the third insulating layer 54 covering the solid metal structure 101 is not corroded when the sacrificial layer is corroded by gas-phase hydrogen fluoride, carbon tetrafluoride, and trifluoromethane in the subsequent process steps.

In some embodiments, the CMOS infrared sensing structure 2 can be configured to include at least two second interconnect pillars 10, the second interconnect pillars 10 including at least one discrete interconnect pillar. In analogy to fig. 14a and 14b, the second pillar 10 may comprise a plurality of discrete pillars, such that the size of each discrete pillar is relatively small, such that the fabrication process of the second pillar 10 is easier to implement.

In some embodiments, the second interconnection pillar 10 may include at least one layer of solid interconnection pillar, which has better mechanical stability, and improves the stability of the support connection between the second interconnection pillar 10 and the beam structure 31 and the absorption plate, thereby improving the structural stability of the infrared sensor pixel and the infrared detector including the infrared detector pixel. In addition, the resistance of the metal solid interconnection column is small, signal loss in the process of electrical signal transmission between the absorption plate and the CMOS measurement circuit system 1 is reduced, the infrared detection performance of the infrared detector is improved, the size of the metal solid interconnection column is easier to control accurately, namely the solid interconnection column can realize the interconnection column with smaller size, the requirement on the size of a smaller chip is met, and the miniaturization of the infrared detector is realized.

S8, depositing a fourth metal interconnection layer and a second dielectric layer, and etching the fourth metal interconnection layer to form a second patterned electrode structure so as to form an absorption plate; the second dielectric layer is a heat sensitive dielectric layer.

Fig. 19a to 19b are schematic structural diagrams corresponding to a manufacturing process of an absorption plate according to an embodiment of the present invention. As shown in fig. 19a, the fourth metal interconnection layer 11 may be prepared by a PVD process or a CVD process, for example, the fourth metal interconnection layer 11 may be prepared on the second sacrificial layer 9 by a PVD process or a CVD process. As shown in fig. 19b, a PVD process or a CVD process is then used to prepare a second dielectric layer 12 on the fourth metal interconnect layer 11, the second dielectric layer 12 being a heat sensitive dielectric layer, and the second dielectric layer 12 is lithographically etched to form a patterned dielectric layer, which further involves etching the fourth metal interconnect layer 11 to form a second patterned electrode structure to form the absorber plate 32.

Specifically, the heat sensitive dielectric layer is used for converting an infrared temperature detection signal into an infrared detection electrical signal, and the second patterned electrode structure is used for transmitting the infrared detection electrical signal converted from the heat sensitive dielectric layer in the absorption plate 32 to the first patterned electrode structure in the beam structure 31 through the second interconnection column 10, and further to the CMOS measurement circuit system 1 through the first interconnection column 7. Taking the infrared transmission detector including two second interconnection columns 10 as an example, the two second interconnection columns 10 respectively transmit positive and negative signals of the infrared detection electrical signal, and the readout circuit in the CMOS measurement circuit system 1 implements non-contact infrared temperature detection by analyzing the acquired infrared detection electrical signal.

Illustratively, a fourth metal interconnection layer 11 may be deposited and the fourth metal interconnection layer 11 may be etched to form a second patterned electrode structure, which is electrically connected to the solid metal structure 101 in the second interconnection stud 10, as shown in fig. 19a, and then a second dielectric layer 12 may be formed on the fourth metal interconnection layer 11 and the second dielectric layer 12 may be etched to form a patterned dielectric layer, i.e., a patterned heat sensitive dielectric layer, as shown in fig. 19 b.

Fig. 20a-20b are schematic structural diagrams corresponding to another manufacturing process of an absorption plate according to an embodiment of the present invention. As shown in fig. 20a, the second dielectric layer 12 may also be prepared by a PVD process or a CVD process, for example, the second dielectric layer 12 is prepared on the second sacrificial layer 9 by a PVD process or a CVD process. As shown in fig. 20b, a PVD-process or a CVD-process is used to prepare the fourth metal interconnect layer 11 on the second dielectric layer 12, which involves etching the fourth metal interconnect layer 11 to form a second patterned electrode structure and lithographically etching the second dielectric layer 12 to form a patterned dielectric layer to form the absorber plate 32.

Illustratively, the second dielectric layer 12 may be deposited first, and the second dielectric layer 12 is etched to form a patterned heat sensitive dielectric layer and expose the solid metal structures 101 in the second interconnect pillars 10, as shown in fig. 20a, and then the fourth metal interconnect layer 11 is deposited on the second dielectric layer 12, and the fourth metal interconnect layer 11 is etched to form second patterned electrode structures, as shown in fig. 20b, which are electrically connected to the solid metal structures 101 in the second interconnect pillars 10.

Illustratively, the material constituting the fourth metal interconnection layer 11 includes at least one of titanium, titanium nitride, tantalum nitride, titanium-tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, nickel-silicon alloy, nickel, chromium, platinum, tungsten, aluminum, or copper, and the material constituting the second dielectric layer 12 includes at least one of materials having a temperature coefficient of resistance greater than a set value, which are prepared from titanium oxide, vanadium titanium oxide, amorphous silicon, amorphous germanium, amorphous silicon germanium oxide, silicon, germanium, silicon germanium oxide, amorphous carbon, graphene, yttrium barium copper oxide, copper, or platinum.

In some embodiments, before the fourth metal interconnection layer 11 and the second dielectric layer 12 are prepared, step 8 may further include preparing a fifth dielectric layer by using a CVD process and etching the fifth dielectric layer to form a patterned dielectric layer; the fifth dielectric layer is a supporting layer of the absorption plate, and the material forming the fifth dielectric layer comprises at least one of silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium-silicon, germanium-silicon, amorphous carbon or aluminum oxide; and/or after the fourth metal interconnection layer 11 and the second dielectric layer 12 are prepared, the step 8 may further include preparing a sixth dielectric layer by using a CVD process and etching the sixth dielectric layer to form a patterned dielectric layer; the sixth dielectric layer is a passivation layer of the absorber plate, and the material forming the sixth dielectric layer includes at least one of silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, silicon germanium, amorphous carbon, or aluminum oxide.

Fig. 21a to 21d are schematic structural diagrams corresponding to a manufacturing process of another absorption plate according to an embodiment of the present invention. Step 8 may further include, for example, before the fourth metal interconnection layer 11 and the second dielectric layer 12 are prepared, preparing a fifth dielectric layer 27 by using a CVD process and etching the fifth dielectric layer 27 to form a patterned dielectric layer, and preparing a sixth dielectric layer 28 by using a CVD process and etching the sixth dielectric layer 28 to form a patterned dielectric layer. As shown in fig. 21a, after forming the second interconnection stud 10, a fifth dielectric layer 27 may be deposited on the second sacrificial layer 9 and the fifth dielectric layer 27 may be etched to form a patterned dielectric layer, the etched fifth dielectric layer 27 exposing the solid metal structure 101 in the second interconnection stud 10, the fifth dielectric layer 27 serving as a support layer for the absorber plate 32. As shown in fig. 21b, a fourth metal interconnect layer 11 is deposited on the fifth dielectric layer 27 and the fourth metal interconnect layer 11 is etched to form a second patterned electrode structure. As shown in fig. 21c, a second dielectric layer 12 is deposited on the fourth metal interconnect layer 11 and the second dielectric layer 12 is etched to form a patterned heat sensitive dielectric layer. As shown in fig. 21d, a sixth dielectric layer 28 is deposited on the heat sensitive dielectric layer and the sixth dielectric layer 28 is etched to form a patterned dielectric layer, the sixth dielectric layer 28 acting as a passivation layer for the absorber plate 32.

In addition, after the fourth metal interconnection layer 11 and the second dielectric layer 12 are prepared, the fifth dielectric layer 27 and/or the sixth dielectric layer 28 may be etched at the same time, or the fifth dielectric layer 27 and/or the sixth dielectric layer 28 may be etched together with the second dielectric layer 12 to form the absorber plate 32, or the fifth dielectric layer 27 and/or the sixth dielectric layer 28 may be etched together with the second dielectric layer 12 and the fourth metal interconnection layer 11 to form the absorber plate 32.

In some embodiments, after step 7, a PVD process or a CVD process may be further used to deposit a second reinforcing layer on the corresponding position of the second interconnection pillar 10, and the second reinforcing layer is etched to form a reinforcing structure corresponding to the absorber plate 32, wherein the material constituting the second reinforcing layer includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride, silicon carbonitride, silicon oxide, silicon, germanium, silicon germanium, aluminum, copper, tungsten, gold, platinum, nickel, chromium, titanium-tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, or nickel-silicon alloy.

Fig. 21a-21d illustratively provide that the corresponding location of second interconnect post 10 is directly above second interconnect post 10. Illustratively, the fifth dielectric layer 27 may be deposited and the fifth dielectric layer 27 etched to form a patterned support layer, as shown in fig. 21a, then the second reinforcement layer 30 may be deposited and the second reinforcement layer 30 may be etched on the fifth dielectric layer 27 to form a patterned reinforcement structure corresponding to the second interconnect pillar 10, as shown in fig. 21b, then the fourth metal interconnect layer 11 may be deposited and the fourth metal interconnect layer 11 may be etched to form a second patterned electrode structure, then the second dielectric layer 12 may be deposited and the second dielectric layer 12 may be etched on the fourth metal interconnect layer 11 to form a patterned heat sensitive dielectric layer, as shown in fig. 21c, and then the sixth dielectric layer 28 may be deposited and the sixth dielectric layer 28 and the fifth dielectric layer 27 may be simultaneously etched on the second dielectric layer 12 to form a patterned support layer and a patterned passivation layer, as shown in fig. 21 d.

Specifically, the reinforced structure 301 that sets up to using second interconnection column 10 can strengthen the connection steadiness between second interconnection column 10 and the absorption plate 32, and including aggravating massive structure to the reinforced structure 301 that sets up to using second interconnection column 10, the reinforced structure 301 that sets up to corresponding second interconnection column 10 can effectively strengthen the mechanical stability between second interconnection column 10 and the absorption plate 32 to promote the infrared detector pixel and the infrared detector's that includes the infrared detector pixel structural stability.

Exemplarily, the reinforcing structure 301 disposed for the second interconnection column 10 may also be located between the fourth metal interconnection layer 11 and the sixth dielectric layer 28, or may also be located on a side of the sixth dielectric layer 28 away from the fourth metal interconnection layer 11 and disposed in contact with the sixth dielectric layer 28, which may both enhance the connection stability between the second interconnection column 10 and the absorbing plate 32, and the detailed process of the reinforcing structure 301 corresponding to the foregoing case is not described herein again. In addition, FIGS. 18a-18c and 19a-19b are equally applicable to providing a reinforcing structure 301 to enhance the mechanical stability between the second column 10 and the absorber plate 32, and will not be described here.

Fig. 22 is a structural schematic diagram corresponding to a manufacturing process of another absorption plate according to an embodiment of the present invention. As shown in fig. 22, the absorber plate 32 may also be disposed to sequentially include the fifth dielectric layer 27, the fourth metal interconnection layer 11, and the sixth dielectric layer 28, and at this time, the material forming the fifth dielectric layer 27 and/or the sixth dielectric layer 28 may be disposed to include at least one of materials with a temperature coefficient of resistance greater than a set value, which are made of amorphous silicon, amorphous germanium, amorphous silicon-germanium, or amorphous carbon, that is, the fifth dielectric layer 27 and/or the sixth dielectric layer 28 may be used as a heat sensitive dielectric layer of the absorber plate 32.

In some embodiments, the first sacrificial layer 6 may be formed of silicon oxide prepared by a thermal oxidation process or a CVD process, and the second sacrificial layer 9 may be formed of silicon oxide prepared by a thermal oxidation process or a CVD process. Fig. 23 is a schematic cross-sectional structure diagram of an infrared detector pixel provided in an embodiment of the present invention. With reference to fig. 21a to 21d and fig. 23, after step 8, the manufacturing method further includes etching the first sacrificial layer 6 and the second sacrificial layer 9 by using a release process, so that the beam structure 31 and the absorption plate 32 are suspended in the first dielectric layer 5 to form the suspended CMOS infrared sensing structure 2.

Specifically, the first sacrificial layer 6 and the second sacrificial layer 9 are used for enabling the CMOS infrared sensing structure 2 to form a hollow structure, the material of the first sacrificial layer 6 and the second sacrificial layer 9 is silicon oxide, and the first sacrificial layer 6 and the second sacrificial layer 9 are etched by a post-CMOS process. For example, the post-CMOS process may etch the first sacrificial layer 6 and the second sacrificial layer 9 using at least one of gases having etching characteristics to silicon oxide, such as gas phase hydrogen fluoride, carbon tetrafluoride, and trifluoromethane. The infrared detector takes silicon oxide as the first sacrificial layer 6 and the second sacrificial layer 9, the silicon oxide is completely compatible with a CMOS process, the preparation process is simple and easy to control, the CMOS process does not have the problem that the vacuum degree of a detector chip is influenced due to incomplete release of polyimide of the sacrificial layer, the subsequent film growth temperature is not limited by the sacrificial layer material, the multilayer process design of the sacrificial layer can be realized, the process is not limited by the process, the sacrificial layer can be easily utilized to realize planarization, the process difficulty and the possible risks are reduced, namely the material for forming the sacrificial layer is silicon oxide, the CMOS process is compatible, and a post-CMOS process can be adopted, namely the post-CMOS process corrodes the sacrificial layer to release the sacrificial layer in the final infrared detection chip product.

The embodiment of the invention also provides an infrared detector, which can be prepared by adopting the preparation method of the CMOS infrared detector with the solid column, so that the infrared detector has the beneficial effects of the embodiment and is not repeated herein.

Referring to fig. 2 and 23, the infrared detector comprises a CMOS measurement circuitry 1 and a CMOS infrared sensing structure 2, the CMOS measurement circuitry 1 comprises at least one hermetic release barrier layer thereon, and fig. 23 exemplarily sets the CMOS measurement circuitry 1 to comprise a hermetic release barrier layer, i.e., a first dielectric layer 5, thereon.

The CMOS manufacturing process of the CMOS infrared sensing structure 2 comprises a metal interconnection process, a through hole process, an IMD (in-mold decoration) process and an RDL (remote description language) process, wherein the CMOS infrared sensing structure 2 comprises at least three metal interconnection layers, at least four dielectric layers and a plurality of interconnection through holes, each metal interconnection layer at least comprises a reflection layer and two electrode layers, the reflection layer is a first metal interconnection layer 4, and the two electrode layers are a second metal interconnection layer 8 and a fourth metal interconnection layer 11. The dielectric layer at least comprises a closed release insulating layer, two sacrificial layers and a heat sensitive dielectric layer, wherein the closed release insulating layer is a first dielectric layer 5, the two sacrificial layers are a first sacrificial layer and a second sacrificial layer, the two sacrificial layers are released in a final infrared detector structure, and the heat sensitive dielectric layer is a second dielectric layer 12. The thermal sensitive medium layer is used for converting temperature change corresponding to infrared radiation absorbed by the thermal sensitive medium layer into resistance change, and further converting an infrared target signal into a signal capable of realizing electric reading through the CMOS measuring circuit system 1, the thermal sensitive medium layer comprises a thermal sensitive material with a resistance temperature coefficient larger than a set value, the resistance temperature coefficient can be larger than or equal to 0.015/K, and the thermal sensitive material with the resistance temperature coefficient larger than the set value forms the thermal sensitive medium layer, so that the detection sensitivity of the infrared detector is improved.

The CMOS infrared sensing structure 2 includes a resonant cavity formed by a reflective layer and a heat sensitive medium layer and a suspended microbridge structure for controlling heat transfer, that is, the CMOS infrared sensing structure 2 includes a resonant cavity formed by a first metal interconnection layer 4 and a second medium layer 12 and a suspended microbridge structure 40 for controlling heat transfer, the suspended microbridge structure 40 includes at least one beam structure 31 and at least one absorption plate 32, fig. 2 and 23 exemplarily set the suspended microbridge structure 40 to include one beam structure 31 and one absorption plate 32, the beam structure 31 is located at a side of the absorption plate 32 adjacent to or far away from the CMOS measurement circuit system 1, and fig. 2 and 23 exemplarily set the beam structure 31 at a side of the absorption plate 32 adjacent to the CMOS measurement circuit system 1.

A first interconnection column 7 is arranged between the reflective layer, i.e. the first metal interconnection layer 4, and the beam structure 31, and the first interconnection column 7 is directly electrically connected to the reflective layer, i.e. the support base 42 and the corresponding beam structure 31 in the first metal interconnection layer 4, the beam structure 31 is electrically connected to the CMOS measurement circuitry 1 through the first interconnection column 7 and the support base 42, and the first interconnection column 7 is used for supporting the corresponding beam structure 31 after the first sacrificial layer is released. The second interconnection column 10 is arranged between the absorption plate 32 and the beam structure 31, the second interconnection column 10 is directly and electrically connected with the corresponding absorption plate 32 and the corresponding beam structure 31, the absorption plate 32 is used for converting infrared signals into electric signals and is electrically connected with the corresponding first interconnection column 7 through the second interconnection column 10 and the corresponding beam structure 31, namely the electric signals converted by the absorption plate 32 via the infrared signals are transmitted to the CMOS measurement circuit system 1 through the second interconnection column 10, the beam structure 31, the first interconnection column 7 and the support base 42 in sequence, the CMOS measurement circuit system 1 processes the received electric signals to reflect temperature information, non-contact infrared temperature detection of the infrared detector is realized, and the second interconnection column 10 is used for supporting the corresponding beam structure 31 or the absorption plate 32 after the second sacrificial layer is released.

It should be noted that, the first interconnection column 7 of the above embodiment directly electrically connects the support base 42 and the beam structure 31 in the reflective layer, which means that the first interconnection column 7 only has two electrical connection ends, one electrical connection end of the first interconnection column 7 is directly electrically connected to the support base 42, and the other electrical connection end of the first interconnection column 7 is directly electrically connected to the beam structure 31 closest to the electrical connection end of the first interconnection column 7. Second interconnection column 10 of the above-described embodiment directly electrically connects absorption plate 32 and beam structure 31, meaning that second interconnection column 10 has only two electrical connection terminals, one electrical connection terminal of second interconnection column 10 directly electrically connects absorption plate 32 closest to the electrical connection terminal of second interconnection column 10, and the other electrical connection terminal of second interconnection column 10 directly electrically connects beam structure 31 closest to the electrical connection terminal of second interconnection column 10.

The CMOS infrared sensing structure 2 outputs a positive electrical signal and a ground electrical signal through different electrode structures, and the positive electrical signal and the ground electrical signal are transmitted to the corresponding supporting bases 42 through different sets of interconnection columns, which include a first interconnection column 7 and a second interconnection column 10. Illustratively, the CMOS infrared sensing structure 2 may be arranged to include two sets of interconnect pillars, one set of which may be arranged to transmit a positive electrical signal and the other set of which may be arranged to transmit a ground electrical signal, in a direction parallel to the CMOS measurement circuitry 1. The direction parallel to the CMOS measuring circuit system 1 can be set, the CMOS infrared sensing structure 2 comprises four groups of interconnection columns, every two of the four groups of interconnection columns can be respectively used as a group for transmitting positive electric signals and grounding electric signals, the infrared detector comprises a plurality of infrared detector pixels arranged in an array, the four groups of interconnection columns can also select two groups of interconnection columns to respectively transmit positive electric signals and grounding electric signals, and the other two groups of interconnection columns supply the adjacent infrared detector pixels for transmitting electric signals.

Fig. 24 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in an embodiment of the present invention, and the infrared detector pixel having the structure shown in fig. 24 is also applicable to the method for manufacturing an infrared detector described in the above embodiment. As shown in fig. 24, the suspended micro-bridge structure 40 may also be configured to include a multi-layer beam structure 31, fig. 24 exemplarily configures the suspended micro-bridge structure 40 to include a two-layer beam structure 31, for example, a first-layer beam structure 311 and a second-layer beam structure 312, the first-layer beam structure 311 is located on a side of the second-layer beam structure 312 away from the CMOS measurement circuit system 1, and an interconnection column 313 is also disposed between the first-layer beam structure 311 and the second-layer beam structure 312, and the interconnection column 313 is used for supporting the first-layer beam structure 311 after the sacrificial layer between the first-layer beam structure 311 and the second-layer beam structure 312 is released. The electrode layer in the absorption plate 32 is electrically connected with the electrode layer in the first layer beam structure 311 through the second interconnection column 10, the electrode layer in the first layer beam structure 311 is electrically connected with the electrode layer in the second layer beam structure 312 through the interconnection column 313 between the first layer beam structure 311 and the second layer beam structure 312, the electrode layer in the second layer beam structure 312 is electrically connected with the first interconnection column 7, and the electric signal converted by the absorption plate 32 through the infrared signal is transmitted to the CMOS measurement circuit system 1 through the second interconnection column 10, the first layer beam structure 311, the interconnection column 313 between the first layer beam structure 311 and the second layer beam structure 312, the first interconnection column 7 and the support base 42 in sequence. Wherein the first interconnection column 7 directly electrically connects the support base 42 and the beam structure 31 closest to the CMOS measurement circuitry 1, and the second interconnection column 10 directly electrically connects the absorber plate 32 closest to the CMOS measurement circuitry 1 and the beam structure 31 closest to the absorber plate 32.

Fig. 25 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in an embodiment of the present invention, and the infrared detector pixel having the structure shown in fig. 25 is also applicable to the method for manufacturing an infrared detector described in the above embodiment. As shown in fig. 25, it is also possible to arrange suspended micro-bridge structure 40 to include multiple layers of absorbing plates 32, fig. 25 exemplarily arranging suspended micro-bridge structure 40 to include two layers of absorbing plates 32, for example, including a first layer of absorbing plate 321 and a second layer of absorbing plate 322, first layer of absorbing plate 321 being located on the side of second layer of absorbing plate 322 far from CMOS measurement circuit system 1, and interconnecting column 323 also being arranged between first layer of absorbing plate 321 and second layer of absorbing plate 322, and being used for supporting first layer of absorbing plate 321 after the sacrificial layer between first layer of absorbing plate 321 and second layer of absorbing plate 322 is released. The first absorption plate 321 and the second absorption plate 322 both include electrode layers, the electrode layers in the two may be electrically connected through the interconnection column 323 between the first absorption plate 321 and the second absorption plate 322, and the electrode layers in the two may not be electrically connected, the electrode layer in the second absorption plate 322 is electrically connected through the second interconnection column 10 to the electrode layer in the beam structure 31, the electrode layer in the beam structure 31 is electrically connected to the support base 42 through the first interconnection column 7, and the electric signal converted by the absorption plate 32 via the infrared signal is transmitted to the CMOS measurement circuit system 1 sequentially through the second interconnection column 10, the beam structure 31, the first interconnection column 7 and the support base 42. In addition, the materials of the heat sensitive medium layers in the first absorption plate 321 and the second absorption plate 322 may be the same or different, the suspended microbridge structure 40 is configured to include a plurality of absorption plates 32, and the heights of the resonant cavities corresponding to the heat sensitive medium layers in different absorption plates 32 are different, so that the infrared detector can absorb infrared radiation of different bands. Wherein the first interconnection column 7 directly electrically connects the support base 42 and the beam structure 31 closest to the CMOS measurement circuitry 1, and the second interconnection column 10 directly electrically connects the absorber plate 32 closest to the CMOS measurement circuitry 1 and the beam structure 31 closest to the absorber plate 32.

Fig. 26 is a schematic cross-sectional structure diagram of another infrared detector pixel provided in an embodiment of the present invention, and the infrared detector pixel having the structure shown in fig. 26 is also applicable to the method for manufacturing an infrared detector described in the above embodiment. The infrared detector arrangement beam structure 31 of the structure shown in fig. 26 is located on the side of the absorber plate 32 remote from the CMOS measurement circuitry 1, and the suspended microbridge structure 40 exemplarily provided in fig. 26 includes a layer of the beam structure 31 and a layer of the absorber plate 32. Specifically, the electrode layer in the absorption plate 32 is electrically connected to the electrode layer in the beam structure 31 through the second interconnection column 10, the electrode layer in the beam structure 31 is electrically connected to the support base 42 through the first interconnection column 7, and the electrical signal converted by the infrared signal in the absorption plate 32 is transmitted to the CMOS measurement circuit system 1 through the second interconnection column 10, the beam structure 31, the first interconnection column 7 and the support base 42 in sequence.

In some embodiments, it may be provided that the absorber plate 32 is formed with at least one hole-like structure, which penetrates at least the medium layer in the absorber plate 32; and/or, at least one hole-shaped structure is formed on the beam structure 31, that is, only the absorption plate 32 is formed with a hole-shaped structure, only the beam structure 31 is formed with a hole-shaped structure, or both the absorption plate 32 and the beam structure 31 are formed with a hole-shaped structure. For example, whether the hole structures on the absorption plate 32 or the beam structures 31, the hole structures may be circular hole structures, square hole structures, polygonal hole structures, or irregular pattern hole structures, the shape of the hole structures on the absorption plate 32 and the beam structures 31 is not specifically limited in the embodiment of the present invention, and the number of the hole structures on the absorption plate 32 and the beam structures 31 is not specifically limited in the embodiment of the present invention. Therefore, at least one hole-shaped structure is formed on the absorption plate 32, the hole-shaped structure at least penetrates through the dielectric layer in the absorption plate 32, the infrared detectors are all provided with sacrificial layers which are contacted with the absorption plate 32 and need to be released finally, the sacrificial layers need to be corroded by chemical reagents at the end of the infrared detector manufacturing process when the sacrificial layers are released, and the hole-shaped structures on the absorption plate 32 are beneficial to increasing the contact area of the chemical reagents for releasing and the sacrificial layers and accelerating the release rate of the sacrificial layers. In addition, the area of the absorption plate 32 is larger than that of the beam structure 31, the hole-shaped structure on the absorption plate 32 is beneficial to releasing the internal stress of the absorption plate 32, the planarization degree of the absorption plate 32 is optimized, the structural stability of the absorption plate 32 is improved, and the structural stability of the whole infrared detector is improved. In addition, at least one hole-shaped structure is formed on the beam structure 31, which is beneficial to further reducing the thermal conductance of the beam structure 31 and improving the infrared detection sensitivity of the infrared detector.

In some embodiments, a hermetic release barrier, i.e., the first dielectric layer 5, is used to protect the CMOS measurement circuitry 1 from process effects during the release etch process used to fabricate the CMOS infrared sensing structure 2. In some embodiments, the close release isolation layer is located at the interface between the CMOS measurement circuitry 1 and the CMOS infrared sensing structure 2 and/or in the CMOS infrared sensing structure 2, that is, the close release isolation layer may be located at the interface between the CMOS measurement circuitry 1 and the CMOS infrared sensing structure 2, or the close release isolation layer may be located in the CMOS infrared sensing structure 2, or the interface between the CMOS measurement circuitry 1 and the CMOS infrared sensing structure 2 may be provided with a close release isolation layer and the CMOS infrared sensing structure 2 is provided with a close release isolation layer, and the close release isolation layer is used to protect the CMOS measurement circuitry 1 from corrosion when the sacrificial layer is released by the etching process.

In some embodiments, a hermetic release isolation layer is located in the CMOS infrared sensing structure 2, and the hermetic release isolation layer may be, for example, a dielectric layer or multiple dielectric layers located above the reflective layer, i.e., the first metal interconnection layer 4, as shown in fig. 22, where fig. 22 exemplarily shows that the hermetic release isolation layer is a dielectric layer, and the material constituting the hermetic release isolation layer may include at least one of silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, silicon germanium alloy, amorphous carbon, or aluminum oxide, and the thickness of the hermetic release isolation layer is smaller than that of the first sacrificial layer. The resonant cavity of the infrared detector is realized by releasing the vacuum cavity behind the silicon oxide sacrificial layer, the sacrificial layer is positioned between the reflecting layer and the suspended microbridge structure, and when at least one layer of airtight release isolating layer positioned on the reflecting layer is arranged and materials such as silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, silicon-germanium alloy, amorphous carbon or aluminum oxide are selected as one part of the resonant cavity, the reflection effect of the reflecting layer is not influenced, the height of the resonant cavity can be reduced, the thickness of the first sacrificial layer is further reduced, and the release difficulty of the first sacrificial layer formed by silicon oxide is reduced. In addition, a closed release isolation layer and the first interconnection column 7 are arranged to form a closed structure, so that the CMOS measurement circuit system 1 is completely separated from the first sacrificial layer, and the CMOS measurement circuit system 1 is protected.

In some embodiments, a hermetic release isolation layer may also be provided at the interface between the CMOS measurement circuitry 1 and the CMOS infrared sensing structure 2, for example, the hermetic release isolation layer is located between the reflective layer and the CMOS measurement circuitry 1, i.e., the hermetic release isolation layer is located under the metal interconnection layer of the reflective layer, and the support base 42 is electrically connected to the CMOS measurement circuitry 1 through a through hole penetrating the hermetic release isolation layer. Specifically, because the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are both formed by using a CMOS process, after the CMOS measurement circuit system 1 is formed, a wafer including the CMOS measurement circuit system 1 is formed by preparation and is transferred to a next process to form the CMOS infrared sensing structure 2, because silicon oxide is the most common dielectric material in the CMOS process, and silicon oxide is mostly used as an insulating layer between metal layers on the CMOS circuit, if no insulating layer is used as a barrier when silicon oxide with a thickness of about 2um is corroded, the circuit will be seriously affected, and in order to ensure that the silicon oxide medium on the CMOS measurement circuit system 1 is not corroded when a sacrificial layer of silicon oxide is released, a closed release insulating layer is provided at an interface between the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2.

Illustratively, the material constituting the hermetic release barrier layer may include at least one of silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, a silicon germanium alloy, amorphous carbon, or aluminum oxide. Specifically, silicon carbide, silicon carbonitride, silicon nitride, amorphous silicon, amorphous germanium, amorphous silicon germanium, silicon, germanium, a silicon germanium alloy, amorphous carbon, or aluminum oxide are all CMOS process corrosion resistant materials, i.e., these materials are not corroded by the sacrificial layer release agent, so the hermetic release barrier layer can be used to protect the CMOS measurement circuitry 1 from corrosion when the corrosion process is performed to release the sacrificial layer. In addition, the closed release isolation layer covers the CMOS measurement circuit system 1, and the closed release isolation layer can also be used for protecting the CMOS measurement circuit system 1 from being influenced by the process in the release etching process for manufacturing the CMOS infrared sensing structure 2. In addition, when at least one layer of airtight release isolation layer is arranged on the reflection layer, the material for forming the airtight release isolation layer comprises at least one of silicon, germanium, silicon-germanium alloy, amorphous silicon, amorphous germanium, amorphous silicon-germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride or silicon carbonitride, when the airtight release isolation layer is arranged to improve the stability of the first interconnection column 7, the airtight release isolation layer hardly influences the reflection process in the resonant cavity, the influence of the airtight release isolation layer on the reflection process of the resonant cavity can be avoided, and the influence of the airtight release isolation layer on the detection sensitivity of the infrared detector is further avoided.

The CMOS fabrication process of the CMOS infrared sensing structure 2 includes a Metal interconnection process, a via process, an IMD (Inter Metal Dielectric) process, and an RDL (re-wiring) process. Specifically, the metal interconnection process is used to achieve electrical connection between upper and lower metal interconnection layers, for example, to achieve electrical connection between a conductive layer in the first interconnection pillar 7 and the supporting pedestal 42, the via process is used to form an interconnection via for connecting the upper and lower metal interconnection layers, for example, to form an interconnection via for connecting the conductive layer in the first interconnection pillar 7 and the supporting pedestal, the IMD process is used to achieve isolation between the upper and lower metal interconnection layers, that is, electrical insulation, for example, to achieve electrical insulation between the electrode layers in the absorber plate 32 and the beam structure 31 and the reflector plate 41, the RDL process is a redistribution layer process, that is, a process in which a layer of metal is re-laid above the top metal layer of the circuit and is electrically connected with the top metal layer of the circuit, for example, a tungsten pillar, the RDL process may be used to prepare the reflective layer in the infrared detector on the top metal layer of the CMOS measurement circuit system 1, and the supporting pedestal 42 on the reflective layer is electrically connected with the top metal layer of the CMOS measurement circuit system 1. In addition, the CMOS manufacturing process of the CMOS measurement circuit system 1 may also include a metal interconnection process and a via process, the CMOS measurement circuit system 1 includes metal interconnection layers, dielectric layers, and a silicon substrate at the bottom, which are disposed at intervals, and the upper and lower metal interconnection layers are electrically connected through vias.

In some embodiments, the infrared detector may further include a metamaterial structure and/or a polarization structure, the metamaterial structure or the polarization structure is at least one metal interconnection layer, the metamaterial structure formed by using the patterned structure is combined with the infrared detector structure, the infrared electromagnetic wave absorbed by the metamaterial structure can enhance the infrared electromagnetic wave signal absorbed by the infrared detector, the infrared electromagnetic wave absorbed by the metamaterial structure is overlapped with the infrared electromagnetic wave absorbed by the microbridge detector structure, and the infrared electromagnetic wave absorbed by the metamaterial structure is coupled with the component of the incident infrared electromagnetic wave, that is, the metamaterial structure is configured to increase the intensity of the absorbed infrared electromagnetic wave signal, so as to increase the absorption rate of the infrared electromagnetic wave by the infrared detector. In addition, the polarization structure and the uncooled infrared detector are integrated in a single chip, so that the polarization sensitive infrared detector can be integrated in a single chip, the difficulty of optical design is greatly reduced, an optical system is simplified, optical elements are reduced, and the cost of the optical system is reduced. In addition, the image collected by the single-chip integrated polarization uncooled infrared detector is original infrared image information, the CMOS measuring circuit system 1 can obtain accurate image information only by processing signals detected by the infrared detector, image fusion of the existing detector is not needed, and authenticity and effectiveness of the image are greatly improved.

In some embodiments, at least one patterned metal interconnection layer may be disposed between the reflective layer and the suspended microbridge structure, the patterned metal interconnection layer is located above or below the hermetic release barrier layer and is electrically insulated from the reflective layer, and the patterned metal interconnection layer is used for adjusting a resonance mode of the infrared detector. Specifically, a Bragg reflector (Bragg reflector) is an optical device for enhancing reflection of light with different wavelengths by utilizing constructive interference of reflected light with different interfaces, and the Bragg reflector is composed of a plurality of 1/4 wavelength reflectors so as to realize efficient reflection of incident light with a plurality of wavelengths.

In some embodiments, the infrared detector may be configured based on a 3nm, 7nm, 10nm, 14nm, 22nm, 28nm, 32nm, 45nm, 65nm, 90nm, 130nm, 150nm, 180nm, 250nm, or 350nm CMOS process that characterizes process nodes of the integrated circuit, i.e., features during processing of the integrated circuit. In addition, the metal wiring material constituting the metal interconnection layer in the infrared detector may be configured to include at least one of aluminum, copper, tungsten, titanium, nickel, chromium, platinum, silver, ruthenium, or cobalt, and for example, the material constituting the reflective layer may be configured to include at least one of aluminum, copper, tungsten, titanium, nickel, chromium, platinum, silver, ruthenium, or cobalt. In addition, the CMOS measuring circuit system 1 and the CMOS infrared sensing structure 2 are both prepared by using a CMOS process, the CMOS infrared sensing structure 2 is directly prepared on the CMOS measuring circuit system 1, the radial side length of the first interconnection column 7 and the radial side length of the second interconnection column 10 can be more than or equal to 0.5um and less than or equal to 3um, the width of the beam structure 31, namely the width of a single line in the beam structure 31 is less than or equal to 0.3um, and the height of the resonant cavity is less than or equal to 2.5um.

It should be noted that, some of the individual steps described in the embodiments of the present invention include multiple implementation manners, and different implementation manners between the supplements may be combined at will, which all belong to the protection scope of the present application.

It is noted that, in this document, relational terms such as "first" and "second," and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a component of' 8230; \8230;" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.

The above are merely exemplary embodiments of the present invention, which can be understood and implemented by those skilled in the art. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A preparation method of a CMOS infrared detector with a solid column is characterized by comprising the following steps:

providing a substrate;

the CMOS infrared sensing structure is directly prepared on the CMOS measuring circuit system by adopting a CMOS process, and the CMOS infrared sensing structure comprises the following components:

step 2, depositing a first dielectric layer; the first dielectric layer is a closed release isolation layer;

step 3, depositing a first sacrificial layer on the first dielectric layer;

step 4, preparing a first interconnection column by adopting a through hole process and a CMP planarization process;

step 7, depositing to form a second sacrificial layer;

step 8, depositing a fourth metal interconnection layer and a second dielectric layer, and etching the fourth metal interconnection layer to form a second patterned electrode structure so as to form an absorption plate; the second dielectric layer is a heat sensitive dielectric layer;

after the step 4, further comprising: and depositing a first reinforcing layer by adopting a PVD (physical vapor deposition) process or a CVD (chemical vapor deposition) process, and etching the first reinforcing layer to form a reinforcing structure arranged at a position corresponding to the second interconnection column, wherein the reinforcing structure is positioned between the first interconnection column and the second interconnection column, and the reinforcing structure is used for heightening the first patterned electrode structure arranged at the position corresponding to the second interconnection column so as to optimize the electric contact performance of the first patterned electrode structure and the second interconnection column in the beam structure.

2. The method for manufacturing a CMOS infrared detector having a solid pillar according to claim 1, wherein a CMOS measurement circuit system is manufactured on the substrate using a CMOS process, comprising:

preparing a process layer in the CMOS measuring circuit system by adopting an oxidation process, a deposition process and a doping process;

positioning the interval by adopting a photoetching process to transfer the digitized pattern to the CMOS measuring circuit system;

and removing the material of the set area in the CMOS measuring circuit system by adopting an etching process.

3. The method for manufacturing a CMOS infrared detector with solid pillars according to claim 1, wherein the step 1 of manufacturing a first metal interconnection layer on a top metal layer of the CMOS measurement circuitry by using an RDL process includes:

depositing a first insulating layer on the CMOS measuring circuit system, and processing the surface of the first insulating layer by adopting a CMP (chemical mechanical polishing) process;

etching a first through hole on the first insulation layer after planarization;

depositing metal tungsten by adopting a PVD (physical vapor deposition) process to fill the first through hole, or depositing metal copper by adopting an ECP (electro-plating) process to fill the first through hole;

processing the surface of the first through hole by adopting a CMP (chemical mechanical polishing) process;

depositing a metal layer on the surface of the first through hole, and etching the metal layer to form the first metal interconnection layer;

the step 1 of using the top metal of the CMOS measurement circuit system as a first metal interconnection layer includes:

and processing the surface of the CMOS measuring circuit system by adopting a CMP process.

4. The method for manufacturing a CMOS infrared detector having a solid pillar according to claim 1, wherein the step 2 is performed after the step 1, and the step 2 specifically includes:

depositing the first dielectric layer on the first metal interconnection layer by adopting a CVD (chemical vapor deposition) process;

or, the step 1 prepares a first metal interconnection layer on a top metal layer of the CMOS measurement circuit system by using an RDL process, and the step 2 is performed before the step 1, where the step 2 specifically includes:

processing the surface of the CMOS measuring circuit system by adopting a CMP process;

depositing the first dielectric layer on the surface of the CMOS measuring circuit system by adopting a CVD (chemical vapor deposition) process;

the first dielectric layer is used for protecting the CMOS measuring circuit system from being influenced by the process in the release etching process of manufacturing the CMOS infrared sensing structure.

5. The method for manufacturing a CMOS infrared detector having a solid pillar according to claim 1, wherein the first sacrificial layer is made of silicon oxide manufactured by a thermal oxidation process or a CVD process, and the second sacrificial layer is made of silicon oxide manufactured by a thermal oxidation process or a CVD process;

after the step 8, the preparation method further includes:

and etching the first sacrificial layer and the second sacrificial layer by adopting a release process, so that the beam structure and the absorption plate are suspended in the first dielectric layer to form the suspended CMOS infrared sensing structure.

6. The method for manufacturing a CMOS infrared detector having a solid pillar as set forth in claim 1, wherein the step 4 specifically includes:

etching the first sacrificial layer to form a columnar through hole;

depositing metal tungsten or metal copper within the pillar-shaped via to form the first interconnect pillar;

or, the step 4 specifically includes:

etching the first sacrificial layer to form a columnar through hole;

depositing an adhesion layer in the columnar through hole; wherein the material forming the adhesion layer comprises at least one of titanium, titanium nitride, tantalum or tantalum nitride;

depositing metal tungsten or metal copper on the adhesion layer of the columnar through hole to form the first interconnection column;

or, the step 4 specifically includes:

etching the first sacrificial layer to form a columnar through hole;

depositing a second insulating layer in the columnar through hole by adopting a CVD (chemical vapor deposition) process; wherein the material forming the second insulating layer comprises at least one of silicon carbide, silicon carbonitride, silicon nitride, silicon, germanium, silicon germanium, amorphous carbon or aluminum oxide;

etching the second insulating layer to form a second through hole;

depositing metal tungsten or metal copper within the second via to form the first interconnect pillar;

or, the step 4 specifically includes:

etching the first sacrificial layer to form a columnar through hole;

etching the second insulating layer to form a second through hole;

depositing an adhesion layer in the second through hole; wherein the material forming the adhesion layer comprises at least one of titanium, titanium nitride, tantalum or tantalum nitride;

depositing metal tungsten or metal copper on the adhesion layer of the second via to form the first interconnection pillar;

wherein the CMOS infrared sensing structure comprises at least two first interconnection pillars, including at least one discrete interconnection pillar.

7. The method for manufacturing a CMOS infrared detector having a solid pillar according to claim 1, wherein the step 5 specifically includes:

preparing the second metal interconnection layer by adopting a PVD (physical vapor deposition) process or a CVD (chemical vapor deposition) process, and etching the second metal interconnection layer to form the first patterned electrode structure so as to form the beam structure;

or, the step 5 specifically includes:

preparing a third dielectric layer by adopting a CVD (chemical vapor deposition) process; the third dielectric layer is a supporting layer of the beam structure, and the material forming the third dielectric layer comprises at least one of amorphous silicon, amorphous germanium-silicon, aluminum oxide or amorphous carbon;

preparing the second metal interconnection layer on the third dielectric layer by adopting a PVD (physical vapor deposition) process or a CVD (chemical vapor deposition) process, etching the second metal interconnection layer to form the first patterned electrode structure, and etching the third dielectric layer to form the patterned dielectric layer to form the beam structure;

or, the step 5 specifically includes:

preparing the second metal interconnection layer by adopting a PVD (physical vapor deposition) process or a CVD (chemical vapor deposition) process;

preparing a fourth dielectric layer on the second metal interconnection layer by adopting a CVD (chemical vapor deposition) process, etching the fourth dielectric layer to form a patterned dielectric layer, and etching the second metal interconnection layer to form the first patterned electrode structure so as to form the beam structure; the fourth dielectric layer is a passivation layer of the beam structure, and the material forming the fourth dielectric layer comprises at least one of amorphous silicon, amorphous germanium-silicon, aluminum oxide or amorphous carbon;

or, the step 5 specifically includes:

preparing a third dielectric layer by adopting a CVD (chemical vapor deposition) process; the third dielectric layer is a supporting layer of the beam structure, and the material of the third dielectric layer comprises at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, aluminum oxide or amorphous carbon;

preparing the second metal interconnection layer on the third dielectric layer by adopting a PVD (physical vapor deposition) process or a CVD (chemical vapor deposition) process;

preparing a fourth dielectric layer on the second metal interconnection layer by adopting a CVD (chemical vapor deposition) process, etching the fourth dielectric layer to form a patterned dielectric layer, etching the second metal interconnection layer to form the first patterned electrode structure, and etching the third dielectric layer to form the patterned dielectric layer to form the beam structure; the fourth dielectric layer is a passivation layer of the beam structure, and the material forming the fourth dielectric layer comprises at least one of amorphous silicon, amorphous germanium-silicon, aluminum oxide or amorphous carbon;

wherein a material constituting the second metal interconnection layer includes at least one of titanium, titanium nitride, tantalum nitride, a titanium tungsten alloy, a nickel chromium alloy, a nickel platinum alloy, a nickel silicon alloy, nickel, chromium, platinum, tungsten, aluminum, or copper.

8. The method for manufacturing a CMOS infrared detector having a solid pillar according to claim 1, wherein the step 7 specifically includes:

depositing the second sacrificial layer;

processing the surface of the second sacrificial layer by adopting a CMP (chemical mechanical polishing) process; wherein the CMP process is stopped to an upper surface of the third metal interconnect layer;

alternatively, after the step 6, the preparation method further comprises:

depositing a third insulating layer on the second interconnection pillar using a CVD process;

the step 7 specifically includes:

depositing the second sacrificial layer;

processing the surface of the second sacrificial layer by adopting a CMP (chemical mechanical polishing) process; wherein the CMP process is stopped to an upper surface of the third metal interconnection layer or the third insulating layer;

wherein the material forming the third insulating layer comprises at least one of silicon carbide, silicon carbonitride, silicon nitride, silicon, germanium, silicon germanium, amorphous carbon or aluminum oxide;

wherein the material forming the third metal interconnection layer comprises metal aluminum, the CMOS infrared sensing structure comprises at least two second interconnection columns, and the second interconnection columns comprise at least one discrete interconnection column.

9. The method for manufacturing a CMOS infrared detector having a solid pillar according to claim 1, wherein the step 8 specifically includes:

preparing the fourth metal interconnection layer by adopting a PVD (physical vapor deposition) process or a CVD (chemical vapor deposition) process;

preparing the second dielectric layer on the fourth metal interconnection layer by adopting a PVD (physical vapor deposition) process or a CVD (chemical vapor deposition) process, photoetching the second dielectric layer to form a patterned dielectric layer, and etching the fourth metal interconnection layer to form the second patterned electrode structure to form the absorption plate;

or, the step 8 specifically includes:

preparing the second dielectric layer by adopting a PVD (physical vapor deposition) process or a CVD (chemical vapor deposition) process;

preparing the fourth metal interconnection layer on the second dielectric layer by adopting a PVD (physical vapor deposition) process or a CVD (chemical vapor deposition) process, etching the fourth metal interconnection layer to form the second patterned electrode structure, and photoetching the second dielectric layer to form the patterned dielectric layer to form the absorption plate;

the fourth metal interconnection layer is made of a material including at least one of titanium, titanium nitride, tantalum nitride, titanium-tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, nickel-silicon alloy, nickel, chromium, platinum, tungsten, aluminum or copper, and the second dielectric layer is made of at least one of materials with a temperature coefficient of resistance greater than a set value, wherein the materials of the fourth metal interconnection layer include at least one of titanium oxide, vanadium oxide, titanium vanadium oxide, silicon, germanium, silicon germanium oxide, amorphous carbon, graphene, yttrium barium copper oxide, copper or platinum.

10. The method for manufacturing a CMOS infrared detector having a solid pillar according to claim 1, wherein before the step 8 of manufacturing the fourth metal interconnection layer and the second dielectric layer, the method further comprises:

preparing a fifth dielectric layer by adopting a CVD (chemical vapor deposition) process and etching the fifth dielectric layer to form a graphical dielectric layer; the fifth dielectric layer is a supporting layer of the absorption plate, and the material forming the fifth dielectric layer comprises at least one of silicon carbide, silicon carbonitride, silicon nitride, silicon, germanium, silicon germanium, amorphous carbon or aluminum oxide;

and/or after the fourth metal interconnection layer and the second dielectric layer are prepared, the step 8 further comprises:

preparing a sixth dielectric layer by adopting a CVD (chemical vapor deposition) process and etching the sixth dielectric layer to form a graphical dielectric layer; the sixth dielectric layer is a passivation layer of the absorption plate, and the material forming the sixth dielectric layer includes at least one of silicon carbide, silicon carbonitride, silicon nitride, silicon, germanium, silicon germanium, amorphous carbon or aluminum oxide.

11. The method for manufacturing a CMOS infrared detector having a solid pillar according to claim 1, wherein a material constituting the first reinforcing layer includes at least one of amorphous carbon, silicon carbide, aluminum oxide, silicon nitride, silicon carbonitride, silicon oxide, silicon, germanium, silicon germanium, aluminum, copper, tungsten, gold, platinum, nickel, chromium, titanium tungsten alloy, nickel-chromium alloy, nickel-platinum alloy, or nickel-silicon alloy;

after the step 7, the method further comprises the following steps:

depositing a second reinforcing layer at a position corresponding to the second interconnection column by using a PVD (physical vapor deposition) process or a CVD (chemical vapor deposition) process, and etching the second reinforcing layer to form a reinforcing structure corresponding to the absorption plate; the second reinforcing layer is made of at least one of amorphous carbon, silicon carbide, aluminum oxide, silicon nitride, silicon carbonitride, silicon oxide, silicon, germanium, silicon germanium, aluminum, copper, tungsten, gold, platinum, nickel, chromium, titanium-tungsten alloy, nickel-chromium alloy, nickel-platinum alloy or nickel-silicon alloy.

12. An infrared detector, which is prepared by the method for preparing a CMOS infrared detector with a solid pillar according to any one of claims 1 to 11, the infrared detector comprising:

the CMOS measurement circuitry and the CMOS infrared sensing structure;

the CMOS infrared sensing structure comprises a resonant cavity formed by the reflecting layer and the heat sensitive medium layer and a suspended micro-bridge structure for controlling heat transfer, the suspended micro-bridge structure comprises at least one layer of beam structure and at least one layer of absorption plate, and the beam structure is positioned on one side of the absorption plate close to the CMOS measuring circuit system;