CN113938212B - Direct current offset eliminating circuit with switchable bandwidth - Google Patents
Direct current offset eliminating circuit with switchable bandwidth Download PDFInfo
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- CN113938212B CN113938212B CN202111408994.7A CN202111408994A CN113938212B CN 113938212 B CN113938212 B CN 113938212B CN 202111408994 A CN202111408994 A CN 202111408994A CN 113938212 B CN113938212 B CN 113938212B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
- H04B10/69—Electrical arrangements in the receiver
- H04B10/697—Arrangements for reducing noise and distortion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/66—Non-coherent receivers, e.g. using direct detection
- H04B10/69—Electrical arrangements in the receiver
- H04B10/693—Arrangements for optimizing the preamplifier in the receiver
- H04B10/6933—Offset control of the differential preamplifier
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention discloses a direct current offset cancellation circuit with switchable bandwidth, which comprises: the peak pulse generating circuit is used for detecting the signal amplitude at a node in the main external radio frequency path and outputting a pulse signal when the signal amplitude changes; the low-pass filter circuit comprises an extraction unit and a feedforward switch unit, wherein the extraction unit is used for extracting a direct current signal in a radio frequency signal output by an output end of a radio frequency amplifier in an external radio frequency main circuit, and the feedforward switch unit is used for switching the bandwidth of the low-pass filter circuit from a low cut-off state to a high cut-off state according to a pulse signal, transmitting the direct current signal to an operational amplifier for amplification and then outputting the direct current signal; and the direct current offset feedback circuit is used for feeding back the amplified direct current signal to the input end of a radio frequency amplifier in the external radio frequency main circuit in an inverted form to counteract the direct current offset of the external radio frequency main circuit until the direct current signal extracted by the low-pass filter circuit is balanced. The invention can accelerate the speed of eliminating the direct current deviation in the radio frequency main circuit.
Description
Technical Field
The invention belongs to the technical field of direct current offset cancellation circuits, and particularly relates to a direct current offset cancellation circuit with switchable bandwidth.
Background
As a basic module, an amplifier is now the basis of various functional circuits. For a multi-stage differential amplifier, if a dc offset is introduced at the input or the output of the first stage due to manufacturing process variations, the offset will be further amplified by the subsequent multi-stage amplifier, resulting in a deviation of the output dc. In addition, due to the characteristics of the partial amplifier, in the case of single-ended input and differential output, if the input amplitude changes, the amplifier may be saturated at this time. The traditional solution is to use a dc offset cancellation circuit to cancel the dc offset at the output due to process variation or dc level offset at the input.
Fig. 1 is a schematic diagram of a circuit of a general dc offset cancellation circuit in the prior art, where the dc offset cancellation circuit is composed of a low-pass filter, an operational amplifier, and a feedback unit. The resistor R3, the resistor R4 and the capacitor C3 form a low-pass filter; the transistor M3 and the resistor R5 constitute a feedback unit. One end of the resistor R3 is connected with the radio frequency main circuit and used for collecting direct current signals in the radio frequency main circuit, the collected direct current signals are amplified through the operational amplifier U1 and fed back to the radio frequency main circuit in an opposite mode through the transistor M3, direct current deviation of the radio frequency main circuit is offset, negative feedback is formed due to the whole loop, and finally the direct current deviation on the radio frequency main circuit is 0 when the radio frequency main circuit is stable. Although the dc offset cancellation circuit shown in fig. 1 can eliminate the dc offset in the main rf circuit, the low-pass filter circuit composed of the resistor R3, the resistor R4 and the capacitor C3 has a low bandwidth, which causes the low-pass filter circuit to have a very large time constant, and affects the speed of the dc offset cancellation circuit in eliminating the dc offset in the main rf circuit.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a direct current offset cancellation circuit with switchable bandwidth, which can switch the bandwidth of a low-pass filter circuit according to the change condition of the signal amplitude in an external radio frequency main circuit, so that the bandwidth of the low-pass filter circuit is switched from a low cut-off state to a high cut-off state when the signal amplitude in the external radio frequency main circuit is changed, and the speed of eliminating direct current offset in the radio frequency main circuit is accelerated.
In order to achieve the above object, the present invention provides a dc offset cancellation circuit with switchable bandwidth, which comprises a peak pulse generation circuit, a low pass filter circuit, an operational amplifier and a dc offset feedback circuit, wherein,
the peak pulse generating circuit is used for detecting the signal amplitude at a node in the external radio frequency main circuit and outputting a pulse signal when the signal amplitude changes;
the low-pass filter circuit comprises an extraction unit and a feedforward switch unit, wherein the extraction unit is used for extracting a direct current signal in a radio frequency signal output by an output end of a radio frequency amplifier in an external radio frequency main circuit, and the feedforward switch unit is used for switching the bandwidth of the low-pass filter circuit from a low cut-off state to a high cut-off state according to the pulse signal, transmitting the direct current signal to the operational amplifier for amplification and then outputting the direct current signal;
the dc offset feedback circuit is configured to feed back the amplified dc signal to an input end of a radio frequency amplifier in the main external radio frequency circuit in an inverted form, so as to offset a dc offset of the main external radio frequency circuit until the dc signal extracted by the low-pass filter circuit is balanced.
Because the peak pulse generating circuit and the feedforward switch unit are introduced into the feedback loop, when the signal amplitude of the radio frequency main circuit is changed, the peak pulse generating circuit generates transient pulses, the bandwidth of the low-pass filter circuit is changed, the time domain signal convergence speed is accelerated, and the speed of eliminating the direct current deviation is accelerated; and because the pulse width is limited, the bandwidth of the low-pass filter circuit will only occur when the input changes, ensuring that a lower cut-off frequency can be maintained in steady state.
In one embodiment, the peak pulse generating circuit is connected to a node near the input end of the main external rf circuit, and the dc offset feedback circuit is connected to the input ends of the rest of the rf amplifiers except the first stage rf amplifier in the main external rf circuit.
In one embodiment, the peak pulse generating circuit is further configured to amplify the pulse signal amplitude to a pulse signal of 0-VDD, and output the pulse signal of 0-VDD to the feedforward switching unit after extending the width of the pulse signal.
In one embodiment, the peak pulse generating circuit comprises a blocking capacitor, a multi-stage amplifier and an even number of first inverters, one end of the blocking capacitor is connected with a node in the external radio frequency main circuit, and the other end of the blocking capacitor is connected with the feedforward switch unit sequentially through amplifiers connected in series and inverters connected in series; and each stage of amplifier comprises a second phase inverter and a load resistor, wherein one end of the load resistor is respectively connected with the grid electrode of an NMOS tube and the grid electrode of a PMOS tube in the second phase inverter, and the other end of the load resistor is respectively connected with the drain electrode of the NMOS tube and the drain electrode of the PMOS tube in the second phase inverter.
In one embodiment, the feedforward switch unit includes a transistor M1, the extraction unit includes a resistor R1, a resistor R2, and a capacitor C1, one end of the resistor R1 is connected to an output terminal of a radio frequency amplifier in the main external radio frequency circuit, the other end of the resistor R1 is respectively connected to one end of the resistor R2 and a drain of the transistor M1, the other end of the resistor R2 is respectively connected to a source of the transistor M1, one end of the capacitor C1, and an input terminal of the operational amplifier, a gate of the transistor M1 is connected to an output terminal of the peak pulse generating circuit, and the other end of the capacitor C1 is connected to an output terminal of the operational amplifier.
In one embodiment, the resistor R1 is a kilo-ohm resistor.
In one embodiment, the dc offset feedback circuit includes a transistor M2, a gate of the transistor M2 is connected to the output terminal of the operational amplifier, a source of the transistor M2 is grounded, and a drain of the transistor M2 is connected to an input terminal of a rf amplifier in the external rf main circuit.
Drawings
FIG. 1 is a schematic circuit diagram of a prior art DC offset cancellation circuit;
fig. 2 is a diagram of an architecture of a dc offset cancellation circuit with switchable bandwidth according to an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a peak pulse generating circuit according to an embodiment of the present invention;
fig. 4 is a schematic block diagram of the bandwidth-switchable dc offset cancellation circuit applied to a front-end system of a photo-receiver according to the present invention;
FIG. 5 is a schematic circuit diagram of a switchable bandwidth DC offset cancellation circuit according to an embodiment of the present invention;
FIG. 6 is a graph showing frequency response curves of a system under different conditions according to an embodiment of the present invention;
FIG. 7 is a time domain simulation result under the prior art;
fig. 8 is a time domain simulation result provided by the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
Fig. 2 is a schematic diagram of a dc offset cancellation circuit with switchable bandwidth according to an embodiment of the present invention, as shown in fig. 2, the dc offset cancellation circuit includes a peak pulse generating circuit 100, a low pass filter circuit 200, an operational amplifier 300, and a dc offset feedback circuit 400.
The peak pulse generating circuit 100 is configured to detect a signal amplitude at a node in the main external radio frequency circuit, and output a pulse signal when the signal amplitude changes. Since the dc offset generated by the main rf circuit is usually generated at the input terminal of the main rf circuit or the output terminal of the first stage rf amplifier therein, the peak pulse generating circuit 100 is preferably connected to a node of the main rf circuit near the input terminal thereof for improving the detection accuracy.
The low-pass filter circuit 200 comprises an extraction unit 210 and a feed-forward switch unit 220, wherein the extraction unit 210 is used for extracting a direct current signal from the radio frequency signals output by any one of the radio frequency amplifier output ends in the external radio frequency main path; the feedforward switch unit 220 is configured to switch the bandwidth of the low-pass filter circuit 200 from a low-off state to a high-off state according to the pulse signal output by the peak pulse generating circuit 100, and send the dc signal extracted by the extracting unit 210 to the operational amplifier 300 for amplification and output. In order to better drive the feedforward switch unit 220 in the low-pass filter circuit 200 to complete the broadband switching, the peak pulse generating circuit 100 provided in this embodiment may also be configured to amplify the pulse signal to a pulse signal with an amplitude of 0-VDD, and output the amplified pulse signal to the feedforward switch unit 220 after the width of the pulse signal is extended.
The dc offset feedback circuit 400 is configured to feed back the dc signal amplified by the operational amplifier 300 to an input terminal of a radio frequency amplifier in an external main radio frequency circuit in an inverted form, so as to cancel the dc offset of the main radio frequency circuit until the dc signal extracted by the low-pass filter circuit 200 is balanced. In order to achieve a better dc offset suppression effect, the dc offset feedback circuit 400 is preferably connected to the input terminals of the rest of the rf amplifiers in the external rf main path except the first stage rf amplifier.
It should be noted that each unit circuit in the dc offset cancellation circuit with switchable bandwidth provided in this embodiment needs to be designed correspondingly according to different types of the connected main rf circuit, and when the connected main rf circuit is a differential output, each unit circuit provided in this embodiment needs to use a differential circuit; when the accessed main rf path is a single-ended output, if the input of the main rf path is a single-ended input, the single-ended circuit may be selected by each unit circuit provided in this embodiment, and if the input of the main rf path is a differential input, the differential circuit may be selected by each unit circuit provided in this embodiment, which will be described in detail in the following embodiments.
In the dc offset cancellation circuit with switchable bandwidth provided in this embodiment, because the peak pulse generating circuit 100 and the feedforward switching unit 220 are introduced into the feedback loop, when the amplitude of the signal of the main rf path is changed, the peak pulse generating circuit 100 generates a short pulse, the bandwidth of the low-pass filter circuit 200 is changed, and the convergence rate of the time domain signal is increased, that is, the speed of eliminating the dc offset is increased; and since the pulse width is limited, the bandwidth of the low pass filter circuit 200 will only occur when the input changes, ensuring that a lower cut-off frequency can be maintained in steady state.
In one embodiment, as shown in fig. 3, the peak pulse generating circuit 100 may include a dc blocking capacitor C2, a multi-stage amplifier, and an even number of first inverters, wherein one end of the dc blocking capacitor C2 is connected to a node in the external rf main circuit, and the other end of the dc blocking capacitor C2 is connected to the feedforward switching unit 220 through the amplifiers connected in series and the inverters connected in series in sequence; and each stage of amplifier comprises a second phase inverter and a load resistor, one end of the load resistor is respectively connected with the grid electrode of the NMOS tube and the grid electrode of the PMOS tube in the second phase inverter, and the other end of the load resistor is respectively connected with the drain electrode of the NMOS tube and the drain electrode of the PMOS tube in the second phase inverter.
In the embodiment, the dc blocking capacitor C2 forms a high-pass network together with the input impedance in the back-end multi-stage amplifier, and is used for detecting the signal amplitude at a node in the main external radio frequency circuit and generating a pulse signal when the signal amplitude changes; the multistage amplifier is used for amplifying the amplitude of the pulse signal and amplifying the weak pulse signal into a pulse signal with the swing amplitude of 0-VDD; the even number of inverters is used to extend the width of the pulse signal of 0-VDD without inverting the signal. Specifically, the multistage amplifier can adopt a three-stage amplifier, and the even number of inverters can adopt 2 inverters, so that the peak pulse with the height of about 3mV and the width of about 5ns can be amplified and shaped to 0-VDD swing and 40ns peak pulse. The high output amplitude pulse is beneficial for driving the feedforward switch unit 220 in the low-pass filter circuit 200 to realize bandwidth switching.
In one embodiment, as shown in fig. 5, the feedforward switch unit 220 in the low-pass filter circuit 200 includes a transistor M1, the extraction unit 210 includes a resistor R1, a resistor R2, and a capacitor C1, one end of the resistor R1 is connected to an output end of a radio frequency amplifier in the external radio frequency main circuit, the other end of the resistor R1 is respectively connected to one end of the resistor R2 and a drain of the transistor M1, the other end of the resistor R2 is respectively connected to a source of the transistor M1, one end of the capacitor C1, and an input end of the operational amplifier, a gate of the transistor M1 is connected to an output end of the peak pulse generating circuit 100, and the other end of the capacitor C1 is connected to an output end of the operational amplifier. Specifically, the transistor M1 may be a MOS transistor, and certainly, an IGBT transistor may also be used, and the embodiment is not limited.
In this embodiment, the resistor R1 is used to ensure isolation of the rf signal in the rf main path, extract a dc component in the rf signal, and to ensure isolation of the rf signal more effectively, only extract the dc component in the rf signal, and the resistance of the resistor R1 may preferably be in the k Ω level. The resistor R2 is connected with the transistor M1 in parallel to form an adjustable resistor structure, a control end Vpulse of the adjustable resistor structure is connected with the peak pulse generating circuit 100, when the peak pulse generating circuit 100 detects that the amplitude of a signal on the radio frequency main circuit changes, the peak pulse generating circuit 100 outputs a high level to a grid electrode of the transistor M1, the transistor M1 is conducted, the resistor R2 is short-circuited, so that the bandwidth of the whole low-pass filter circuit is widened, the speed of the rear-end direct current offset feedback circuit 400 for offsetting direct current deviation in the radio frequency main circuit is increased, and finally, when the whole loop forms negative feedback, the direct current deviation on the radio frequency main circuit is 0; when the dc offset on the main rf circuit is 0, the peak pulse generating circuit 100 outputs a low level to the gate of the transistor M1, the transistor M1 is turned off, and the resistor R2 operates, so that the bandwidth of the low-pass filtering circuit 200 is narrowed, and the dc offset cancellation circuit is in a standby state.
To illustrate the present solution more clearly, the following description is made with reference to specific examples:
the invention provides a direct current offset cancellation circuit with switchable bandwidth, and for explaining a possible implementation manner of the direct current offset cancellation circuit, the direct current offset cancellation circuit is taken as an example to be applied to a front-end system of a photoelectric receiver to correspondingly explain. Fig. 4 is a schematic block diagram of the bandwidth-switchable dc offset cancellation circuit applied to a front-end system of a photoelectric receiver, and as can be seen from fig. 4, the front-end system of the photoelectric receiver is a single-ended input and differential output, and includes a transimpedance gain unit, a variable gain amplifier VGA1, a variable gain amplifier VGA2, an equalizer, and a buffer, and 5 stages of amplification units are provided in total, so that the gain of the overall system gain S parameter can reach over 40 dB.
In order to better eliminate the dc offset in the system, the input terminal of the peak pulse generating circuit 100 in the dc offset canceling circuit provided by the present invention may be connected to a node in the variable gain amplifier VGA1, the input terminal of the low pass filter circuit 200 may be connected to the output terminal of the variable gain amplifier VGA1, and the output terminal of the dc offset feedback circuit 400 may be connected to the output terminal of the buffer.
Fig. 5 is a schematic circuit diagram of the dc offset cancellation circuit with switchable bandwidth according to an embodiment of the present invention, and as shown in fig. 5, a resistor R1 is connected to a main rf circuit, and the resistor R1 with k Ω level is used to effectively ensure isolation of the dc offset cancellation circuit from the rf signal and only extract dc components; the resistor R2 is connected with the transistor M1 in parallel to form an adjustable resistor structure, and the control end Vpulse of the adjustable resistor structure is connected with the peak pulse generating circuit 100; the capacitor C1 crosses the input and output terminals of the fully differential operational amplifier OPAMP, and forms a low pass filter circuit 200 together with the resistor R1, the resistor R2, and the transistor M1; the dc offset feedback circuit 400 includes a transistor M2, and the transistor M2 converts the analog voltage output by the fully differential operational amplifier OPAMP into a current, which is fed into the main rf circuit.
The working principle is as follows: the low-pass filter circuit 200 composed of the resistor R1, the resistor R2, the capacitor C1 and the transistor M1 can extract a direct current signal in a main circuit of the radio frequency signal; when the dc component in the rf main path signal is offset, the offset value is amplified by the fully differential operational amplifier OPAMP, and the error is fed back to the rf main path in an opposite form through the transistor M2, so as to cancel the dc offset of the rf main path until the dc signal extracted by the low pass filter circuit 200 is balanced.
Compared with the traditional architecture, in the invention, the capacitor C1 in the low-pass filter circuit 200 is spanned across the input and output ends of the fully differential operational amplifier OPAMP, and assuming that the gain of the fully differential operational amplifier OPAMP is a (usually more than 100) and the capacitance value of the capacitor C1 is C, the effective capacitance value equivalent to the input end of the fully differential operational amplifier OPAMP is C (1 + a) according to the miller theorem, so that the capacitor C1 on the chip can only use the capacitance value of pF level, thereby realizing the equivalent filtering effect under the condition that a larger capacitor (about hundred times) is originally needed, and greatly reducing the implementation cost.
Fig. 6 is a frequency response curve relationship of the dc offset cancellation circuit provided by the present invention. It can be seen that under the action of the dc offset cancellation circuit provided by the present invention, the low cut-off frequency of the system can be switched between 15kHz and 30 MHz.
Fig. 7 is a time domain response waveform of a system of a conventional dc offset cancellation circuit with a low cutoff frequency of 15 kHz. As can be seen from fig. 7, at 400us, the input terminal suddenly changes, and at this time, due to the large time constant, the system can make the P-terminal output and the N-terminal output coincide after several tens of microseconds (at this time, DC balance is achieved).
Fig. 8 is a time domain response waveform for a system utilizing the switchable bandwidth dc offset cancellation circuit of the present invention. Likewise, the change will be entered at 400 us. When the change occurs, the feedforward pulse is generated, so that the switch in the variable bandwidth DC offset cancellation circuit is switched to switch the bandwidth of the DC offset cancellation circuit to the high-off state (the black solid line in fig. 6), and at this time, although there is a faster response speed (the DC balance can be realized faster by the P-side output and the N-side output), there are many low-frequency signals to be suppressed, and the convergence accuracy is not high. Thus, after full balancing, the feed forward pulse will reset causing the bandwidth of the dc offset cancellation circuit to switch back to the low-off state (dashed line in fig. 6).
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (5)
1. A DC offset cancellation circuit with switchable bandwidth is characterized by comprising a peak pulse generation circuit, a low pass filter circuit, an operational amplifier and a DC offset feedback circuit, wherein,
the peak pulse generating circuit is used for detecting the signal amplitude at a node in the external radio frequency main circuit and outputting a pulse signal when the signal amplitude changes; the amplitude of the pulse signal is amplified to be 0-VDD pulse signal, and the width of the 0-VDD pulse signal is output to the feedforward switch unit after being extended; the peak pulse generating circuit comprises a blocking capacitor, a multi-stage amplifier and an even number of first inverters, one end of the blocking capacitor is connected with a node in the external radio frequency main circuit, and the other end of the blocking capacitor is connected with the feedforward switch unit sequentially through amplifiers and inverters which are connected in series; each stage of amplifier comprises a second phase inverter and a load resistor, wherein one end of the load resistor is respectively connected with a grid electrode of an NMOS (N-channel metal oxide semiconductor) tube in the second phase inverter and a grid electrode of a PMOS (P-channel metal oxide semiconductor) tube, and the other end of the load resistor is respectively connected with a drain electrode of the NMOS tube in the second phase inverter and a drain electrode of the PMOS tube;
the low-pass filter circuit comprises an extraction unit and a feedforward switch unit, wherein the extraction unit is used for extracting a direct current signal in a radio frequency signal output by an output end of a radio frequency amplifier in an external radio frequency main circuit, and the feedforward switch unit is used for switching the bandwidth of the low-pass filter circuit from a low cut-off state to a high cut-off state according to the pulse signal, transmitting the direct current signal to the operational amplifier for amplification and then outputting the direct current signal;
the dc offset feedback circuit is configured to feed back the amplified dc signal to an input end of a radio frequency amplifier in the main external radio frequency circuit in an inverted form, so as to offset a dc offset of the main external radio frequency circuit until the dc signal extracted by the low-pass filter circuit is balanced.
2. The dc offset cancellation circuit with switchable bandwidth according to claim 1, wherein the peak pulse generating circuit is connected to a node near an input terminal of the main external rf frequency circuit, and the dc offset feedback circuit is connected to input terminals of other rf amplifiers except the first stage rf amplifier in the main external rf frequency circuit.
3. The dc offset cancellation circuit with switchable bandwidth according to claim 1 or 2, wherein the feed-forward switch unit includes a transistor M1, the extraction unit includes a resistor R1, a resistor R2, and a capacitor C1, one end of the resistor R1 is connected to an output terminal of a rf amplifier in the main external rf circuit, the other end of the resistor R1 is connected to one end of the resistor R2 and a drain of the transistor M1, the other end of the resistor R2 is connected to a source of the transistor M1, one end of the capacitor C1 and an input terminal of the operational amplifier, a gate of the transistor M1 is connected to the output terminal of the peak pulse generation circuit, and the other end of the capacitor C1 is connected to the output terminal of the operational amplifier.
4. The bandwidth-switchable dc offset cancellation circuit of claim 3, wherein the resistor R1 is a kilo-ohm resistor.
5. The bandwidth switchable dc offset cancellation circuit of claim 3, wherein the dc offset feedback circuit comprises a transistor M2, a gate of the transistor M2 is connected to the output terminal of the operational amplifier, a source of the transistor M2 is grounded, and a drain of the transistor M2 is connected to the input terminal of an rf amplifier in the main external rf circuit.
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| JP4230762B2 (en) * | 2002-12-20 | 2009-02-25 | 株式会社ルネサステクノロジ | Direct conversion receiver |
| US8195096B2 (en) * | 2006-07-13 | 2012-06-05 | Mediatek Inc. | Apparatus and method for enhancing DC offset correction speed of a radio device |
| CN101197581B (en) * | 2006-12-04 | 2011-01-19 | 北京六合万通微电子技术股份有限公司 | Method, device and system for eliminating DC disadjustment in wireless receiving system |
| CN101867350B (en) * | 2009-04-17 | 2013-08-21 | 杭州中科微电子有限公司 | Zero-intermediate-frequency/low-intermediate-frequency configurable variable gain amplifier |
| US8222944B2 (en) * | 2009-11-20 | 2012-07-17 | Electronics And Telecommunications Research Institute | DC offset cancellation circuit |
| CN102130867A (en) * | 2010-12-29 | 2011-07-20 | 电子科技大学 | DC offset cancellation circuit |
| CN102571227B (en) * | 2011-11-10 | 2014-04-16 | 嘉兴联星微电子有限公司 | Amplitude detection circuit with direct current offset elimination function |
| CN104993876A (en) * | 2015-07-17 | 2015-10-21 | 天津大学 | High-speed CMOS monolithically integrated optical receiver with full bandwidth single-ended-to-differential |
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| CN102790596A (en) * | 2011-05-20 | 2012-11-21 | 杭州中科微电子有限公司 | Automatic gain control amplifier for canceling direct current offset |
| CN103731123A (en) * | 2013-12-24 | 2014-04-16 | 华中科技大学 | Ultra-wide-band pulse signal generation device based on memristor |
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