CN113937996B - Test determination method for minimum dead time of IGBT - Google Patents
Test determination method for minimum dead time of IGBT Download PDFInfo
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- CN113937996B CN113937996B CN202111207972.4A CN202111207972A CN113937996B CN 113937996 B CN113937996 B CN 113937996B CN 202111207972 A CN202111207972 A CN 202111207972A CN 113937996 B CN113937996 B CN 113937996B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
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- H02M1/38—Means for preventing simultaneous conduction of switches
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Abstract
The invention provides a test determination method of IGBT minimum dead time, comprising the following steps: under no-load condition, applying control signals to upper IGBT and lower IGBT, gradually reducing dead time of the two control signals until through current appears, wherein the dead time of the two control signals is the minimum dead time T under no-load Dead zone-no load The method comprises the steps of carrying out a first treatment on the surface of the Under the operating condition of the belt running, according to the required load, control signals are applied to an upper IGBT T1 and a lower IGBT T2 of a tested unit, the dead time is gradually reduced until abnormal through current exists in the current IT1 of the upper IGBT T1 and the current IT2 of the lower IGBT T2, and the dead time of the two control signals at the moment is recorded as T Dead zone-on-load The method comprises the steps of carrying out a first treatment on the surface of the Considering the safety margin, calculating the actual use dead time: t (T) Dead zone ＝A*Max(T Dead zone-no load ，T Dead zone-on-load ) The method comprises the steps of carrying out a first treatment on the surface of the The minimum dead time is tested by using a direct test method, and the most reasonable dead time is set so as to solve the problems in the background technology.
Description
Technical Field
The invention relates to the technical field of IGBT control, in particular to a test determination method of minimum dead time of an IGBT.
Background
IGBTs are increasingly used as current converter devices commonly used in the power electronics industry. However, since the IGBT is not an ideal switching device, the on time and the off time thereof are not completely identical. Fig. 1 is a schematic diagram of typical dead time, in order to avoid the direct connection of the IGBT legs, it is generally necessary to add a limitation of "dead time" in the control strategy, that is, one IGBT is turned off first, and after the "dead time", another IGBT is turned on. Thus, the through phenomenon caused by inconsistent on time and off time can be avoided.
Although dead time may avoid bridge arm shoot-through, it may have adverse effects. In general, the polarity of the voltage output by the bridge arm will not be controlled during the dead time, but will depend on the current direction. This may become unstable for some applications.
In order to reasonably set dead time, the method adopted in the industry at present mainly adopts a calculation mode, and a calculation formula is as follows:
t DT ＝[(t d(off),max +t f,max -t d(on),min )+(t PHL,max -t PLH,min )]*S
wherein t is d(off),max +t f,max -t d(on),min Is data related to a power device, t PHL,max -t PLH,min Is a parameter related to the driver, S is a safety factor and generally takes a value of 1.2-1.5.
However, the current dead zone calculation method does not consider the influence of parasitic turn-on, and meanwhile, because a large error exists when substituting the correlation value, the dead zone time is possibly set to be too small or too large, not an optimal value, and no special test means is used for verification. To improve the performance of the system, it is desirable to set the most reasonable dead time in a straightforward manner and verify this.
Disclosure of Invention
In order to overcome the defects in the background technology, the invention provides a test determination method for the minimum dead time of an IGBT, which tests the minimum dead time by using a direct test method, and further sets the most reasonable dead time so as to solve the problems in the background technology.
In order to achieve the above purpose, the invention is realized by adopting the following technical scheme:
a test determination method of IGBT minimum dead time comprises the following steps:
step 1: building an idle load test loop according to an actual application mode;
step 2: the charging cabinet is used for charging the tested unit until the voltage required by the test is reached, control signals are applied to the upper IGBT and the lower IGBT of the same bridge arm under the no-load condition, the dead time of the two control signals is gradually reduced, the currents of the upper IGBT and the lower IGBT are monitored until the direct current appears, and the dead time of the two control signals when the direct current appears is the minimum dead time T under no-load condition Dead zone-no load ；
Step 3: according to the actual application mode, setting up a load test loop;
step 4: under the operating condition of the belt running, the charging cabinet is utilized to charge the tested unit and the accompanying unit until the required voltage for testing is reached, control signals are applied to the upper IGBT T1 and the lower IGBT T2 of the tested unit and the upper IGBT T3 and the lower IGBT T4 of the accompanying unit according to the required load, the dead time is gradually reduced until the through current exists in the current IT1 of the upper IGBT T1 and the current IT2 of the lower IGBT T2 of the tested unit, and the dead time of the two control signals at the moment is recorded as T Dead zone-on-load ；
Step 5: considering the safety margin, calculating the actual use dead time: t (T) Dead zone ＝A*Max(T Dead zone-no load ，T Dead zone-on-load ) A is a safety margin coefficient;
step 6: by using the test device, test verification and confirmation are performed according to the dead time which is actually set.
Further, the no-load test loop, namely the tested unit, comprises an upper IGBT T1, a lower IGBT T2, a capacitor C1 and a discharge resistor R1, wherein the upper IGBT T1 is connected with the lower IGBT T2 in series and then connected with the capacitor C1 in parallel, and the discharge resistor R1 is connected with two ends of the capacitor C1 in parallel.
Further, the on-load test loop comprises a tested unit and a accompany unit;
the tested unit comprises an upper IGBT T1, a lower IGBT T2, a capacitor C1 and a discharge resistor R1, wherein the upper IGBT T1 is connected with the lower IGBT T2 in series and then connected with the capacitor C1 in parallel, and the discharge resistor R1 is connected with two ends of the capacitor C1 in parallel;
the test accompanying unit comprises an upper IGBT T3, a lower IGBT T4, a capacitor C2 and a discharge resistor R2, wherein the upper IGBT T3 is connected with the lower IGBT T4 in series and then connected with the capacitor C2 in parallel, and the discharge resistor R2 is connected with two ends of the capacitor C2 in parallel;
one end of the load inductor L is connected to the middle point of the series connection of the upper IGBT T1 and the lower IGBT T2 of the tested unit, and the other end of the load inductor L is connected to the middle point of the series connection of the upper IGBT T3 and the lower IGBT T4 of the accompanying test unit.
Compared with the prior art, the invention has the beneficial effects that:
the test determination method of the minimum dead time of the IGBT, provided by the invention, utilizes a direct test method to test the minimum dead time, and further sets the most reasonable dead time, so that the technical problems that the dead time is set too small or too large and is not an optimal value because the influence of parasitic turn-on is not considered in the current dead time calculation mode and large errors exist in substituting related values are solved.
Drawings
FIG. 1 is a schematic diagram of typical dead time referred to in the background;
FIG. 2 is a test apparatus for dead time testing according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a test loop under idle test conditions according to an embodiment of the present invention;
fig. 4 is a dead time diagram of the present two IGBT control signals;
FIG. 5 is a typical waveform diagram of a through-flow under idle test conditions in accordance with an embodiment of the present invention;
FIG. 6 is a schematic diagram of a test loop under load test conditions according to an embodiment of the present invention;
fig. 7 is a waveform diagram of a typical case where a through occurs under the load test condition according to the embodiment of the present invention.
Detailed Description
The following detailed description of the embodiments of the invention is provided with reference to the accompanying drawings.
As shown in fig. 2, the embodiment provides an IGBT minimum dead time test device, including a unit under test and a unit under test, where the unit under test includes an upper IGBT T1 and a lower IGBT T2, and further includes a capacitor C1 and a discharge resistor R1, where the upper IGBT T1 and the lower IGBT T2 are connected in series and then connected in parallel with the capacitor C1, and the discharge resistor R1 is connected in parallel with two ends of the capacitor C1; the test accompanying unit comprises an upper IGBT T3, a lower IGBT T4, a capacitor C2 and a discharge resistor R2, wherein the upper IGBT T3 is connected with the lower IGBT T4 in series and then connected with the capacitor C2 in parallel, and the discharge resistor R2 is connected with two ends of the capacitor C2 in parallel; one end of the load inductor L is connected to the middle point of the series connection of the upper IGBT T1 and the lower IGBT T2 of the tested unit, and the other end of the load inductor L is connected to the middle point of the series connection of the upper IGBT T3 and the lower IGBT T4 of the accompanying test unit. The tested unit and the accompanying unit are supplied with power by a transformer T1 and a rectifying circuit ZL. Each IGBT is also connected in parallel with its own diode (D1-D4).
The test device also comprises a control module, wherein the control module is used for providing trigger signals for the IGBT in the tested unit and the accompanying unit and detecting the voltage and the current in the IGBT circuit. The key point of the control module is not a hardware structure (the hardware structure is a control chip such as MCU in the prior art), but an internal control strategy is used for gradually reducing dead time in the method, the dead time can be reduced under no load, and the load control and the dead zone adjustment can be carried out according to specific load requirements during the load.
Step 1: building an idle load test loop according to an actual application mode; as shown in fig. 3, the empty test loop is the unit under test; the test unit is connected into the test loop of fig. 2 (without the accompanying test unit and the load inductance L).
Step 2: charging the tested unit by using a charging cabinet (namely a transformer T1 and a rectifying circuit ZL in the test loop in FIG. 2) until the voltage required by the test is reached, applying control signals to an upper IGBT and a lower IGBT of the same bridge arm under no-load condition, gradually reducing dead time of the two control signals as shown in FIG. 4, monitoring the current of the upper IGBT and the lower IGBT until the through current appears, and obtaining the minimum dead time T of the two control signals under no-load condition when the through current appears as shown in FIG. 5 Dead zone-no load 。
Step 3: according to the actual application mode, setting up a load test loop; as shown in fig. 6, the load test loop includes a test unit and a companion unit and a load inductance L.
Step 4: under the operating condition of the belt running, the charging cabinet is utilized to charge the tested unit and the accompanying unit until the required voltage is reached, control signals are applied to the upper IGBT T1 and the lower IGBT T2 of the tested unit and the upper IGBT T3 and the lower IGBT T4 of the accompanying unit according to the required load, the dead time is gradually reduced, as shown in fig. 7, until abnormal through current exists in the current IT1 of the upper IGBT T1 and the current IT2 of the lower IGBT T2 of the tested unit, and the dead time of the two control signals at the moment is recorded as T Dead zone-on-load 。
Step 5: considering the safety margin, calculating the actual use dead time: t (T) Dead zone ＝A*Max(T Dead zone-no load ，T Dead zone-on-load ) A is a safety margin coefficient;
step 6: test verifies that whether the through current observed in the steps appears is observed under no load and under load, if not, the dead zone is proved to be reasonable and has a certain safety margin; if the through current is found to be still, the safety margin coefficient A is amplified, and the embodiment of the invention takes A=1.2 as a reasonable safety margin, and experiments prove that the through current is not found to be present when A=1.2.
The above examples are implemented on the premise of the technical scheme of the present invention, and detailed implementation manners and specific operation processes are given, but the protection scope of the present invention is not limited to the above examples. The methods used in the above examples are conventional methods unless otherwise specified.
Claims (1)
1. The test determination method of the minimum dead time of the IGBT is characterized by comprising the following steps of:
step 1: building an idle load test loop according to an actual application mode;
step 2: under the no-load condition, a charging cabinet is utilized to charge a tested unit until the voltage required by the test is reached, control signals are applied to an upper IGBT and a lower IGBT of the same bridge arm, the dead time of the two control signals is gradually reduced, the currents of the upper IGBT and the lower IGBT are monitored until the direct current appears, and the dead time of the two control signals when the direct current appears is the minimum dead time T under no-load Dead zone-no load ；
Step 3: according to the actual application mode, setting up a load test loop;
step 4: under the operating condition of the belt running, the charging cabinet is utilized to charge the tested unit and the accompanying unit until the required voltage is tested, control signals are applied to the upper IGBT T1 and the lower IGBT T2 of the tested unit and the upper IGBT T3 and the lower IGBT T4 of the accompanying unit according to the required load, the dead time is gradually reduced until abnormal through currents appear in the current IT1 of the upper IGBT T1 and the current IT2 of the lower IGBT T2 of the tested unit, and the dead time of the two control signals at the moment is recorded as T Dead zone-on-load ；
Step 5: considering the safety margin, calculating the actual use dead time: t (T) Dead zone ＝A*Max(T Dead zone-no load ，T Dead zone-on-load ) A is a safety margin coefficient;
step 6: using the test device, performing test verification and confirmation according to the actually set dead time;
the no-load test loop, namely the tested unit, comprises an upper IGBT T1, a lower IGBT T2, a capacitor C1 and a discharge resistor R1, wherein the upper IGBT T1 and the lower IGBT T2 are connected in series and then connected with the capacitor C1 in parallel, and the discharge resistor R1 is connected with two ends of the capacitor C1 in parallel;
the load test loop comprises a tested unit and a test accompanying unit;
the tested unit comprises an upper IGBT T1, a lower IGBT T2, a capacitor C1 and a discharge resistor R1, wherein the upper IGBT T1 is connected with the lower IGBT T2 in series and then connected with the capacitor C1 in parallel, and the discharge resistor R1 is connected with two ends of the capacitor C1 in parallel;
the test accompanying unit comprises an upper IGBT T3, a lower IGBT T4, a capacitor C2 and a discharge resistor R2, wherein the upper IGBT T3 is connected with the lower IGBT T4 in series and then connected with the capacitor C2 in parallel, and the discharge resistor R2 is connected with two ends of the capacitor C2 in parallel;
one end of the load inductor L is connected to the middle point of the series connection of the upper IGBT T1 and the lower IGBT T2 of the tested unit, and the other end of the load inductor L is connected to the middle point of the series connection of the upper IGBT T3 and the lower IGBT T4 of the accompanying test unit.
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Citations (3)
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| EP3109990A2 (en) * | 2015-06-23 | 2016-12-28 | NXP USA, Inc. | Semiconductor devices and methods for dead time optimization |
| CN112964973A (en) * | 2021-02-25 | 2021-06-15 | 荣信汇科电气股份有限公司 | Method for automatically calculating stray inductance of IGBT module loop |
| CN113092897A (en) * | 2021-03-16 | 2021-07-09 | 荣信汇科电气股份有限公司 | Temperature fatigue aging comprehensive test device for MMC flexible direct converter valve power module |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US10468974B2 (en) * | 2017-03-15 | 2019-11-05 | Hong Kong Applied Science and Technology Research Institute Company Limited | Method and apparatus of dead time tuning in an inverter |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3109990A2 (en) * | 2015-06-23 | 2016-12-28 | NXP USA, Inc. | Semiconductor devices and methods for dead time optimization |
| CN112964973A (en) * | 2021-02-25 | 2021-06-15 | 荣信汇科电气股份有限公司 | Method for automatically calculating stray inductance of IGBT module loop |
| CN113092897A (en) * | 2021-03-16 | 2021-07-09 | 荣信汇科电气股份有限公司 | Temperature fatigue aging comprehensive test device for MMC flexible direct converter valve power module |
Non-Patent Citations (1)
| Title |
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| 一种基于空间矢量PWM的死区效应补偿策略研究;张少锋;高艳霞;徐妍萍;;变频器世界(第03期);全文 * |
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Inventor after: Wang Liangyou Inventor after: Zhou Jianhao Inventor after: Liu Haixin Inventor after: Luo Daijun Inventor after: Wang Qi Inventor after: Liao Xiang Inventor after: Cai Xi Inventor after: Yang Nianhao Inventor after: Fu Guangze Inventor after: Tong Bobin Inventor after: Yu Qiong Inventor before: Luo Daijun Inventor before: Wang Qi Inventor before: Liao Xiang Inventor before: Cai Xi Inventor before: Yang Nianhao Inventor before: Tong Bobin Inventor before: Yu Qiong Inventor before: Zhou Jianhao Inventor before: Liu Haixin |
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