CN113937105A

CN113937105A - Memory array including memory cell strings and method for forming memory array

Info

Publication number: CN113937105A
Application number: CN202110782933.0A
Authority: CN
Inventors: D·比林斯利; J·D·格林利; J·D·霍普金斯; Y·J·胡
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2020-07-14
Filing date: 2021-07-12
Publication date: 2022-01-14
Also published as: US11476274B2; US20220020763A1

Abstract

The present application relates to memory arrays including strings of memory cells and methods for forming memory arrays including strings of memory cells. A memory array including a string of memory cells includes an upper stack located above a lower stack. The lower stack includes vertically alternating lower conductive layers and lower insulating layers. The upper stack includes vertically alternating upper conductive layers and upper insulating layers. An intermediate layer is vertically located between the upper stack and the lower stack. The intermediate layer is at least mainly polysilicon and has a composition different from the compositions of the upper conductive layer and the upper insulating layer directly above the intermediate layer and a composition different from the compositions of the lower conductive layer and the lower insulating layer directly below the intermediate layer. A string of channel material of a memory cell extends through the upper stack, the middle layer, and the lower stack. Other structures and methods are disclosed.

Description

Memory array including memory cell strings and method for forming memory array

Technical Field

Embodiments disclosed herein relate to memory arrays and methods for forming memory arrays.

Background

Memory is one type of integrated circuit system and is used in computer systems to store data. The memory may be fabricated in one or more individual arrays of memory cells. Memory cells can be written to or read from using a digit line (which can also be referred to as a bit line, a data line, or a sense line) and an access line (which can also be referred to as a word line). Sense lines may conductively interconnect memory cells along columns of the array, while access lines may conductively interconnect memory cells along rows of the array. Each memory cell can be uniquely addressed by a combination of a sense line and an access line.

The memory cells may be volatile, semi-volatile, or nonvolatile. The non-volatile memory cells may store data for extended periods of time without power. Non-volatile memory is generally defined as memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, the memory cells are configured to hold or store the memory in at least two different selectable states. In a binary system, the state is considered to be either "0" or "1". In other systems, at least some of the individual memory cells may be configured to store information at more than two levels or states.

A field effect transistor is one type of electronic component that may be used in a memory cell. These transistors include a pair of conductive source/drain regions with a semiconductive channel region therebetween. A conductive gate is adjacent to and separated from the channel region by a thin gate insulator. Application of an appropriate voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. The field effect transistor may also contain additional structures, such as a reversibly programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate.

Flash memory is one type of memory and has many uses in modern computers and devices. For example, modern personal computers may store the BIOS on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to utilize flash memory in solid state drives in place of conventional hard disk drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and provides the ability to remotely upgrade devices to enhance features.

NAND can be the basic architecture for integrated flash memory. A NAND cell unit includes at least one select device coupled in series to a series combination of memory cells (the series combination is commonly referred to as a NAND string). The NAND architecture can be configured as a three-dimensional arrangement including vertically stacked memory cells that individually include reversibly programmable vertical transistors. Control or other circuitry may be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures may also include vertically stacked memory cells that individually include transistors.

The memory arrays may be arranged in memory pages, memory blocks and partial blocks (e.g., sub-blocks), and memory planes, for example, as shown and described in any of U.S. patent application publication nos. 2015/0228651, 2016/0267984, and 2017/0140833. The memory block may at least partially define a longitudinal profile of a single word line in a single word line level of vertically stacked memory cells. The connections to these word lines may occur in a so-called "ladder structure" at the end or edge of the vertically stacked array of memory cells. The stair-step structure comprises a single "step" (also referred to as a "step" or "stair-step") that defines a contact area for a single wordline, on which vertically extending conductive via contacts to provide electrical access to the wordline.

Disclosure of Invention

One embodiment of the present disclosure provides a method for forming a memory array including a string of memory cells, comprising: forming an upper stack over a lower stack, the lower stack comprising vertically alternating lower first layers and lower second layers, the upper stack comprising vertically alternating upper first layers and upper second layers, an intermediate layer located vertically between the upper stack and the lower stack, a lower channel opening extending through the intermediate layer and the lower first layers and the lower second layers, the lower channel opening having a sacrificial material therein in the intermediate layer and in the lower first layers and the lower second layers, the intermediate layer being at least one of (a), (b), and (c), wherein: (a) the method comprises the following steps A thickness greater than a thickness of the upper first layer and a thickness of the upper second layer directly above the intermediate layer and greater than a thickness of the lower first layer and a thickness of the lower second layer directly below the intermediate layer; (b) the method comprises the following steps At least predominantly polycrystalline silicon and having a composition different from the composition of the upper first layer and the upper second layer directly above the intermediate layer and a composition different from the composition of the lower first layer and the lower second layer directly below the intermediate layer; and (c): at least predominantly electrically conductive and having a composition different from the composition of the upper first layer and the upper second layer directly above the intermediate layer and a composition different from the composition of the lower first layer and the lower second layer directly below the intermediate layer; forming an upper channel opening through the upper first layer and the upper second layer to the intermediate layer, a single one of the upper channel openings extending into a single one of the lower channel openings; and removing the sacrificial material from the single lower channel opening through the upper channel opening followed by forming a string of channel material in the upper channel opening and the lower channel opening.

Another embodiment of the present disclosure provides a memory array including a memory cell string, including: an upper stack over the lower stack, the lower stack comprising vertically alternating lower conductive layers and lower insulating layers, the upper stack comprising vertically alternating upper conductive layers and upper insulating layers; an intermediate layer vertically between the upper stack and the lower stack, the intermediate layer being at least predominantly polysilicon and having a composition different from the composition of the upper conductive layer and the upper insulating layer directly above the intermediate layer and having a composition different from the composition of the lower conductive layer and the lower insulating layer directly below the intermediate layer; and a string of channel material of memory cells extending through the upper stack, the middle layer, and the lower stack.

Yet another embodiment of the present disclosure provides a memory array including a memory cell string, including: an upper stack over the lower stack, the lower stack comprising vertically alternating lower conductive layers and lower insulating layers, the upper stack comprising vertically alternating upper conductive layers and upper insulating layers; an intermediate layer vertically between the upper and lower stacks, the intermediate layer being at least predominantly electrically conductive and having a composition different from that of the upper electrically conductive layer directly above the intermediate layer and having a composition different from that of the lower electrically conductive layer directly below the intermediate layer; and a string of channel material of memory cells extending through the upper stack, the middle layer, and the lower stack.

Yet another embodiment of the present disclosure provides a memory array including a memory cell string, including: an upper stack over the lower stack, the lower stack comprising vertically alternating lower conductive layers and lower insulating layers, the upper stack comprising vertically alternating upper conductive layers and upper insulating layers; an intermediate layer vertically between the upper stack and the lower stack; and a string of channel material of memory cells extending through the upper stack, the middle layer, and the lower stack; a portion of a single one of the strings of channel material in the upper stack has an average longitudinal axis that is at an angle to an average longitudinal axis of the portion of the single string of channel material in the lower stack.

Yet another embodiment of the present disclosure provides a memory array including a memory cell string, including: an upper stack over the lower stack, the lower stack comprising vertically alternating lower conductive layers and lower insulating layers, the upper stack comprising vertically alternating upper conductive layers and upper insulating layers; an intermediate layer vertically between the upper stack and the lower stack, the intermediate layer being at least one of (a), (b), and (c), wherein: (a) the method comprises the following steps A thickness greater than a thickness of the upper conductive layer and a thickness of the upper insulating layer directly above the intermediate layer and greater than a thickness of the lower conductive layer and a thickness of the lower insulating layer directly below the intermediate layer; (b) the method comprises the following steps At least predominantly polysilicon and having a composition different from the composition of the upper conductive layer and the upper insulating layer directly above the intermediate layer and a composition different from the composition of the lower conductive layer and the lower insulating layer directly below the intermediate layer; and (c): at least predominantly electrically conductive and having a composition different from the composition of the upper electrically conductive layer directly above the intermediate layer and having a composition different from the composition of the lower electrically conductive layer directly below the intermediate layer; and a string of channel material of memory cells extending through the upper stack, the middle layer, and the lower stack; a portion of a single one of the strings of channel material in the upper stack has an average longitudinal axis that is at an angle to an average longitudinal axis of the portion of the single string of channel material in the lower stack.

Drawings

FIG. 1 is a schematic cross-sectional view of a portion of a substrate in process according to an embodiment of the invention, and taken along line 1-1 in FIG. 2.

Fig. 2 is a schematic cross-sectional view taken along line 2-2 in fig. 1.

Fig. 3 is an enlarged view of a portion of fig. 1 and 2.

Fig. 4-20 are schematic sequential cross-sectional, expanded, enlarged, and/or partial views of the construction of fig. 1-3, or portions thereof, in a process according to some embodiments of the invention.

FIG. 21 illustrates an alternative exemplary method and/or structure embodiment of the present invention.

Detailed Description

Embodiments of the invention encompass methods for forming memory arrays, such as NAND or other memory cells that may have at least some peripheral control circuitry underneath the array (e.g., CMOS-under-array). Embodiments of the present invention encompass so-called "back-gate" or "replacement-gate" processes, so-called "front-gate" processes, and other processes now existing or developed in the future that are not related to when a transistor gate is formed. Embodiments of the present invention also contemplate memory arrays (e.g., NAND architectures) that are independent of the method of fabrication. A first exemplary method embodiment is described with reference to fig. 1-20, which may be considered a "gate last" or "replacement gate" process and begins with fig. 1-3.

Fig. 1-3 show a construction 10 having an array or array region 12 in which vertically extending strings of transistors and/or memory cells are to be formed. Construction 10 includes a base substrate 11 having any one or more of conductive/conductor/conductive, semi-conductive/semiconductor/semi-conductive or insulating (insulating)/insulator/insulating (i.e., electrical herein) materials. Various materials have been formed vertically above the base substrate 11. The material may be beside, vertically inside or vertically outside the material depicted in fig. 1-3. For example, other portions of the integrated circuit system or all of the finished components may be disposed at some location above, around, or within the base substrate 11. Control and/or other peripheral circuitry for operating components within an array of vertically extending strings of memory cells (e.g., array 12) may also be fabricated, and may or may not be wholly or partially within the array or sub-array. In addition, multiple sub-arrays may also be fabricated and operated independently, in series, or otherwise with respect to each other. In this document, "sub-array" may also be considered an array.

Including a conductor material 17 (e.g., WSi)_xConductively doped polysilicon on top) a conductor layer 16 has been formed over the substrate 11. The conductor layer 16 may include a portion of control circuitry (e.g., peripheral array lower circuitry and/or common source line or plate) for controlling read and write access to transistors and/or memory cells to be formed within the array 12.

A lower stack 18L comprising vertically alternating lower insulating layers 20L and lower conductive layers 22L has been formed over the conductor layer 16. An exemplary thickness of each of the

lower layers

20L and 22L is 22 to 60 nanometers. Only a small number of

lower layers

20L and 22L are shown, it being more likely that the lower stack 18L includes tens, a hundred, or more, etc. of

lower layers

20L and 22L. Other circuitry, which may or may not be part of the peripheral and/or control circuitry, may be between the conductor layer 16 and the lower stack 18L. For example, the plurality of vertically alternating layers of conductive material and insulating material of this circuitry may be below the lowest of the lower conductive layers 22L and/or above the highest of the lower conductive layers 22L. For example, one or more select gate layers (not shown) or dummy layers (not shown) may be between the conductor layer 16 and the lowermost conductive layer 22L, and one or more select gate layers (not shown) or dummy layers (not shown) may be above the uppermost layer in the lower conductive layer 22L. Alternatively or additionally, at least one of the depicted lowermost conductive layers 22L may be a select gate layer. Regardless, the lower conductive layer 22L (alternatively referred to as the lower first layer) may not include a conductive material, while the lower insulating layer 20L (alternatively referred to as the lower second layer) may not include an insulating material, or be insulating at this point in the process in connection with the exemplary method embodiment described initially herein, which is a "back gate" or "replacement gate". The example lower conductive layer 22L includes a first material 26 (e.g., silicon nitride), which may be wholly or partially sacrificial. The example lower insulating layer 20L includes a second material 24 (e.g., silicon dioxide) that has a different composition than the first material 26 and may be wholly or partially sacrificial.

The intermediate layer 21 is above the lower stack 18L and its features are described further below.

A lower channel opening 25 is formed (e.g., by etching) through the intermediate layer 21, the lower insulating layer 20L, and the lower conductive layer 22L to the conductor layer 16. The lower channel opening 25 may be tapered radially inward (not shown) to move deeper into the lower stack 18L. In some embodiments, the lower channel opening 25 may enter the conductor material 17 of the conductor layer 16 as shown, or may stop on top thereof (not shown). Alternatively, as an example, the lower channel opening 25 may stop on top of or inside the lowermost lower insulating layer 20L. The reason for extending the lower channel opening 25 at least into the conductor material 17 of the conductor layer 16 is to provide an anchoring effect of the material within the lower channel opening 25. An etch stop material (not shown) may be in or on top of the conductor material 17 of the conductor layer 16 to facilitate this when it is desired to stop etching the lower channel opening 25 relative to the conductor layer 16. The etch stop material may be sacrificial or non-sacrificial. Regardless, the lower channel opening 25 can be considered to have an average longitudinal axis 75 that is vertical in one embodiment (e.g., averaged if the axis 75 is not perfectly straight).

Horizontally elongated lower trenches 40L have been formed (e.g., by anisotropic etching) into the intermediate layer 21 and the lower stack 18L to form laterally spaced memory block regions 58. By way of example only and for the sake of brevity, the lower channel openings 25 are shown as being arranged in groups or columns of staggered rows of four and five lower channel openings 25 per row, and are arranged in laterally spaced memory block areas 58 which will include the laterally spaced memory blocks 58 of the finished circuitry construction. In this document, "block" generally includes "sub-blocks. The lower trench 40L will typically be wider (e.g., 10 to 20 times wider, although this wider extent is not shown for simplicity) than the lower channel opening 25. Memory block area 58 and resulting memory blocks 58 (not shown) may be considered longitudinally elongated and oriented, for example, along direction 55. Any alternative existing or future developed arrangements and configurations may be used.

Sacrificial material 59 has been formed in the lower channel openings 25 in the intermediate layer 21, the lower first layer 22L, and the lower second layer 20L. In one embodiment and as shown, sacrificial material 59 has been formed in lower trench 40L. In one embodiment, sacrificial material 59 in lower channel opening 25 comprises radially outer silicon dioxide 70, radially inner silicon dioxide 72, and aluminum oxide 71 between radially outer silicon dioxide 70 and radially inner silicon dioxide 72. The lower trench 40L may include corresponding aluminum oxide 71 and

silicon dioxide

70, 72. In other figures,

materials

70, 71 and 72 are only so designated in fig. 3 for the sake of brevity. In one embodiment, the radially outer silica 70 and the radially inner silica 72 have different compositions from one another, and in one such embodiment, the different compositions are characterized by a concentration of at least one of boron and phosphorus. As just one specific example, the radially inner silicon dioxide 72 is BPSG, while the radially outer silicon dioxide 70 is undoped silicon dioxide.

Referring to fig. 4, an upper stack 18U comprising vertically alternating upper insulating layers 20U (alternatively referred to as upper second layers) and upper conductive layers 22U (alternatively referred to as upper first layers) has been formed over the intermediate layer 21 and the lower stack 18L. The upper insulating layer 20U and the upper conductive layer 22U may have any of the properties described above with respect to the lower insulating layer 20L and the lower conductive layer 22L. The exemplary upper conductive layer 22U includes a first material 26 (e.g., silicon nitride), which may be wholly or partially sacrificial. The exemplary upper insulating layer 20U is shown as comprising the second material 24 and the upper conductive layer 22U is shown as comprising the first material 26, but other compositions may of course be used, and need not have the same composition as in the lower stack 18L.

In some embodiments, the intermediate layer 21 is at least one of (a), (b), and (c), wherein:

(a) the method comprises the following steps A thickness greater than the thickness of the upper first layer 22U and the thickness of the upper second layer 20U directly above the intermediate layer 21 and greater than the thickness of the lower first layer 22L and the thickness of the lower second layer 20L directly below the intermediate layer 21 (e.g., at least two times, three times as shown in the figures);

(b) the method comprises the following steps Is at least mainly polycrystalline silicon and has a composition different from the compositions of the upper first layer 22U and the upper second layer 20U immediately above the intermediate layer 21 and a composition different from the compositions of the lower first layer 22L and the lower second layer 20L immediately below the intermediate layer 21; and

(c) the method comprises the following steps Is at least mainly electrically conductive and has a composition different from the compositions of the upper first layer 22U and the upper second layer 20U directly above the intermediate layer 21 and a composition different from the compositions of the lower first layer 22L and the lower second layer 20L directly below the intermediate layer 21.

In one embodiment, the intermediate layer 21 is (a); in one embodiment is (b); in one embodiment is (c); in one embodiment at least two of (a), (b), and (c); and in one embodiment are (a), (b), and (c).

If (b) or comprises (b), then in one embodiment the intermediate layer 21 is at least predominantly undoped polysilicon (i.e. "undoped" in the context of polysilicon is an impurity of increased conductivity by reference and means from 0 atoms/cm³To 1X10¹²Atom/cm³). If (b) or includes (b), then in one embodiment the intermediate layer 21 is at least predominantly doped polysilicon (i.e., "doped" in the context of polysilicon is an impurity of increased conductivity by reference and means from 1x10¹²Atom/cm³To 1x10³⁰Atom/cm³) -in one such embodiment, at least predominantly semiconductive-doped polysilicon (e.g., from 1x 10)¹⁴Atom/cm³To less than 1x10²¹Atom/cm³) And in another such embodiment is at least predominantly conductively-doped polysilicon (e.g., from 1x 10)²¹Atom/cm³To 1x10³⁰Atom/cm³)。

If (c) is included in one embodiment, the intermediate layer 21 is at least predominantly at least one of an elemental metal, a metal alloy, a metal nitride, and a metal silicide. In another embodiment, if (c) or (c) is included, the intermediate layer 21 is at least predominantly conductively doped semiconductive material.

Referring to fig. 5-7, upper channel openings 39 have been formed (e.g., by etching) through the upper first layer 22U and the upper second layer 20U to the intermediate layer 21, with the single upper channel opening 39 extending to the sacrificial material 59 in the single lower channel opening 25. In one embodiment and as shown, and as best understood with reference to fig. 6 and 7, the single upper channel opening 39 is formed to have an average longitudinal axis 85 that is at an angle a to the average longitudinal axis 75 of the respective single lower channel opening 25 to which the upper channel opening is to extend. In one embodiment, this angle is an angle a of at least 0.5 ° from the average longitudinal axis 75, in one such embodiment is an angle a of no greater than 5.0 ° from the average longitudinal axis 75, and in one such embodiment is an angle a of at least 1.0 ° to no greater than 5.0 ° from the average longitudinal axis 75 (4 ° shown in the figures). Regardless, if the upper trench opening 39 is formed by etching, some etching (not shown) may occur in the lower sacrificial material 59, the intermediate material, and/or the uppermost layer.

Referring to fig. 8 and 9, the sacrificial material 59 (i.e., at least some) has been removed (e.g., by etching) from the single lower channel opening 25 through the upper channel opening 39. For example, where

materials

70, 71, and 72 are present, some of 70 and/or 71 may remain to facilitate formation of transistor material (described below).

Transistor channel material can be formed in a single channel opening along the insulating layer and the conductive layer, thus comprising a single string of channel material, the transistor channel material being directly electrically coupled with the conductive material in the conductor layer. The individual memory cells of the example memory array formed may include a gate region (e.g., a control-gate region) and a memory structure laterally between the gate region and the channel material. In one such embodiment, a memory structure is formed to include a charge blocking region, a storage material (e.g., a charge storage material), and an insulating charge channel material. The storage material (e.g., floating gate material such as doped or undoped silicon or charge trapping material such as silicon nitride, metal dots, etc.) of an individual memory cell is vertically along an individual one of the charge blocking regions. An insulating charge channel material (e.g., a band gap engineered structure having a nitrogen-containing material [ e.g., silicon nitride ] sandwiched between two insulator oxides [ e.g., silicon dioxide ]) is located laterally between the channel material and the memory material.

Fig. 10 to 13 show an embodiment in which the charge blocking material 30, the memory material 32 and the charge channel material 34 have been formed vertically along the insulating layer 20 and the conductive layer 22 in a single upper channel opening 39 and lower channel opening 25.

Transistor materials

30, 32, and 34 (e.g., memory cell materials) may be formed by, for example, depositing respective thin layers of the transistor material over upper stack 18U and within

single openings

39 and 25, followed by planarizing such thin layers at least back to the top surface of upper stack 18U.

Channel material 36 is also formed vertically in channel opening 39/25 along insulating layer 20U/20L and conductive layer 22U/22L, thus including a single effective string of channel material 53 in channel opening 39/25. In one embodiment, the string of channel material 53 has memory cell material (e.g., 30, 32, and 34) along it, with the second layer of material (e.g., 24) horizontally located between immediately adjacent strings of channel material 53. Due to the proportions,

materials

30, 32, 34 and 36 are shown collectively in fig. 10 and 11 and are designated only as material 37. Example channel material 36 includes a suitably doped crystalline semiconductor material, such as one or more of silicon, germanium, and so-called group III/V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). An exemplary thickness for each of

materials

30, 32, 34, and 36 is 25 to 100 angstroms. A punch etch may be performed to remove

materials

30, 32, and 34 from the bottom (not shown) of the lower channel opening 25 to expose the conductor layer 16 such that the channel material 36 is directly against the conductor material 17 of the conductor layer 16. This stamping etch may occur separately for each of

materials

30, 32, and 34 (as shown), or may occur with respect to only some of the materials (not shown). Alternatively and by way of example only, no stamping etch may be performed, and the channel material 36 may be directly electrically coupled to the conductor material 17 of the conductor layer 16 only by a separate conductive interconnect (not shown). The channel opening 39/25 is shown as including a radially central solid dielectric material 38 (e.g., a spin-on dielectric, silicon dioxide, and/or silicon nitride). Alternatively, and by way of example only, the radially central portion within the channel opening 39/25 may contain void space (not shown) and/or be devoid of solid material (not shown).

Referring to fig. 14 and 15, a horizontally elongated upper trench 40U has been formed to a lower trench 40L from which sacrificial material 59 (not shown) has subsequently been removed (e.g., by selective etching).

Referring to fig. 16-20, material 26 (not shown) of conductive layer 22U/22L has been removed, such as by isotropically etching away through trench 40U/40L, theoretically selectively relative to other exposed material (e.g., using liquid or vapor H)₃PO₄As the main etchant, where material 26 is silicon nitride and the other material includes one or more oxides or polysilicon). Material 26 (not shown) in conductive layer 22U/22L in the exemplary embodiment is sacrificial and has been replaced with conductive material 48, which has subsequently been removed from trenches 40U/40L, thus forming a single conductive line 29 (e.g., word line) and a vertically extending string 49 of a single transistor and/or memory cell 56.

A thin insulating liner (e.g., Al) may be formed prior to forming conductive material 48₂O₃And not shown). The approximate locations of transistors and/or memory cells 56 are indicated in parenthesis in fig. 19, and some are indicated in dashed outline in fig. 16-18 and 20, where transistors and/or memory cells 56 are substantially ring-shaped or ring-shaped in the depicted example. Alternatively, transistors and/or memory cells 56 may not completely surround with respect to a single channel opening 39/25 such that each channel opening 39/25 may have two or more vertically extending strings 49 (e.g., multiple transistors and/or memory cells surround a single channel opening in a single conductive layer, where each channel opening in a single conductive layer may have multiple word lines, and not shown).Conductive material 48 may be considered to have a terminal 50 corresponding to a control-gate region 52 of a single transistor and/or memory cell 56 (fig. 19). The control-gate region 52 in the depicted embodiment comprises a single portion of a single conductive line 29.

Materials

30, 32, and 34 may be considered memory structure 65 located laterally between control-gate region 52 and channel material 36. In one embodiment and as shown with respect to an exemplary "gate last" process, conductive material 48 of conductive layer 22U/22L is formed after forming channel opening 39/25 and/or trench 40U/40L. Alternatively, for example, with respect to a "front gate" process, the conductive material of the conductive layer may be formed prior to forming the channel opening 39/25 and/or the trenches 40U/40L (not shown).

A charge blocking region (e.g., charge blocking material 30) is between the memory material 32 and the single control-gate region 52. The charge block may have the following functions in the memory cell: in a program mode, the charge block may prevent charge carriers from being transferred out of the storage material (e.g., floating gate material, charge trapping material, etc.) towards the control gate, while in an erase mode, the charge block may prevent charge carriers from flowing into the storage material from the control gate. Thus, the charge block can be used to block charge migration between the control gate region and the storage material of the individual memory cell. The exemplary charge blocking region as shown includes an insulator material 30. By way of further example, the charge blocking region may comprise a laterally (e.g., radially) outer portion of a memory material (e.g., material 32), wherein such memory material is insulative (e.g., without any different composition of material between the insulative memory material 32 and the conductive material 48). Regardless, as an additional example, the interface of the memory material with the conductive material of the control gate may be sufficient to act as a charge blocking region without any separately composed insulator material 30. Further, the interface of the conductive material 48 with the material 30 (when present) in combination with the insulator material 30 may act together as a charge blocking region and, alternatively or additionally, may act as a laterally outer region of an insulating memory material (e.g., silicon nitride material 32). Exemplary material 30 is one or more of hafnium silicon oxide and silicon dioxide.

An intermediate material 57 has been formed in trenches 40U/40L, thereby being formed laterally between and longitudinally along immediately laterally adjacent memory blocks 58. Intermediate material 57 may provide lateral electrical isolation (insulation) between immediately laterally adjacent memory blocks. This may include one or more of insulating, semi-conductive, and conductive materials, and in any event, may facilitate shorting of conductive layers 22 to one another in the finished circuitry construction. An exemplary insulating material is SiO₂、Si₃N₄、Al₂O₃And undoped polysilicon. The intermediate material 57 may contain array through vias (not shown).

In the embodiments illustrated and described with reference to the above embodiments, any other attributes or aspects illustrated and/or described herein with respect to other embodiments may be used.

FIG. 21 illustrates an example alternate embodiment configuration 10a as compared to configuration 10 of FIG. 17. The same reference numerals as in the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix "a" or with different reference numerals. Intermediate layer 21a in construction 10a has the same thickness as layers 22U/22L and 20U/20L directly above and below it. This may result, for example, from modifying the construction 10 in fig. 2 to have an intermediate layer 21a and otherwise continuing the methods described herein. Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

Although not so limited, some aspects of the present invention are motivated by overcoming problems associated with forming the charge blocking material 30 in the form of an oxide. In some approaches, the remaining presence of the radially outer silicon dioxide 70 of the sacrificial material 59 in the lower channel opening 25L facilitates the formation of the charge blocking oxide material 30. The sacrificial material 59 that etches the upper channel opening 39 into the lower channel opening 25L has previously had a tendency to etch away much of the radially outer silicon dioxide 70, creating a gap in which the charge blocking oxide material 30 will not form using such methods. Forming an

intermediate layer

21 or 21a as described herein may reduce or eliminate such problems.

Alternate embodiment configurations may result from the method embodiments described above or other methods. Regardless, embodiments of the present invention encompass memory arrays that are independent of the method of fabrication. However, such memory arrays may have any of the attributes as described herein in method embodiments. Likewise, the above-described method embodiments may be combined, formed and/or have any of the attributes described with respect to the apparatus embodiments.

In one embodiment, a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56) includes an upper stack (e.g., 18U) located above a lower stack (e.g., 18L). The lower stack includes vertically alternating lower conductive layers (e.g., 22L) and lower insulating layers (e.g., 20L). The upper stack includes vertically alternating upper conductive layers (e.g., 22U) and upper insulating layers (e.g., 20U). An intermediate layer (e.g., 21 or 21a) is vertically positioned between the upper and lower stacks. The intermediate layer is at least mainly polysilicon and has a composition different from the compositions of the upper conductive layer and the upper insulating layer immediately above the intermediate layer and a composition different from the compositions of the lower conductive layer and the lower insulating layer immediately below the intermediate layer. A string (e.g., 53) of channel material of a memory cell (e.g., 56) extends through the upper stack, the middle layer, and the lower stack. Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

In one embodiment, a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56) includes an upper stack (e.g., 18U) located above a lower stack (e.g., 18L). The lower stack includes vertically alternating lower conductive layers (e.g., 22L) and lower insulating layers (e.g., 20L). The upper stack includes vertically alternating upper conductive layers (e.g., 22U) and upper insulating layers (e.g., 20U). An intermediate layer (e.g., 21 or 21a) is vertically positioned between the upper and lower stacks. The intermediate layer is at least predominantly electrically conductive and has a composition different from that of the upper electrically conductive layer directly above the intermediate layer and a composition different from that of the lower electrically conductive layer directly below the intermediate layer. A string (e.g., 53) of channel material of a memory cell (e.g., 56) extends through the upper stack, the middle layer, and the lower stack. In one embodiment, the intermediate layer is at least predominantly at least one of an elemental metal, a metal alloy, a metal nitride, and a metal silicide. In another embodiment the intermediate layer is at least predominantly conductively doped semiconductive material.

In one embodiment, the conductive material of the intermediate layer is directly against the conductive material of the upper conductive layer directly above the intermediate layer and directly against the lower conductor layer directly below the intermediate layer. In one such embodiment, each of the conductive material, the electrically conductive material, and the conductor material is a metallic material. And in one such subsequent embodiment, the metallic material is at least predominantly at least one of an elemental metal, a metal alloy, a metal nitride, and a metal silicide.

Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

In one embodiment, a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56) includes an upper stack (e.g., 18U) located above a lower stack (e.g., 18L). The lower stack includes vertically alternating lower conductive layers (e.g., 22L) and lower insulating layers (e.g., 20L). The upper stack includes vertically alternating upper conductive layers (e.g., 22U) and upper insulating layers (e.g., 20U). An intermediate layer [ e.g., 21 or 21a, whether having any of the properties (a), (b), and/or (c) ], is located vertically between the upper and lower stacks. A string (e.g., 53) of channel material of a memory cell (e.g., 56) extends through the upper stack, the middle layer, and the lower stack. The portion of the individual channel material strings in the channel material string in the upper stack has an average longitudinal axis (e.g., 85) that is at an angle to the average longitudinal axis (e.g., 75) of the portion of the individual channel material string in the lower stack. Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

The above-described processes or configurations may be considered relative to an array of components formed as or in or as part of two stacks or two laminations of such components as described above (although the two stacks/laminations may each have multiple layers). Control and/or other peripheral circuitry for operating or accessing such components within the array may also be formed anywhere as part of the finished construction, and in some embodiments may be under the array (e.g., under a CMOS array). In any event, one or more additional such stacks/laminations can be disposed or fabricated above and/or below that shown in the figures or described above. Further, the component arrays may be the same or different from each other in different stacks/laminae, and the different stacks/laminae may have the same thickness or different thicknesses from each other. Intermediate structures may be disposed between immediately vertically adjacent stacks/layers (e.g., additional circuitry and/or dielectric layers). Also, the different stacks/laminations may be electrically coupled to each other. Multiple stacks/laminae may be fabricated separately and sequentially (e.g., on top of each other), or two or more stacks/laminae may be fabricated substantially simultaneously.

The components and structures discussed above may be used in integrated circuits/circuitry and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic system may be any of a variety of systems such as, for example, a camera, a wireless device, a display, a chipset, a set-top box, a gaming console, a lighting device, a vehicle, a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, and so forth.

In this document, "vertical," "upper," "lower," "top," "bottom," "above," "below," "under," "below," "upward," and "downward" generally refer to a vertical direction unless otherwise indicated. "horizontal" refers to a general direction along the main substrate surface (i.e., within 10 degrees) and may be relative to which substrate is processed during fabrication, and vertical is a direction generally orthogonal to horizontal. Reference to "substantially horizontal" is a direction along (i.e., without an angle to) the main substrate surface, and may be relative to which substrate is processed during fabrication. Furthermore, "vertical" and "horizontal" as used herein are generally directions that are perpendicular with respect to each other and independent of the orientation of the substrate in three-dimensional space. Additionally, "vertically extending" and "vertically extending" refer to directions that make an angle of at least 45 ° with true horizontal. Furthermore, "vertically extending", "horizontally extending" and the like with respect to the field effect transistor refer to the orientation of the channel length of the transistor along which current flows between the source/drain regions in operation. For a bipolar junction transistor, "vertically extending," "horizontally extending," etc., are orientations with reference to the base length along which current flows between the emitter and collector in operation. In some embodiments, any component, feature, and/or region that extends vertically or within 10 ° of vertical.

Further, "directly above …," "directly below …," and "directly below …" require that there be at least some lateral overlap (i.e., horizontally) of the two described regions/materials/components with respect to each other. Also, not using "directly" before "over" merely requires that some portion of the area/material/component that is over another area/material/component be vertically outside of the other area/material/component (i.e., independent of whether there is any lateral overlap of the two areas/materials/components). Similarly, not using "directly" before "under" and "beneath" merely requires that some portion of the area/material/component under/beneath another area/material/component be vertically inboard of the other area/material/component (i.e., independent of whether there is any lateral overlap of the two areas/materials/components).

Any of the materials, regions, and structures described herein can be homogeneous or heterogeneous, and can be continuous or discontinuous, whether on any material so covered. When one or more exemplary compositions are provided for any material, the material can include, consist essentially of, or consist of one or more such compositions. Furthermore, unless otherwise indicated, each material may be formed using any suitable existing or future-developed technique, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation.

In addition, "thickness" itself (without a directional adjective preceding it) is defined as the average straight-line distance perpendicularly across a given material or region from the nearest surface of the immediate adjacent material or immediate adjacent region of different composition. In addition, the various materials or regions described herein can have a substantially constant thickness or a variable thickness. If the thickness is variable, the thickness refers to an average thickness unless otherwise indicated, and since the thickness is variable, this material or region will have a certain minimum thickness and a certain maximum thickness. As used herein, "different compositions" only requires that those portions of two described materials or regions that may be directly against each other be chemically and/or physically different, for example, provided that such materials or regions are not homogeneous. "different composition" only requires that those portions of two such materials or regions that are closest to each other be chemically and/or physically different if such materials or regions are not directly against each other, provided that such materials or regions are not homogeneous. In this document, a material, region or structure is "directly against" another material, region or structure when the materials, regions or structures are in at least some physical contact with respect to each other. In contrast, "above," "overlying," "adjacent," "along," and "against" are not preceded by "directly" and encompass "directly against" and configurations in which intervening materials, regions, or structures result in the materials, regions, or structures not being in physical contact with one another.

In this context, region-material-components are "electrically coupled" with respect to one another if, in normal operation, an electrical current can flow continuously from one region-material-component to another region-material-component and, when a subatomic positive and/or negative charge is sufficiently generated, from one region-material-component to another region-material-component predominantly by the movement of the subatomic positive and/or negative charge. Another electronic component may be between and electrically coupled to the region-material-component. In contrast, when a region-material-component is referred to as being "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-component.

Any use of "rows" and "columns" in this document is for convenience in distinguishing one series or orientation of features from another series or orientation of features, and along which features have been or may be formed. "Row" and "column" are used synonymously with respect to any series of regions, components and/or features that are not related to function. In any case, the rows may be straight and/or curved and/or parallel to each other and/or non-parallel, just like the columns. Further, the rows and columns may intersect each other at 90 ° or at one or more other angles (i.e., other than a right angle).

The composition of any of the conductive/conductor/conductive materials herein may be a metallic material and/or a conductively doped semiconductive/semiconductive material. A "metallic material" is any one or combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

Herein, any use of "selectivity" with respect to etching (tch), etching (etching), removing (removing), depositing, forming and/or forming (formation) is such an action that one said material does so at a rate of at least 2:1 by volume relative to another said material. Further, any use of selectively depositing, selectively growing, or selectively forming is to deposit, grow, or form one material relative to another at a rate of at least 2:1 by volume for at least the first 75 angstroms of deposition, growth, or formation.

The use of "or" herein encompasses either or both unless otherwise indicated.

Conclusion

In some embodiments, a method for forming a memory array including a string of memory cells includes forming an upper stack over a lower stack. The lower stack includes vertically alternating lower first and second layers. The upper stack includes vertically alternating upper first and second layers. An intermediate layer is vertically located between the upper stack and the lower stack. A lower channel opening extends through the intermediate layer and the lower first and second layers. The lower channel opening has a sacrificial material therein in the intermediate layer and the lower first and second layers. The intermediate layer is at least one of (a), (b), and (c), wherein: (a) the method comprises the following steps A thickness greater than a thickness of the upper first layer and a thickness of the upper second layer directly above the intermediate layer and greater than a thickness of the lower first layer and a thickness of the lower second layer directly below the intermediate layer; (b) the method comprises the following steps At least predominantly polycrystalline silicon and having a composition different from the composition of the upper first layer and the upper second layer directly above the intermediate layer and a composition different from the composition of the lower first layer and the lower second layer directly below the intermediate layer; and (c): at least predominantly electrically conductive and having a composition different from the composition of the upper first layer and the upper second layer directly above the intermediate layer and a composition different from the composition of the lower first layer and the lower second layer directly below the intermediate layer. An upper channel opening is formed through the upper first layer and the upper second layer to the intermediate layer. A single one of the upper channel openings extends to the sacrificial material in a single one of the lower channel openings. The sacrificial material is removed from the single lower channel opening through the upper channel opening followed by forming a string of channel material in the upper and lower channel openings.

In some embodiments, a memory array including a string of memory cells includes an upper stack located above a lower stack. The lower stack includes vertically alternating lower conductive layers and lower insulating layers. The upper stack includes vertically alternating upper conductive layers and upper insulating layers. An intermediate layer is vertically located between the upper stack and the lower stack. The intermediate layer is at least mainly polysilicon and has a composition different from the compositions of the upper conductive layer and the upper insulating layer directly above the intermediate layer and a composition different from the compositions of the lower conductive layer and the lower insulating layer directly below the intermediate layer. A string of channel material of a memory cell extends through the upper stack, the middle layer, and the lower stack.

In some embodiments, a memory array including a string of memory cells includes an upper stack located above a lower stack. The lower stack includes vertically alternating lower conductive layers and lower insulating layers. The upper stack includes vertically alternating upper conductive layers and upper insulating layers. An intermediate layer is vertically located between the upper stack and the lower stack. The intermediate layer is at least predominantly electrically conductive and has a composition that is different from the composition of the upper conductive layer directly above the intermediate layer and has a composition that is different from the composition of the lower conductive layer directly below the intermediate layer. A string of channel material of a memory cell extends through the upper stack, the middle layer, and the lower stack.

In some embodiments, a memory array including a string of memory cells includes an upper stack located above a lower stack. The lower stack includes vertically alternating lower conductive layers and lower insulating layers. The upper stack includes vertically alternating upper conductive layers and upper insulating layers. An intermediate layer is vertically located between the upper stack and the lower stack. A string of channel material of a memory cell extends through the upper stack, the middle layer, and the lower stack. The portion of a single one of the strings of channel material in the upper stack has an average longitudinal axis that is at an angle to an average longitudinal axis of the portion of the single string of channel material in the lower stack.

In some embodiments, a memory array including a string of memory cells includes an upper stack located above a lower stack. The lower stack includes vertically alternating lower conductive layers and lower insulating layers. The upper stack includes vertically alternating upper conductive layers and upper insulating layers. An intermediate layer is vertically located between the upper stack and the lower stack. The intermediate layer is at least one of (a), (b), and (c), wherein: (a) the method comprises the following steps A thickness greater than a thickness of the upper conductive layer and a thickness of the upper insulating layer directly above the intermediate layer and greater than a thickness of the lower conductive layer and a thickness of the lower insulating layer directly below the intermediate layer; (b) the method comprises the following steps At least predominantly polysilicon and having a composition different from the composition of the upper conductive layer and the upper insulating layer directly above the intermediate layer and a composition different from the composition of the lower conductive layer and the lower insulating layer directly below the intermediate layer; and (c): at least predominantly electrically conductive and having a composition different from the composition of the upper electrically conductive layer directly above the intermediate layer and having a composition different from the composition of the lower electrically conductive layer directly below the intermediate layer; a string of channel material of a memory cell extends through the upper stack, the middle layer, and the lower stack. The portion of a single one of the strings of channel material in the upper stack has an average longitudinal axis that is at an angle to an average longitudinal axis of the portion of the single string of channel material in the lower stack.

In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are, therefore, to be accorded the full scope literally and appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A method for forming a memory array comprising a string of memory cells, comprising:

forming an upper stack over a lower stack, the lower stack comprising vertically alternating lower first layers and lower second layers, the upper stack comprising vertically alternating upper first layers and upper second layers, an intermediate layer located vertically between the upper stack and the lower stack, a lower channel opening extending through the intermediate layer and the lower first layers and the lower second layers, the lower channel opening having a sacrificial material therein in the intermediate layer and in the lower first layers and the lower second layers, the intermediate layer being at least one of (a), (b), and (c), wherein:

(a) the method comprises the following steps A thickness greater than a thickness of the upper first layer and a thickness of the upper second layer directly above the intermediate layer and greater than a thickness of the lower first layer and a thickness of the lower second layer directly below the intermediate layer;

(b) the method comprises the following steps At least predominantly polycrystalline silicon and having a composition different from the composition of the upper first layer and the upper second layer directly above the intermediate layer and a composition different from the composition of the lower first layer and the lower second layer directly below the intermediate layer; and

(c) the method comprises the following steps At least predominantly electrically conductive and having a composition different from the composition of the upper first layer and the upper second layer directly above the intermediate layer and a composition different from the composition of the lower first layer and the lower second layer directly below the intermediate layer;

forming an upper channel opening through the upper first layer and the upper second layer to the intermediate layer, a single one of the upper channel openings extending into a single one of the lower channel openings; and

the sacrificial material is removed from the single lower channel opening through the upper channel opening followed by forming a string of channel material in the upper and lower channel openings.

2. The method of claim 1, wherein the sacrificial material comprises radially outer silica, radially inner silica, and radial alumina between the radially outer silica and the radially inner silica.

3. The method of claim 2, wherein the radially outer silica and the radially inner silica have different compositions from one another.

4. The method of claim 3, wherein the different composition is characterized by a concentration of at least one of boron and phosphorus.

5. The method of claim 1 which is (a).

6. The method of claim 1, which is (b).

7. The method of claim 1, which is (c).

8. The method of claim 1, which is at least two of (a), (b), and (c).

9. The method of claim 1 which is (a), (b) and (c).

10. The method of claim 1, wherein the single upper channel opening is formed to have an average longitudinal axis that is angled from an average longitudinal axis of the respective single lower channel opening to which the single upper channel opening is to extend.

11. The method of claim 10, wherein the angle is an angle of at least 0.5 ° from the average longitudinal axis of its respective single lower channel opening.

12. The method of claim 10, wherein the angle is an angle of no more than at least 5.0 ° from the average longitudinal axis of its respective single lower channel opening.

13. The method of claim 10, wherein the angle is an angle of at least 1.0 ° to no more than 5.0 ° from the average longitudinal axis of its respective single lower channel opening.

14. A memory array comprising a string of memory cells, comprising:

an upper stack over the lower stack, the lower stack comprising vertically alternating lower conductive layers and lower insulating layers, the upper stack comprising vertically alternating upper conductive layers and upper insulating layers;

an intermediate layer vertically between the upper stack and the lower stack, the intermediate layer being at least predominantly polysilicon and having a composition different from the composition of the upper conductive layer and the upper insulating layer directly above the intermediate layer and having a composition different from the composition of the lower conductive layer and the lower insulating layer directly below the intermediate layer; and

a string of channel material of a memory cell extending through the upper stack, the middle layer, and the lower stack.

15. The memory array of claim 14, wherein the intermediate layer is at least predominantly undoped polysilicon.

16. The memory array of claim 14 wherein the intermediate layer is at least predominantly doped polysilicon.

17. The memory array of claim 16, wherein the intermediate layer is at least predominantly semiconductive doped polysilicon.

18. The memory array of claim 16 wherein the intermediate layer is at least predominantly conductively doped polysilicon.

19. A memory array comprising a string of memory cells, comprising:

an intermediate layer vertically between the upper and lower stacks, the intermediate layer being at least predominantly electrically conductive and having a composition different from that of the upper electrically conductive layer directly above the intermediate layer and having a composition different from that of the lower electrically conductive layer directly below the intermediate layer; and

20. The memory array of claim 19 wherein the intermediate layer is at least predominantly at least one of an elemental metal, a metal alloy, a metal nitride, and a metal silicide.

21. The memory array of claim 19, wherein the intermediate layer is at least predominantly conductively doped semiconductive material.

22. The memory array of claim 19, wherein the conductive material of the intermediate layer is directly against the conductive material of the upper conductive layer directly above the intermediate layer and directly against the lower conductor layer directly below the intermediate layer.

23. The memory array of claim 22, wherein each of the conductive material, and the conductor material is a metal material.

24. The memory array of claim 23 wherein the metallic material is at least predominantly at least one of an elemental metal, a metal alloy, a metal nitride, and a metal silicide.

25. The memory array of claim 22, wherein each of the conductive material and the conductor material is a metal material, the conductive material being conductively doped semiconductive material.

26. A memory array comprising a string of memory cells, comprising:

an intermediate layer vertically between the upper stack and the lower stack; and

a string of channel material of memory cells extending through the upper stack, the middle layer, and the lower stack; a portion of a single one of the strings of channel material in the upper stack has an average longitudinal axis that is at an angle to an average longitudinal axis of the portion of the single string of channel material in the lower stack.

27. The memory array of claim 26, wherein the angle is an angle of at least 0.5 ° from the average longitudinal axis of the portion of the single string of channel material in the lower stack.

28. The memory array of claim 26, wherein the angle is an angle of no more than 5.0 ° from the average longitudinal axis of the portion of the single string of channel material in the lower stack.

29. The memory array of claim 26, wherein the angle is an angle of at least 1.0 ° to no more than 5.0 ° from the average longitudinal axis of the portion of the single string of channel material in the lower stack.

30. A memory array comprising a string of memory cells, comprising:

an intermediate layer vertically between the upper stack and the lower stack, the intermediate layer being at least one of (a), (b), and (c), wherein:

(a) the method comprises the following steps A thickness greater than a thickness of the upper conductive layer and a thickness of the upper insulating layer directly above the intermediate layer and greater than a thickness of the lower conductive layer and a thickness of the lower insulating layer directly below the intermediate layer;

(b) the method comprises the following steps At least predominantly polysilicon and having a composition different from the composition of the upper conductive layer and the upper insulating layer directly above the intermediate layer and a composition different from the composition of the lower conductive layer and the lower insulating layer directly below the intermediate layer; and

(c) the method comprises the following steps At least predominantly electrically conductive and having a composition different from the composition of the upper electrically conductive layer directly above the intermediate layer and having a composition different from the composition of the lower electrically conductive layer directly below the intermediate layer; and

31. The memory array of claim 30, which is (a).

32. The memory array of claim 30, which is (b).

33. The memory array of claim 30, which is (c).

34. The memory array of claim 30, being at least two of (a), (b), and (c).

35. The memory array of claim 30, being (a), (b), and (c).

36. The memory array of claim 30, wherein the angle is an angle of at least 0.5 ° from the average longitudinal axis of the portion of the single string of channel material in the lower stack.

37. The memory array of claim 30, wherein the angle is an angle of no more than 5.0 ° from the average longitudinal axis of the portion of the single string of channel material in the lower stack.

38. The memory array of claim 30, wherein the angle is an angle of at least 1.0 ° to no more than 5.0 ° from the average longitudinal axis of the portion of the single string of channel material in the lower stack.