CN113922683B - Single-stage wireless charging circuit based on digital rectifier - Google Patents

Single-stage wireless charging circuit based on digital rectifier Download PDF

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Publication number
CN113922683B
CN113922683B CN202111131834.2A CN202111131834A CN113922683B CN 113922683 B CN113922683 B CN 113922683B CN 202111131834 A CN202111131834 A CN 202111131834A CN 113922683 B CN113922683 B CN 113922683B
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constant
input
voltage
circuit
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CN113922683A (en
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马彦昭
孙宇飞
樊晓桠
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Northwestern Polytechnical University
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Northwestern Polytechnical University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/02—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from ac mains by converters
    • H02J7/04—Regulation of charging current or voltage
    • H02J7/06—Regulation of charging current or voltage using discharge tubes or semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J2207/20—Charging or discharging characterised by the power electronics converter

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)

Abstract

The invention relates to a single-stage wireless charging circuit based on a digital rectifier, which comprises a digital rectifier main circuit, a constant-current constant-voltage charging control circuit and a high-speed current sampling circuit. The digital rectifier main circuit generates alternating voltages VAC1 and VAC2, and transmits a battery voltage VBAT and a feedback voltage VFB to the constant-current constant-voltage control circuit. The high-speed current sampling circuit also converts the sampled inductive current into a sampling voltage and transmits the sampling voltage to the constant-current constant-voltage control circuit. The constant-current constant-voltage control circuit outputs a switch signal SW1 to control high-speed current sampling to sample when the power tube is conducted; the output switch signals SG1 and SG2 control the switch of the power tube, thereby achieving the purpose of constant-current constant-voltage charging. The invention solves the problem of lower efficiency of the tertiary structure. The life of the battery can be prolonged by using a digitally controlled constant current and constant voltage charging technique. Because of the digital design, the wireless charger has simple structure, good stability and convenient integration, and can reduce the chip area along with the reduction of the process size.

Description

Single-stage wireless charging circuit based on digital rectifier
Technical Field
The invention belongs to the technical field of electronic circuits, and relates to a single-stage wireless charging circuit based on a digital rectifier.
Background
Wireless charging is applied in various fields. In portable devices such as mobile phones, magnetic induction wireless charging is used. Magnetic induction wireless charging has no special requirement on the resonance frequency, and the transmission distance is between a few millimeters and a few centimeters. For implantable medical devices, magnetic resonance wireless charging is often employed. The transmission distance of the magnetic resonance type wireless charging can reach several centimeters or even meters, and the wireless charging needs to work at a resonance frequency when energy is transmitted. Currently, the wireless charging of magnetic resonance is generally carried out in two frequency bands, namely 13.56MHz and 6.78 MHz.
[ document 1 ] J.T.Hwang et al, "An All-in-One (Qi, PMA and A4 WP) 2.5. 2.5W Fully Integrated Wireless Battery Charger IC for Wearable Applications," ISSCC,2016, pp.378-380.
The current research on the wireless charging structure is mainly as shown in document 1. The wireless charger adopts a three-stage structure. The first stage is a diode rectifying circuit, the second stage is a DC-DC voltage stabilizing circuit, and the third stage is a constant current (constant current CC) constant voltage (constant voltage CV) charging circuit. However, the efficiency of each stage of such a tertiary structure is limited by its structure, resulting in a relatively low overall transmission efficiency.
Disclosure of Invention
Technical problem to be solved
In order to avoid the defects of the prior art, the invention provides a single-stage wireless charging circuit based on a digital rectifier, which solves the problem of lower efficiency of a three-stage structure. The invention adopts the counter to replace the traditional shift register control mode, thereby greatly reducing the chip area. The invention adopts the digital control constant-current constant-voltage charging technology, and can prolong the service life of the battery. The invention basically adopts digital design, has simple structure, good stability and convenient integration, and can reduce the chip area along with the reduction of the process size.
Technical proposal
A single-stage wireless charging circuit based on a digital rectifier is characterized by comprising a digital rectifier main circuit, a constant-current constant-voltage charging control circuit and a high-speed current sampling circuit; the charging signal is wirelessly induced to generate a signal V via the resonant inductance L and the resonant capacitance C AC1 And V AC2 Connected to the input of the main circuit of the digital rectifier and the signal V at its output BAT The output voltage of the circuit is connected with a charged battery; simultaneous signal V AC1 Connected with the sampling input end of the high-speed current sampling circuit and converted into a sampling voltage V SEN The output is fed back to the constant-current constant-voltage charging control circuit; in addition signal V AC1 And V AC2 Output signal V of digital rectifier main circuit BAT V (V) BAT Is divided into divided signals V FB All are connected with the input end of the constant-current constant-voltage charging control circuit, and control signals are generated through comparison of the battery voltage and a reference; output signal S of constant-current constant-voltage charge control circuit W1 Connected to the input of the high-speed current sampling circuit for controlling the current sampling circuitThe opening time of the road; output signal S G1[0:8] An output signal S of the constant-current constant-voltage charge control circuit connected with the input of the digital rectifier main circuit G2[0:8] Connected to an input of a main circuit of the digital rectifier, signal S G1[0:8] And signal S G2[0:8] The magnitude of the charging current is controlled.
The main circuit of the digital rectifier comprises a resonant inductor L, a resonant capacitor C and a 9-bit PMOS power tube M P1 -M P2 NMOS power tube M N1 -M N2 Feedback resistor R 1 -R 2 And capacitor C O The method comprises the steps of carrying out a first treatment on the surface of the The resonant inductance L and the resonant capacitance C are in parallel connection, and one end V of the resonant inductance L and the resonant capacitance C AC1 Connecting PMOS power tube M P1 Drain terminal of (2), NMOS power tube M N1 Drain terminal of (2) and NMOS power tube M N2 Is arranged at the gate end of the gate electrode; the other end V of the resonant inductance L and the resonant capacitance C AC2 Connecting PMOS power tube M P2 Drain terminal of (2), NMOS power tube M N2 Drain terminal of (2) and NMOS power tube M N1 Is arranged at the gate end of the gate electrode; PMOS power tube M P1 Output signal S of gate terminal and constant-current constant-voltage charge control circuit G1[0:8] The ends are connected; PMOS power tube M P2 Output signal S of gate terminal and constant-current constant-voltage charge control circuit G2[0:8] The ends are connected; PMOS power tube M P1 Source terminal of (1) and PMOS power tube M P2 Is commonly connected with the source terminal of the output voltage V BAT An end; NMOS power tube M N1 Source terminal of (2) and NMOS power tube M N2 Is commonly connected to the power ground; feedback resistor R 1 One end of (2) is connected with V BAT The other end is connected with V FB The ends are connected, and the feedback resistor R 2 One end of (2) is connected with V FB The end is connected with the other end is connected with the power ground; capacitor C O And one end of battery BAT and V BAT The ends are connected, and the other ends are connected with power ground.
The constant-current constant-voltage charging control circuit comprises a counter, comparators 1-6, 9-bit NAND gates NAND-NAND2, 9-bit drivers BUF1-BUF2, a D trigger, a NOR gate NOR and a multiplexer MUX; UP [0 ] of first bit input of counter]End sum DN [0 ]]The end is connected with the output of the D trigger; the positive input of the first comparator 1 and the output V of the digital rectifier main circuit AC1 The negative input end is connected with the output V of the main circuit of the digital rectifier BAT The ends are connected; the positive input of the second comparator 2 and the output V of the digital rectifier main circuit AC2 The negative input end is connected with the output V of the digital rectifier main circuit 1 BAT The ends are connected; the positive input end of the third comparator 3 is connected with the reference voltage, and the negative input end is connected with the output V of the digital rectifier main circuit FB The ends are connected; the positive input end of the fourth comparator 4 and the output V of the high-speed current sampling circuit SEN The negative input end is connected with the output end of the multiplexer MUX; the positive input of the fifth comparator 5 and the output V of the digital rectifier main circuit AC2 The negative input end is connected with the output V of the main circuit of the digital rectifier AC1 The ends are connected; the positive input end of the sixth comparator 6 is connected with the reference voltage, and the negative input end is connected with the output V of the digital rectifier main circuit FB The ends are connected; one input of NAND gate NAND1 and output S of first comparator 1 W1 The other input is connected with the output Q of the counter, and the output is connected with the input of the driver BUF 1; one input of NAND gate NAND2 and output S of second comparator 2 W2 The other input is connected with the output Q of the counter, and the output is connected with the input of the driver BUF 2; output S of driver BUF1 G1 Is connected with the input of the main circuit of the digital rectifier; output S of driver BUF2 G2 Is connected with the input of the main circuit of the digital rectifier; the D input end of the D trigger is connected with the output NOR of the NOR gate; the clock input end of the D trigger is connected with the output end of the fifth comparator 5; one input end of the nor gate is connected with the output end of the third comparator 3, and the other input end of the nor gate is connected with the input end of the fourth comparator 4; the selection end of the multiplexer MUX is connected with the output end of the sixth comparator 6; the input of the multiplexer MUX is connected to a reference voltage.
Advantageous effects
The invention provides a single-stage wireless charging circuit based on a digital rectifier, which comprises a digital rectifier main circuit, a constant-current constant-voltage charging control circuit and a high-speed current sampling circuit. The digital rectifier main circuit generates alternating voltages VAC1 and VAC2, and transmits a battery voltage VBAT and a feedback voltage VFB to the constant-current constant-voltage control circuit. The high-speed current sampling circuit also converts the sampled inductive current into a sampling voltage and transmits the sampling voltage to the constant-current constant-voltage control circuit. The constant-current constant-voltage control circuit outputs a switch signal SW1 to control high-speed current sampling to sample when the power tube is conducted; the output switch signals SG1 and SG2 control the switch of the power tube, thereby achieving the purpose of constant-current constant-voltage charging.
Compared with the three-stage wireless charger provided in the background art, the circuit adopts a single-stage digital rectifier structure, and solves the problem of lower efficiency of the three-stage structure. The life of the battery can be prolonged by using a digitally controlled constant current and constant voltage charging technique. Because of the digital design, the wireless charger has simple structure, good stability and convenient integration, and can reduce the chip area along with the reduction of the process size.
1. The invention discloses a wireless charger with a single-stage structure: the problem that the transmission efficiency of the traditional three-stage structure is limited by each stage is solved. The advantage of a single-stage structure is utilized, and the transmission efficiency of the whole system is improved.
2. The invention discloses a digital control constant-current constant-voltage charging mode: the constant-current constant-voltage charging technology can prolong the service life of the battery, is convenient for integration by using digital control, and can reduce the area of a chip along with the reduction of the process size.
Drawings
Fig. 1 is a block diagram of a single-stage wireless charger based on a digital rectifier according to the present invention
Fig. 2 is a schematic diagram of a single-stage wireless charger circuit based on a digital rectifier according to the present invention
FIG. 3 is a timing chart of a single-stage wireless charger based on a digital rectifier according to the present invention
FIG. 4 shows a counter circuit of a single-stage wireless charger based on a digital rectifier according to the present invention
FIG. 5 shows a specific implementation of a high-speed current sampling circuit of a single-stage wireless charger based on a digital rectifier according to the present invention
Detailed Description
The invention will now be further described with reference to examples, figures:
reference is made to fig. 1-5. The invention discloses a single-stage wireless charger circuit based on a digital rectifier, which consists of a digital rectifier main circuit 1, a constant-current constant-voltage charging control circuit 2 and a high-speed current sampling circuit 3.
Single-stage wireless charger circuit based on digital rectifier, its characterized in that: the wireless charger circuit comprises a digital rectifier main circuit 1, a constant-current constant-voltage charging control circuit 2 and a high-speed current sampling circuit 3. Output signal V of digital rectifier main circuit 1 BAT An output signal V of the digital rectifier main circuit 1 is connected with the input of the constant-current constant-voltage charge control circuit 2 FB An output signal V of the digital rectifier main circuit 1 is connected with the input of the constant-current constant-voltage charge control circuit 2 AC2 An output signal V of the digital rectifier main circuit 1 is connected with the input of the constant-current constant-voltage charge control circuit 2 AC1 An output signal V of the digital rectifier main circuit 1 is connected with the input of the constant-current constant-voltage charge control circuit 2 AC1 An output signal S of the constant-current constant-voltage charge control circuit 2 connected to an input of the high-speed current sampling circuit 3 W1 An output signal S of the constant-current constant-voltage charge control circuit 2 connected to an input of the high-speed current sampling circuit 3 G1[0:8] An output signal S of the constant-current constant-voltage charge control circuit 2 connected to an input of the digital rectifier main circuit 1 G2[0:8] An output signal V of the high-speed current sampling circuit 3 is connected to an input of the digital rectifier main circuit 1 SEN Is connected with the input of the constant-current constant-voltage charge control circuit 2.
The wireless charger consists of a constant current loop and a constant voltage loop. In constant current loop control, a high-speed current sampling circuit 3 is used for controlling a lower power tube M in a digital rectifier main circuit 1 N1 Is not equal to the drain terminal V of AC1 Sampling the charging current and converting the charging current into a sampling voltage V SEN And outputting. The comparator 4 in the constant-current constant-voltage charge control circuit 2 compares V by comparison SEN And a reference voltage output signal V CC Then output to D flip-flop through NAND gate, when clock rising edge reaches output UP [0 ]]And DN [0 ]]A signal.The counter receives UP [0 ]]And DN [0 ]]Post signal control Q0:8]Increase or decrease, thereby controlling the switch M P1 [k]And M is as follows P2 [k]Increasing or decreasing, thereby increasing or decreasing the charging current. In a constant voltage loop, the output signal V of the digital rectifier main circuit 1 FB Is the battery voltage passing through resistor R 1 And resistance R 2 Partial pressure is generated. The comparator 3 in the constant-current constant-voltage charge control circuit 2 compares V FB And a reference voltage output signal V CV Similar to the constant current loop, when V FB Above the reference voltage, the counter outputs the signal Q0:8]The number of switches is reduced, so that the charging current is reduced, and the purpose of constant voltage is achieved.
The digital rectifier main circuit 1 is composed of a resonant inductor L, a resonant capacitor C and a 9-bit PMOS power tube M P1 -M P2 NMOS power tube M N1 -M N2 Feedback resistor R 1 -R 2 Capacitance C O And battery BAT. The resonant inductance L and the resonant capacitance C are in parallel connection, and one end V of the resonant inductance L and the resonant capacitance C AC1 Connecting PMOS power tube M P1 Drain terminal of (2), NMOS power tube M N1 Drain terminal of (2) and NMOS power tube M N2 Is arranged at the gate end of the gate electrode; the other end V of the resonant inductance L and the resonant capacitance C AC2 Connecting PMOS power tube M P2 Drain terminal of (2), NMOS power tube M N2 Drain terminal of (2) and NMOS power tube M N1 Is arranged at the gate end of the gate electrode; PMOS power tube M P1 Gate terminal of (2) and output S of constant current constant voltage charge control circuit G1 The ends are connected; PMOS power tube M P2 Gate terminal of (2) and output S of constant current constant voltage charge control circuit G2 The ends are connected; PMOS power tube M P1 Source terminal of (1) and PMOS power tube M P2 Is commonly connected with the source end of V BAT An end; NMOS power tube M N1 Source terminal of (2) and NMOS power tube M N2 Is commonly connected to the power ground; feedback resistor R 1 One end of (2) is connected with V BAT The other end is connected with V FB The ends are connected, and the feedback resistor R 2 One end of (2) is connected with V FB The end is connected with the other end is connected with the power ground; capacitor C O And one end of battery BAT and V BAT The ends are connected, and the other ends are connected with power ground.
The constant-current constant-voltage charging control circuit 2 consists of a counter, comparators 1-6, 9-bit NAND gates NAND-NAND2, 9-bit drivers BUF1-BUF2, a D trigger, a NOR gate NOR and a multiplexer MUX. UP [0 ] of first bit input of counter]End sum DN [0 ]]The end is connected with the output of the D trigger; the positive input of the first comparator 1 and the output V of the digital rectifier main circuit 1 AC1 The negative input end is connected with the output V of the digital rectifier main circuit 1 BAT The ends are connected; the positive input of the second comparator 2 and the output V of the digital rectifier main circuit 1 AC2 The negative input end is connected with the output V of the digital rectifier main circuit 1 BAT The ends are connected; the positive input end of the third comparator 3 is connected with the reference voltage, and the negative input end is connected with the output V of the digital rectifier main circuit 1 FB The ends are connected; the positive input of the fourth comparator 4 and the output V of the high-speed current sampling circuit 3 SEN The negative input end is connected with the output end of the multiplexer MUX; the positive input of the fifth comparator 5 and the output V of the digital rectifier main circuit 1 AC2 The negative input end is connected with the output V of the digital rectifier main circuit 1 AC1 The ends are connected; the positive input of the sixth comparator 6 is connected to the reference voltage and the negative input is connected to the output V of the digital rectifier main circuit 1 FB The ends are connected; one input of NAND gate NAND1 and output S of first comparator 1 W1 The other input is connected with the output Q of the counter, and the output is connected with the input of the driver BUF 1; one input of NAND gate NAND2 and output S of second comparator 2 W2 The other input is connected with the output Q of the counter, and the output is connected with the input of the driver BUF 2; output S of driver BUF1 G1 Connected to an input of the digital rectifier main circuit 1; output S of driver BUF2 G2 Connected to an input of the digital rectifier main circuit 1; the D input end of the D trigger is connected with the output NOR of the NOR gate; the clock input end of the D trigger is connected with the output end of the fifth comparator 5; one input end of the nor gate is connected with the output end of the third comparator 3, and the other input end of the nor gate is connected with the input end of the fourth comparator 4; the selection end of the multiplexer MUX is connected with the output end of the sixth comparator 6; input terminal of multiplexer MUX is phase with reference voltageAnd (3) connecting.
The counter consists of a 9-bit register structure. Bit 0 consists of a JK flip-flop. The J end and the K end of the JK trigger are connected with a power supply voltage; the clock terminal is connected to the output terminal of the fifth comparator 5 of the constant-current constant-voltage charge control circuit 2. The 1 st bit to the 7 th bit have the same structure and are composed of a JK trigger, NAND gates NAND1-NAND3 and inverters INV1-INV 2. The J end and the K end of the JK trigger are connected with the output of the NAND gate NAND3, and the clock end is connected with the output end of the fifth comparator 5 of the constant-current constant-voltage charging control circuit 2; one end of the input end of the NAND gate NAND1 is connected with the UP end of the upper bit, and the other end of the input end of the NAND gate NAND1 is connected with the Q end of the upper bit; one end of the input end of the NAND gate NAND2 is connected with the DN end of the last bit, and the other end of the input end of the NAND gate NAND2 is connected with the Q opposite end of the last bit; an input of the inverter INV1 is connected with an output of the NAND gate NAND 1; an input of the inverter INV2 is connected with an output of the NAND gate NAND 2; one end of the input end of the NAND gate NAND3 is connected with the output of the NAND gate NAND1, and the other end of the input end of the NAND gate NAND3 is connected with the output of the NAND gate NAND 2. Bit 8 consists of a JK flip-flop and NAND gates NAND1-NAND 3. The J end and the K end of the JK trigger are connected with the output end of the NAND gate NAND 3; one end of the input end of the NAND gate NAND1 is connected with the UP end of the 7 th bit, and the other end of the input end of the NAND gate NAND1 is connected with the Q end of the 7 th bit; one end of the input end of the NAND gate NAND2 is connected with the Q reverse end of the 7 th bit, and the other end of the input end of the NAND gate NAND2 is connected with the DN end of the 7 th bit; one end of the input end of the NAND gate NAND3 is connected with the output end of the NAND gate NAND1, and the other end is connected with the input end of the NAND gate NAND 2.
The high-speed current sampling circuit consists of a switch and an NMOS sampling tube M S1 -M S2 The circuit comprises an amplifier and a current-to-voltage circuit. The amplifier is composed of a PMOS tube M 1 -M 6 And NMOS tube M 7 -M 8 Composition, V X Terminal and V Y The terminal is the source input of the amplifier. PMOS tube M for current-to-voltage circuit 11 -M 14 NMOS tube M 9 Resistance R S And capacitor C S Composition is prepared. The control end of the switch and the output S of the first comparator 1 of the constant-current constant-voltage charge control circuit 2 W1 The input end of the switch is connected with ground and the other end is connected with the output V of the digital rectifier main circuit 1 AC1 The ends are connected; NMOS sampling tube M S1 The source terminal of (2) is connected to ground, the drain terminal is connected to the drain input V of the amplifier X Are connected; NMOS sampling tube M S2 The source terminal of the switch is connected with the output terminal of the switch, and the drain terminal is connected with the drain input V of the amplifier Y Are connected.
Reference is made to fig. 2-5. The wireless charger of the invention is embodied as follows, the inductance L and the capacitance C resonate to generate sine wave V AC1 And V AC2 The voltage of VAC1 and VBAT is compared by the comparator 1, when VAC1 is larger than VBAT, the output of the comparator controls the PMOS power tube MP1 to be opened, the voltage of VAC2 and VBAT is compared by the comparator 2, and when VAC2 is larger than VBAT, the output of the comparator controls the PMOS power tube MP2 to be opened. The wireless charger has two modes, namely a constant current mode and a constant voltage mode. The comparator 6 compares the feedback voltage V FB With the reference voltage, the reference voltage of the comparator 4 is selected when the battery voltage V BAT When the voltage is less than 2.8V, the reference voltage V is selected REF_TC At this time, the constant current loop is charged with a small current; when the battery voltage V BAT When the voltage is greater than 2.8V, the reference voltage V is selected REF_CC At this time, the constant current loop is charged with a large current.
In the constant current loop, the high-speed current sampling circuit 3 is arranged at the drain terminal V of the lower power tube MN1 in the digital rectifier main circuit 1 AC1 Sampling the charging current and converting the charging current into a sampling voltage V SEN And outputting. The fourth comparator 4 compares V by comparison SEN And a reference voltage output signal V CC Then output to D flip-flop through NAND gate, when clock rising edge reaches output UP [0 ]]And DN [0 ]]A signal. The counter receives UP [0 ]]And DN [0 ]]Post signal control Q0:8]Increasing or decreasing, thereby controlling the switch MP1[ k ]]With MP2[ k ]]Increasing or decreasing, thereby increasing or decreasing the charging current. When sampling voltage V SEN When the charging current is higher than the reference voltage, the charging current is larger than the set value, and the D trigger DN [0 ]]Set to 1, counter output Q0:8]The number of the PMOS power tubes to be turned on is reduced, so that the charging current is reduced. When sampling voltage V SEN Lower than the reference voltage.
In a constant voltage loop, the output signal V of the digital rectifier main circuit 1 FB Is generated by dividing the battery voltage by a resistor R1 and a resistor R2. The comparator 3 compares V by comparison FB And a reference voltage output signal V CV Similar to the constant current loop, when V FB Above the reference voltage, the counter outputs the signal Q0:8]The number of switches is reduced, so that the charging current is reduced, and the purpose of constant voltage is achieved.

Claims (4)

1. A single-stage wireless charging circuit based on a digital rectifier is characterized by comprising a digital rectifier main circuit, a constant-current constant-voltage charging control circuit and a high-speed current sampling circuit; the charging signal is wirelessly induced to generate a signal V via the resonant inductance L and the resonant capacitance C AC1 And V AC2 Connected to the input of the main circuit of the digital rectifier and the signal V at its output BAT The output voltage of the circuit is connected with a charged battery; simultaneous signal V AC1 Connected with the sampling input end of the high-speed current sampling circuit and converted into a sampling voltage V SEN The output is fed back to the constant-current constant-voltage charging control circuit; in addition signal V AC1 And V AC2 Output signal V of digital rectifier main circuit BAT V (V) BAT Is divided into divided signals V FB All are connected with the input end of the constant-current constant-voltage charging control circuit, and control signals are generated through comparison of the battery voltage and a reference; output signal S of constant-current constant-voltage charge control circuit W1 The switching-on time of the current sampling circuit is controlled by connecting with the input of the high-speed current sampling circuit; output signal S G1[0:8] An output signal S of the constant-current constant-voltage charge control circuit connected with the input of the digital rectifier main circuit G2[0:8] Connected to an input of a main circuit of the digital rectifier, signal S G1[0:8] And signal S G2[0:8] Controlling the magnitude of the charging current;
the constant-current constant-voltage charging control circuit comprises a counter, comparators 1-6, 9-bit NAND gates NAND1-NAND2, 9-bit drivers BUF1-BUF2, a D trigger, a NOR gate NOR and a multiplexer MUX; UP [0 ] of first bit input of counter]End sum DN [0 ]]The end is connected with the output of the D trigger; the positive input end of the first comparator (1) and the output V of the digital rectifier main circuit AC1 The negative input end is connected with the output V of the main circuit of the digital rectifier BAT End to endThe method comprises the steps of carrying out a first treatment on the surface of the The positive input end of the second comparator (2) and the output V of the digital rectifier main circuit AC2 The negative input end is connected with the output V of the main circuit of the digital rectifier BAT The ends are connected; the positive input end of the third comparator (3) is connected with the reference voltage, and the negative input end is connected with the output V of the digital rectifier main circuit FB The ends are connected; the positive input end of the fourth comparator (4) and the output V of the high-speed current sampling circuit SEN The negative input end is connected with the output end of the multiplexer MUX; the positive input end of the fifth comparator (5) and the output V of the digital rectifier main circuit AC2 The negative input end is connected with the output V of the main circuit of the digital rectifier AC1 The ends are connected; the positive input end of the sixth comparator (6) is connected with the reference voltage, and the negative input end is connected with the output V of the digital rectifier main circuit FB The ends are connected; one input of NAND gate NAND1 and output S of first comparator (1) W1 The other input is connected with the output Q of the counter, and the output is connected with the input of the driver BUF 1; one input of NAND gate NAND2 and output S of second comparator (2) W2 The other input is connected with the output Q of the counter, and the output is connected with the input of the driver BUF 2; output S of driver BUF1 G1 Is connected with the input of the main circuit of the digital rectifier; output S of driver BUF2 G2 Is connected with the input of the main circuit of the digital rectifier; the D input end of the D trigger is connected with the output NOR of the NOR gate; the clock input end of the D trigger is connected with the output end of the fifth comparator (5); one input end of the NOR gate is connected with the output end of the third comparator (3), and the other input end of the NOR gate is connected with the input end of the fourth comparator (4); the selection end of the multiplexer MUX is connected with the output end of the sixth comparator (6); the input of the multiplexer MUX is connected to a reference voltage.
2. The digital rectifier-based single-stage wireless charging circuit of claim 1, wherein: the main circuit of the digital rectifier comprises a resonant inductor L, a resonant capacitor C and a 9-bit PMOS power tube M P1 -M P2 NMOS power tube M N1 -M N2 Feedback resistor R 1 -R 2 And capacitor C O The method comprises the steps of carrying out a first treatment on the surface of the Harmonic waveThe resonant inductance L and the resonant capacitance C are in parallel connection, and one end V of the resonant inductance L and the resonant capacitance C AC1 Connecting PMOS power tube M P1 Drain terminal of (2), NMOS power tube M N1 Drain terminal of (2) and NMOS power tube M N2 Is arranged at the gate end of the gate electrode; the other end V of the resonant inductance L and the resonant capacitance C AC2 Connecting PMOS power tube M P2 Drain terminal of (2), NMOS power tube M N2 Drain terminal of (2) and NMOS power tube M N1 Is arranged at the gate end of the gate electrode; PMOS power tube M P1 Output signal S of gate terminal and constant-current constant-voltage charge control circuit G1[0:8] The ends are connected; PMOS power tube M P2 Output signal S of gate terminal and constant-current constant-voltage charge control circuit G2[0:8] The ends are connected; PMOS power tube M P1 Source terminal of (1) and PMOS power tube M P2 Is commonly connected with the source terminal of the output voltage V BAT An end; NMOS power tube M N1 Source terminal of (2) and NMOS power tube M N2 Is commonly connected to the power ground; feedback resistor R 1 One end of (2) is connected with V BAT The other end is connected with V FB The ends are connected, and the feedback resistor R 2 One end of (2) is connected with V FB The end is connected with the other end is connected with the power ground; capacitor C O And one end of battery BAT and V BAT The ends are connected, and the other ends are connected with power ground.
3. The digital rectifier-based single-stage wireless charging circuit of claim 1, wherein: the high-speed current sampling circuit comprises a switch and an NMOS sampling tube M S1 -M S2 An amplifier and a current-to-voltage circuit; the amplifier is composed of a PMOS tube M 1 -M 6 And NMOS tube M 7 -M 8 Composition, V X Terminal and V Y The end is the source end input of the amplifier; PMOS tube M for current-to-voltage circuit 11 -M 14 NMOS tube M 9 Resistance R S And capacitor C S Composition; the control end of the switch and the output S of the first comparator (1) of the constant-current constant-voltage charge control circuit W1 The end is connected with one end of the input end of the switch is connected with the ground, and the other end is connected with the output V of the digital rectifier main circuit AC1 The ends are connected; NMOS sampling tube M S1 The source terminal of (2) is connected to ground, the drain terminal is connected to the drain input V of the amplifier X Are connected; NMOS sampling tube M S2 The source terminal of the switch is connected with the output terminal of the switch, and the drain terminal is connected with the drain input V of the amplifier Y Are connected.
4. The digital rectifier-based single-stage wireless charging circuit of claim 1, wherein: the counter includes a 9-bit register structure; the 0 th bit consists of a JK trigger, and the J end and the K end of the JK trigger are connected with a power supply voltage; the clock end is connected with the output end of a fifth comparator (5) of the constant-current constant-voltage charging control circuit; the 1 st bit to the 7 th bit have the same structure and consist of a JK trigger, NAND gates NAND1-NAND3 and inverters INV1-INV 2; the J end and the K end of the JK trigger are connected with the output of the NAND gate NAND3, and the clock end is connected with the output end of a fifth comparator (5) of the constant-current constant-voltage charging control circuit; one end of the input end of the NAND gate NAND1 is connected with the UP end of the upper bit, and the other end of the input end of the NAND gate NAND1 is connected with the Q end of the upper bit; one end of the input end of the NAND gate NAND2 is connected with the DN end of the last bit, and the other end of the input end of the NAND gate NAND2 is connected with the Q opposite end of the last bit; an input of the inverter INV1 is connected with an output of the NAND gate NAND 1; an input of the inverter INV2 is connected with an output of the NAND gate NAND 2; one end of the input end of the NAND gate NAND3 is connected with the output of the NAND gate NAND1, and the other end of the input end of the NAND gate NAND3 is connected with the output of the NAND gate NAND 2; bit 8 consists of a JK flip-flop and NAND gates NAND1-NAND 3; the J end and the K end of the JK trigger are connected with the output end of the NAND gate NAND 3; one end of the input end of the NAND gate NAND1 is connected with the UP end of the 7 th bit, and the other end of the input end of the NAND gate NAND1 is connected with the Q end of the 7 th bit; one end of the input end of the NAND gate NAND2 is connected with the Q reverse end of the 7 th bit, and the other end of the input end of the NAND gate NAND2 is connected with the DN end of the 7 th bit; one end of the input end of the NAND gate NAND3 is connected with the output end of the NAND gate NAND1, and the other end is connected with the input end of the NAND gate NAND 2.
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