CN113921691A - Josephson junction, josephson junction array, preparation method and application thereof - Google Patents

Josephson junction, josephson junction array, preparation method and application thereof Download PDF

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CN113921691A
CN113921691A CN202111480542.XA CN202111480542A CN113921691A CN 113921691 A CN113921691 A CN 113921691A CN 202111480542 A CN202111480542 A CN 202111480542A CN 113921691 A CN113921691 A CN 113921691A
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josephson junction
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杨丽娜
冯加贵
熊康林
贾浩林
吴艳伏
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Gusu Laboratory of Materials
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Abstract

The invention provides a Josephson junction, a Josephson junction array, a preparation method and application thereof, wherein the preparation method of the Josephson junction comprises the following steps: a-plane sapphire is selected as a substrate, and a quasi-epitaxial Ta (110) superconducting film with a smooth surface can be prepared based on small lattice mismatch and is used as a Josephson junction lower electrode; further, dense, stable and controllable Ta is formed by oxidation or deposition methods2O5The oxide layer is used as a Josephson junction middle layer; a Ta superconducting layer is deposited on the substrate to be used as a Josephson junction upper electrode; and the subsequent compatible photoetching and air bridge scheme is used for preparing the superconducting circuit and conducting the junction electrode, so that the preparation of the Josephson junction array is completed. The related scheme adopts a chemical passivation mode to protect the superconducting circuit and the Josephson junction. The invention avoids repeatingThe method has the advantages of simple process steps, high yield, large-scale production and the like.

Description

Josephson junction, josephson junction array, preparation method and application thereof
Technical Field
The invention belongs to the technical field of superconducting chips, and relates to a Josephson junction, a Josephson junction array, a preparation method and application thereof.
Background
Quantum computers are devices for information processing and operation based on quantum mechanics, and compared with classical computers, the quantum computers have the advantage of high computing speed, and the arrival of the quantum technology era is marked. Quantum chips are key devices for implementing quantum computing. To date, a great deal of research focus has been on superconducting qubit systems based on josephson junctions (arrays), which have been widely studied due to their advantages of high gate operation fidelity, good system integration, and compatibility with conventional semiconductor fabrication processes, making them the most competitive candidates for quantum computing.
The preparation of the Josephson junction with high quality and high stability is the key for ensuring the characteristic performance of the quantum ratio. The traditional josephson junction is a sandwich structure, the upper and lower layers are usually low temperature superconducting layers, such as niobium, tantalum and aluminum films, and a very thin insulating layer, such as aluminum oxide, is sandwiched between the upper and lower layers, wherein the traditional josephson junction mainly relates to the disciplines of material growth, nano-processing technology and the like. Based on Al/AlO so farxAl superconductive josephson junctions have been of high quality, mainly achieved by means of the suspensoid process and the dual-angle evaporation method, for example, CN108110131A discloses the dual-angle coating method, but the oblique coating method has certain disadvantages, for example: the film thickness uniformity in a large range cannot be guaranteed, the generated redundant patterns are not beneficial to high integration level, and meanwhile, the problems of low yield and the like caused by glue pollution and broken lapping wires exist. In terms of materials, Al is active in chemical properties and is naturally oxidized AlO at room temperaturexHas certain dielectric loss when working at low temperature. At the same time, AlOxAlthough the oxide layer is dense and can achieve some passivation protection through oxidation treatment, it is still unstable in the atmospheric environment or in the photolithography process, and is easily denatured after being subjected to moisture or chemical agent treatment, further increasing dielectric loss, and changing the critical current of the josephson junction.
The metal tantalum has received great attention due to its high superconducting transition temperature (Tc = 4.5K) and its small quasi-particle density in the superconducting qubit working environment, especially the oxide component on the Ta surface (Ta)2O5) Has high compactness, low dielectric loss and high stability. Thus, stable body-centered cubic Ta film materials have been widely used in superconducting circuit structures. Furthermore, researchers prefer to obtain the Ta (110) crystal plane rather than the Ta (111) crystal plane based on the compactness and saturation of the oxide layer. Limited to the triple symmetry of the C-plane sapphire substrate itself, with the crystal orientation (0001), the grown thin film material has a different orientation, grown in the vertical direction of [ 100 ] or [ 111 ]. Meanwhile, a Ta (110) film grown on a C-plane sapphire substrate is very likely to be accompanied by a small amount of Ta (111) phase growth, and finally becomes a mixed-phase Ta thin film. In superconducting qubits, however, higher quality Ta single crystal epitaxial films are required as superconducting circuits, and the grown oxides should have high process stability and low dielectric loss.
In summary, in order to realize high-quality, high-stability and scalable quantum chips, it is necessary to start with material growth and to improve the current josephson junction process.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a Josephson junction, a Josephson junction array, a preparation method and application thereof, wherein A-surface sapphire is selected as a substrate, and a quasi-epitaxial Ta (110) superconducting thin film with a smooth surface and high quality is prepared as a lower electrode of the Josephson junction based on small lattice mismatch. Thereon, a dense, stable and controllable Ta is formed by means of an oxidation or deposition process2O5The oxide layer is used as an intermediate layer, and further, a superconductive Ta layer is deposited to be used as a Josephson junction upper electrode to prepare and obtain Ta/Ta2O5a/Ta Josephson junction sandwich structure. And the subsequent compatible photoetching and air bridge scheme is used for preparing the superconducting circuit and conducting the junction electrode, so that the preparation of the Josephson junction array is completed. The related scheme adopts a chemical passivation mode to carry out ultra-deep etchingThe conductive path and the Josephson junction are protected. The invention avoids complex process steps such as suspension glue and double-dip-angle evaporation, and has the characteristics of simple process steps, high yield, large-scale production and the like.
In order to achieve the purpose, the invention adopts the following technical scheme:
in a first aspect, the present invention provides a method of preparing a josephson junction, the method comprising:
preparing a lower electrode Ta layer on the A-surface sapphire substrate, and sequentially preparing Ta on the lower electrode Ta layer2O5And processing the Josephson junction graph to obtain the Josephson junction.
According to the invention, the lower electrode Ta layer is prepared by adopting the A-surface sapphire as the substrate, and the high-quality quasi-single crystal Ta (110) film with almost single orientation, namely the lower electrode Ta layer, can be prepared based on small lattice mismatch; further, based on the high-quality lower electrode, the surface of the lower electrode is easy to generate compact, stable and nearly single valence Ta2O5A layer, the oxide layer having low dielectric loss.
In the prior art, a C-plane sapphire substrate is adopted, the triple symmetry relationship of the substrate is limited, the grown Ta layer has different orientations and grows along the vertical direction of 100 or 111, and multiple grain boundaries inevitably exist in the Ta layer. Meanwhile, a Ta (110) film grown on a C-plane sapphire substrate is very likely to be accompanied by a small amount of Ta (111) phase growth, and finally becomes a mixed-phase Ta thin film.
It should be noted that the present invention does not specifically require or be limited to the pattern processing manner, and those skilled in the art can reasonably select the pattern processing manner according to the operation requirement, for example, the pattern processing manner is a photolithography process, and in the photolithography process, the superconducting tunneling channel of the josephson junction can be protected by performing passivation optimization on the Ta (110) thin film oxide layer exposed by etching.
In the present invention, the crystal orientation of the a-plane sapphire substrate was (11-20).
It should be noted that the size of the a-plane sapphire substrate is not specifically required and limited, and those skilled in the art can reasonably select the substrate according to the operation requirements, for example, the thickness is 0.43-0.50 mm, and a clean-free substrate is preferred, so as to avoid introducing other impurities in the chemical cleaning process.
According to a preferable technical scheme of the invention, the A-surface sapphire substrate is pretreated, and the pretreatment process comprises substrate surface atomic step treatment, back surface pre-plating film and active oxygen auxiliary surface cleaning which are sequentially carried out.
In one embodiment, the pretreatment process of the present invention includes substrate atomic step treatment, back surface pre-plating, and active oxygen plasma assisted high temperature annealing, and specifically includes the following steps:
(a) performing high-temperature annealing on the A-surface sapphire substrate in a 900-1200 ℃ tubular furnace in an atmosphere with oxygen flux of more than or equal to 60sccm for more than or equal to 1h to obtain a smooth substrate surface with distinct atomic steps, wherein the temperature is 900 ℃, 950 ℃, 1000 ℃, 1050 ℃, 1100 ℃, 1150 ℃ or 1200 ℃, the oxygen flux is 60sccm, 65sccm, 70sccm, 75sccm, 80sccm, 85sccm, 90sccm, 95sccm or 100sccm, and the annealing time is 1h, 2h, 3h or 4h and the like;
(b) pre-plating the back surface of the A-surface sapphire substrate obtained in the step (a) in a vacuum environment, wherein the plating film has a light-shielding effect, and is preferably made of a high-temperature-resistant and oxidation-resistant metal material, such as a titanium film with the thickness of more than or equal to 50nm, so that the temperature uniformity in the post-treatment of the substrate and the growth process of the material is ensured;
(c) a first stage of treating the A-surface sapphire substrate obtained in the step (b) with active oxygen plasma with oxygen flow rate of less than or equal to 1sccm and radio frequency power of 80-120W for 20-40 min in a high vacuum environment at 300-500 ℃, wherein the filter screen needs to filter out charged ions damaging the substrate, for example, the temperature is 300 ℃, 350 ℃, 400 ℃, 450 ℃ or 500 ℃, the oxygen flow rate is 0.2sccm, 0.3sccm, 0.4sccm, 0.5sccm, 0.6sccm, 0.7sccm, 0.8sccm, 0.9sccm or 1.0sccm, the radio frequency power is 80W, 90W, 100W, 110W or 120W, and the time is 20min, 22min, 24min, 26min, 28min, 30min, 32min, 34min, 36min, 38min or 40 min; and a second stage, stopping oxygen introduction, and annealing at 600-1000 ℃ in a pure high-temperature environment for 20-40 min, for example, at 600 ℃, 650 ℃, 700 ℃, 750 ℃, 800 ℃, 850 ℃, 900 ℃, 950 ℃ or 1000 ℃ for 20min, 22min, 24min, 26min, 28min, 30min, 32min, 34min, 36min, 38min or 40 min.
As a preferred technical solution of the present invention, the preparation manner of the lower electrode Ta layer and the upper electrode Ta layer includes a deposition method.
The invention does not make specific requirements and special limitations on the deposition modes of the lower electrode Ta layer and the upper electrode Ta layer, and a person skilled in the art can reasonably select the deposition modes according to the deposition requirements.
Said Ta2O5The layer may be formed by oxidation or deposition.
As a preferred embodiment of the present invention, the deposition method includes one or a combination of at least two of magnetron sputtering, molecular beam epitaxy, and electron beam evaporation.
In one embodiment, an ultra-high vacuum magnetron sputtering method is adopted to prepare a lower electrode Ta layer, and the working parameters of the ultra-high vacuum magnetron sputtering method comprise:
the growth temperature is 500-700 ℃, the working pressure is less than or equal to 2mTorr, the direct current power is 50-200W, the target base distance is 90-150 mm, and a lower electrode Ta layer with the thickness of 50-150 nm is grown. For example, a temperature of 500 ℃, 550 ℃, 600 ℃, 650 ℃, 660 ℃ or 700 ℃, a working pressure of 1.0mTorr, 1.2mTorr, 1.4mTorr, 1.6mTorr, 1.8mTorr or 2.0mTorr, a DC power of 50W, 65W, 80W, 95W, 110W, 125W, 140W, 155W, 170W, 185W or 200W, a target base distance of 90mm, 100mm, 110mm, 120mm, 130mm, 140mm or 150mm, and a growth thickness of 50nm, 70nm, 90nm, 110nm, 130nm or 150 nm. As known to those skilled in the art, a long-time pre-sputtering step needs to be performed on the Ta target before growth to ensure a clean target surface, and in addition, high-temperature empty burning needs to be performed on a sample table in a growth cavity of the equipment, so that pollution caused by impurities volatilized by the sample table in a high-temperature environment in the growth process is avoided. And under the condition that the background vacuum of the growth cavity meets the requirement, transferring the substrate to the growth cavity, degassing the substrate at high temperature, and evaporating water vapor and other adsorption adsorbed on the surface of the substrate.
In one embodiment, an ultra-high vacuum magnetron sputtering method is provided for preparing the upper electrode Ta layer, and the working parameters of the ultra-high vacuum magnetron sputtering method comprise:
the growth temperature is 300-500 ℃, the working pressure is not less than 5mTorr, the direct current power is 50-200W, the target base distance is 90-150 mm, and an upper electrode Ta layer with the thickness of 100-200 nm is grown. For example, the temperature is 300 ℃, 350 ℃, 400 ℃, 450 ℃ or 500 ℃, the working pressure is 5mTorr, 7mTorr, 9mTorr, 11mTorr, 13mTorr, 15mTorr or 20mTorr, the direct current power is 50W, 65W, 80W, 95W, 110W, 125W, 140W, 155W, 170W, 185W or 200W, the target base distance is 90mm, 100mm, 110mm, 120mm, 130mm, 140mm or 150mm, and the growth thickness is 100nm, 120nm, 140nm, 160nm, 180nm or 200 nm. As known to those skilled in the art, a long-time pre-sputtering step needs to be performed on the Ta target before growth to ensure a clean target surface, and in addition, high-temperature empty burning needs to be performed on a sample table in a growth cavity of the equipment, so that pollution caused by impurities volatilized by the sample table in a high-temperature environment in the growth process is avoided. And under the condition that the background vacuum of the growth cavity meets the requirement, the sample is transferred to the growth cavity, the substrate is subjected to high-temperature degassing, and water vapor and other adsorption adsorbed on the surface of the sample are evaporated.
The lower electrode Ta layer and the upper electrode Ta layer are prepared in the same or different modes.
As a preferred embodiment of the present invention, the oxidation method includes a quasi-in-situ high-temperature thermal oxidation method or a low-temperature wet oxidation method.
In one embodiment, Ta is prepared by a quasi-in-situ high temperature thermal oxidation method2O5A layer, comprising: oxidizing the surface of the lower electrode Ta layer at 200-600 ℃ in an oxygen pressure atmosphere of 100-1000 Pa to generate 2-4 nm Ta2O5A layer, for example, at a temperature of 200 ℃, 250 ℃, 300 ℃, 350 ℃, 400 ℃, 450 ℃, 500 ℃, 550 ℃ or 600 ℃, and a thickness of 2.0nm, 2.2nm, 2.4nm, 2.6nm, 2.8nm, 3.0nm, 3.2nm, 3.4nm, 3.6 nmnm, 3.8nm or 4.0nm, and oxygen pressure of 100Pa, 200Pa, 300Pa, 400Pa, 500Pa, 600Pa, 700Pa, 800Pa, 900Pa or 1000 Pa.
In a second aspect, the present invention provides a josephson junction obtained by the method of the first aspect, wherein the structure of the josephson junction comprises an a-plane sapphire substrate, and a lower electrode Ta layer and a Ta layer sequentially stacked on the a-plane sapphire substrate2O5A layer and an upper electrode Ta layer, the lower electrode Ta layer having a crystal orientation of Ta (110).
The crystal orientation of the lower electrode Ta layer prepared by the invention is Ta (110), and further, high-quality Ta can be prepared2O5The layer is used as an intermediate insulating layer, compared with AlO adopted by a traditional Josephson junctionxIntermediate layer, Ta obtained2O5Has higher environmental and process stability and lower dielectric loss. And the invention can be further optimized by passivation.
It should be noted that the crystal orientation of the upper electrode Ta layer is not specifically required or limited, and those skilled in the art may reasonably select the crystal orientation according to the design requirement, for example, the crystal orientation of the upper electrode Ta layer is the same as the crystal orientation of the lower electrode Ta layer, and is Ta (110).
In a third aspect, the present invention provides a josephson junction array comprising josephson junctions arranged in an array and a gap bridge structure for conducting junction electrodes, wherein the josephson junctions adopt the josephson junctions of the second aspect.
It should be noted that, according to the design requirement, the air bridge structure is reasonably selected to conduct the junction electrode, and part of the junctions can be selected to conduct.
In a fourth aspect, the present invention provides a method for preparing the josephson junction array of the third aspect, the method for preparing the josephson junction array comprising:
preparing Josephson junctions arranged in an array on the A-surface sapphire substrate, and processing a superconducting circuit pattern after passivation treatment and protection; and after passivation treatment and protection, constructing an air bridge, and conducting connection on the junction electrodes in the Josephson junction array to prepare the Josephson junction array.
The method is different from the traditional double-inclination-angle evaporation method, firstly, the preparation of a quasi-single crystal Ta (110) film is carried out based on an A-surface sapphire substrate and is used as a lower electrode, and further, the dense and stable Ta is prepared2O5A layer and an upper electrode Ta layer, and build up Ta/Ta2O5a/Ta sandwich structure, and multiple Ta/Ta layers are formed by photoetching process2O5Etching preparation of a/Ta Josephson junction, and then preparing a superconducting circuit pattern. Finally, it is possible to pass through conventional SiO2And (3) an air bridge scheme is adopted to complete the conducting preparation of a plurality of necessary Josephson junction electrodes in the Josephson junction array. In the preparation process, the surface of the device is passivated, so that the superconducting circuit structure and the Josephson junction are protected favorably. The process steps are simple, the design is reasonable, and the preparation of the high-quality superconducting qubit can be completed.
In one embodiment, the manner of air bridge construction includes: deposition of SiO on the surface of structures by low temperature Plasma Enhanced Chemical Vapor Deposition (PECVD)2A sacrificial layer covering multiple Josephson junctions, Chemical Mechanical Polishing (CMP) to SiO2And removing the sacrificial layer and ensuring the polished surface to be flat. Then, etching the superconducting circuit structure overlapped with the junction region by a photoetching process to remove SiO on the surface2Etching the junction region and the superconducting circuit structure overlapped with the junction region by an ion etching process to remove the oxide layer on the surface, depositing a metal Ta wire, and finally removing SiO2And completing the construction of the air bridge, and then protecting the exposed superconducting circuit and junction area through passivation treatment.
As a preferred embodiment of the present invention, the passivation treatment includes chemical passivation.
According to the invention, through passivation treatment, the surface of the exposed Ta layer on the inner side of the etched channel can be optimized, the thickness and compactness of an oxide layer are further increased, and a passivation protection effect is achieved. The passivation process of the Josephson junction can protect the superconductive tunneling channel in the Josephson junction.
In one embodiment, the invention achieves chemical passivation by treatment with a piranha solution consisting of concentrated H at a volume ratio of 2:12SO4And H2O2(30% mass concentration) and the soaking time is 10-20 min.
Exemplarily, there is provided a method for preparing the above josephson junction array, the method for preparing the josephson junction array specifically comprising the steps of:
the method comprises the following steps of pretreating an A-surface sapphire substrate, wherein the pretreatment step comprises the following steps:
(a) in a 900-1200 ℃ tube furnace, in the atmosphere with oxygen flux not less than 60sccm, performing high-temperature annealing on the A-surface sapphire substrate for not less than 1h to obtain a smooth substrate surface with clear atomic steps;
(b) pre-plating the back surface of the A-surface sapphire substrate obtained in the step (a) in a vacuum environment, wherein the plating film has a light-shielding effect, and is preferably made of a high-temperature-resistant and oxidation-resistant metal material, such as a titanium film with the thickness of more than or equal to 50nm, so that the temperature uniformity in the post-treatment of the substrate and the growth process of the material is ensured;
(c) in the first stage, in a high vacuum environment at 300-500 ℃, treating the A-surface sapphire substrate obtained in the step (b) for 20-40 min by using active oxygen plasma with oxygen flow less than or equal to 1sccm and radio frequency power of 80-120W, and filtering out charged ions damaging the substrate by using a filter screen in the period; and in the second stage, stopping oxygen introduction, and annealing for 20-40 min at 600-1000 ℃ in a pure high-temperature environment.
Preparing a lower electrode Ta layer: the growth temperature is 500-700 ℃, the working pressure is less than or equal to 2mTorr, the direct current power is 50-200W, the target base distance is 90-150 mm, and a lower electrode Ta layer with the thickness of 50-150 nm is grown.
Preparation of Ta2O5Layer (b): oxidizing the surface of the lower electrode Ta layer at 200-600 ℃ in an oxygen pressure atmosphere of 100-1000 Pa to generate 2-4 nm Ta2O5And (3) a layer.
Preparing an upper electrode Ta layer: the growth temperature is 300-500 ℃, the working pressure is not less than 5mTorr, the direct current power is 50-200W, the target base distance is 90-150 mm, and an upper electrode Ta layer with the thickness of 100-200 nm is grown.
Preparation of josephson junction patterns: the Josephson junction is prepared by adopting the photoetching process, namely the steps of photoresist homogenizing, exposure, development, etching, photoresist removing and the like.
Josephson junction passivation treatment: and soaking the fish in the piranha solution for passivation for 10-20 min.
Preparing a superconducting circuit structure: the superconducting circuit structure is prepared by utilizing a photoetching process.
And (3) passivating the superconducting circuit structure: and soaking the fish in the piranha solution for passivation for 10-20 min.
Constructing an air bridge: deposition of SiO on the surface of structures by low temperature Plasma Enhanced Chemical Vapor Deposition (PECVD)2A sacrificial layer covering multiple Josephson junctions, Chemical Mechanical Polishing (CMP) to SiO2And removing the sacrificial layer and ensuring the polished surface to be flat. Then, etching the superconducting circuit structure overlapped with the junction region by a photoetching process to remove SiO on the surface2Etching the junction region and the superconducting circuit structure overlapped with the junction region by an ion etching process to remove the surface oxide layer, depositing a metal Ta wire, and finally removing SiO2And completing the construction of the air bridge. And then the exposed superconducting circuit and junction area are protected by passivation treatment.
In a fifth aspect, the present invention provides a use of the josephson junction of the first aspect in the field of superconducting chips.
The recitation of numerical ranges herein includes not only the above-recited numerical values, but also any numerical values between non-recited numerical ranges, and is not intended to be exhaustive or to limit the invention to the precise numerical values encompassed within the range for brevity and clarity.
Compared with the prior art, the invention has the beneficial effects that:
(1) the method adopts the A-surface sapphire substrate to grow the Ta epitaxial film and is applied to the preparation of a superconducting chip, and based on the small lattice mismatch degree and the symmetry relationship of the substrate, a high-quality quasi-monocrystalline Ta (110) film with almost single orientation can be epitaxially grown on the A-surface sapphire substrate. In the traditional scheme, the Ta superconducting film grows by adopting the C-plane sapphire substrate, and is limited in the triple symmetry relation of the C-plane sapphire substrate, so that the grown Ta film has different orientations, grows along the vertical direction of 100 or 111, and multiple grain boundaries are inevitably presented in the film. In the research of low-temperature superconducting circuits, high-quality single crystal epitaxial Ta films are more popular. The preparation method is suitable for magnetron sputtering technology, but is not limited to the magnetron sputtering technology, and is also applied to technologies such as molecular beam epitaxy, electron beam evaporation and the like, so that the preparation method has wider equipment compatibility, and technologies similar to the molecular beam epitaxy, the electron beam evaporation and the like cannot grow a Ta (110) film on C-plane sapphire due to the substrate matching relationship.
(2) The invention is based on that the Ta (110) film surface is easy to generate oxide (Ta) with compact, stable and nearly single valence state component2O5) Based on Ta is proposed2O5As a scheme of a josephson junction intermediate insulating layer. Is different from common AlOxIntermediate layer of Ta2O5Has higher stability, can be kept stable in the atmospheric environment and the photoetching process, and can be optimized through passivation treatment. Ta2O5The intermediate layer used as the Josephson junction can be prepared by oxidation or deposition method, and can realize stability and controllable thickness compared with AlOxLower dielectric losses in the low temperature superconducting bit.
(3) The invention provides a novel Josephson junction structure, wherein the upper and lower electrodes are homogeneous Ta superconducting layers, and Ta with low dielectric loss and high stability is sandwiched between the upper and lower electrodes2O5Layer, i.e. Ta/Ta2O5A structure of/Ta. Based on Ta2O5The prepared Josephson junction can be passivated and optimized on the fresh exposed surface in the process of patterning the junction region by passivation treatment, such as selecting a piranha solution, under the condition of further removing residual glue, so that the protection of a superconducting tunneling channel in the Josephson junction is completed. The design scheme of the Josephson junction only needs to utilize the photoetching processThus, the Josephson junction with high quality, high stability and controllable area can be realized.
(4) The invention provides a preparation scheme of a novel Josephson junction array, which is different from the traditional double-inclination evaporation method, and firstly, a plurality of Ta/Ta films are carried out on the basis of a Ta film with high superconducting transition temperature2O5And preparing a/Ta Josephson junction, and then etching the superconducting circuit structure. Compatible with conventional SiO2The preparation of the empty bridge is carried out during which the benefit is obtained from the surface-dense, stable Ta2O5The passivation layer can complete the conduction preparation of a plurality of necessary Josephson junction electrodes in the array on the premise of not damaging the Josephson junctions. The preparation scheme of the Josephson junction array provided by the invention has the advantages of simple process steps and reasonable design, and can finish the preparation of high-quality superconducting qubits.
Drawings
Fig. 1 is a process flow diagram for the preparation of josephson junctions provided in example 1 of the present invention;
FIG. 2 is a flow chart of a process for preparing a superconducting circuit pattern provided in example 1 of the present invention;
FIG. 3 is a flow chart of a manufacturing process for constructing an air bridge provided in embodiment 1 of the present invention;
FIG. 4 is an atomic force microscope photograph of a lower electrode Ta layer provided in example 1 of the present invention;
FIG. 5 is an atomic force microscope photograph of a lower electrode Ta layer provided in comparative example 1 of the present invention;
FIG. 6 is an atomic force microscope photograph of a lower electrode Ta layer provided in comparative example 2 of the present invention;
FIG. 7 is an X-ray diffraction chart of a lower electrode Ta layer provided in example 1 of the present invention;
FIG. 8 is an X-ray diffraction pattern of a lower electrode Ta layer provided in comparative example 1 of the present invention;
FIG. 9 is an X-ray diffraction pattern of a lower electrode Ta layer provided in comparative example 2 of the present invention.
Wherein, the 1-A surface is a sapphire substrate; 2-lower electrode Ta layer; 3-Ta2O5A layer; 4-upper electrode Ta layer; 5-SiO2A sacrificial layer.
Detailed Description
The technical solution of the present invention is further explained by the following embodiments.
Example 1
The embodiment provides a preparation method of a josephson junction array, which specifically comprises the following steps:
the method comprises the following steps of (I) preprocessing an A-surface sapphire substrate 1, wherein the preprocessing step comprises the following steps:
(a) in a 1000 ℃ tube furnace, in the atmosphere with oxygen flux of 80sccm, performing high-temperature annealing on the A-surface sapphire substrate 1 for 2 hours to obtain a smooth substrate surface with clear atomic steps;
(b) in a vacuum environment, a titanium film with the thickness of 60nm is plated on the back surface of the A-surface sapphire substrate 1 obtained in the step (a) in advance;
(c) and (b) carrying out substrate cleaning on the A-surface sapphire substrate 1 obtained in the step (b): the first stage, in a high vacuum environment at 400 ℃, adopting active oxygen plasma with oxygen flow of 0.5sccm and radio frequency power of 100W for treatment for 30min, wherein in the period, a filter screen filters out charged ions which damage a substrate; and in the second stage, stopping oxygen introduction, and annealing for 30min at the pure high temperature of 800 ℃.
(II) As shown in FIG. 1, preparing a lower electrode Ta layer 2: the growth temperature is 600 ℃, the working pressure is 1.5mTorr, the direct current power is 200W, the target base distance is 90mm, and the lower electrode Ta layer 2 with the thickness of 100nm is grown.
(III) preparation of Ta2O5Layer 3: oxidizing the surface of the lower electrode Ta layer 2 at 400 ℃ in an oxygen pressure atmosphere of 500Pa to form 3nm of Ta2O5Layer 3.
(IV) preparation of an upper electrode Ta layer 4: the growth temperature is 400 ℃, the working pressure is 15mTorr, the direct current power is 200W, the target base distance is 90mm, and the upper electrode Ta layer 4 with the thickness of 150nm is grown.
(V) processing the Josephson junction pattern as shown in FIG. 1: the method comprises the steps of carrying out organic cleaning on the whole structure by using acetone and isopropanol, then carrying out deionized water washing to ensure that the surface of the whole structure is clean and has no organic residues, carrying out a photoetching process after drying by using nitrogen, wherein the photoetching step comprises the steps of firstly heating a hot plate to remove water vapor, then carrying out glue homogenizing treatment, and then carrying out the working procedures of prebaking, exposing, developing, hardening, etching, removing glue and the like to prepare the Josephson junction.
(vi) josephson junction passivation treatment: soaking with piranha solution for 20min, and optimizing Ta (110)/Ta while further removing residual gum2O5The newly exposed surface in the structure of the/Ta (110) three-layer film further increases the thickness and compactness of an oxide layer, plays roles of passivation and optimization and finishes the protection of a superconducting tunneling channel in a Josephson junction.
(VII) As shown in FIG. 2, the superconducting circuit structure is prepared: forming a pattern of the superconducting circuit structure by a photolithography process in which the Josephson junction pattern is protected by a photoresist, the step being performed by Ta2O5Compared with AlOxHas high stability in the photoetching process and can not generate failure.
(VIII) structural passivation of the superconducting circuit: soaking for 20min by piranha solution, further removing residual glue, optimizing the surface of the Ta (110) film on the inner side of the channel in the structure, further increasing the thickness and compactness of an oxide layer in a new exposed area, and completing passivation.
(IX) As shown in FIG. 3, the air bridge is built up: deposition of SiO on the surface of structures by low temperature Plasma Enhanced Chemical Vapor Deposition (PECVD)2Sacrificial layer 5 of SiO2The sacrificial layer 5 is required to cover multiple josephson junctions and polished to SiO at the josephson junction region2Removing the sacrificial layer 5, and etching the superconducting circuit structure overlapped with the junction region by photoetching process to remove SiO on the surface2Etching the junction region and the superconducting circuit structure overlapped with the junction region by an ion etching process to remove the surface oxide layer, depositing a metal Ta wire, and finally removing SiO2And completing the construction of an air bridge between the junction and the superconducting circuit.
(X) soaking the Johnson fish in the piranha solution for 20min again, passivating the fresh exposed surface on the inner side of the air bridge, and finally completing passivation protection of the Josephson junction array.
Example 2
The embodiment provides a preparation method of a josephson junction array, which specifically comprises the following steps:
the method comprises the following steps of (I) preprocessing an A-surface sapphire substrate 1, wherein the preprocessing step comprises the following steps:
(a) in a 900 ℃ tube furnace, in the atmosphere with oxygen flux of 60sccm, performing high-temperature annealing on the A-surface sapphire substrate 1 for 4 hours to obtain a smooth substrate surface with clear atomic steps;
(b) in a vacuum environment, a titanium film with the thickness of 50nm is plated on the back surface of the A-surface sapphire substrate 1 obtained in the step (a) in advance;
(c) and (b) carrying out substrate cleaning on the A-surface sapphire substrate 1 obtained in the step (b): the first stage, in a high vacuum environment at 300 ℃, adopting active oxygen plasma with oxygen flow of 0.2sccm and radio frequency power of 80W for treatment for 40min, wherein in the period, a filter screen filters out charged ions which damage a substrate; and in the second stage, stopping oxygen introduction, and annealing for 40min at 600 ℃ in a pure high-temperature environment.
(II) As shown in FIG. 1, preparing a lower electrode Ta layer 2: the growth temperature is 500 ℃, the working pressure is 1mTorr, the direct current power is 50W, the target base distance is 150mm, and the lower electrode Ta layer 2 with the thickness of 50nm is grown.
(III) preparation of Ta2O5Layer 3: oxidizing the surface of the lower electrode Ta layer 2 at 200 ℃ in an oxygen pressure atmosphere of 100Pa to form 2nm of Ta2O5Layer 3.
(IV) preparation of an upper electrode Ta layer 4: the growth temperature is 300 ℃, the working pressure is 5mTorr, the direct current power is 50W, the target base distance is 150mm, and the upper electrode Ta layer 4 with the thickness of 100nm is grown.
(V) processing the Josephson junction pattern as shown in FIG. 1: the method comprises the steps of carrying out organic cleaning on the whole structure by using acetone and isopropanol, then carrying out deionized water washing to ensure that the surface of the whole structure is clean and has no organic residues, carrying out a photoetching process after drying by using nitrogen, wherein the photoetching step comprises the steps of firstly heating a hot plate to remove water vapor, then carrying out glue homogenizing treatment, and then carrying out the working procedures of prebaking, exposing, developing, hardening, etching, removing glue and the like to prepare the Josephson junction.
(vi) josephson junction passivation treatment: soaking with piranha solution for 15min, and optimizing Ta (110)/Ta while further removing residual gum2O5The newly exposed surface in the structure of the/Ta (110) three-layer film further increases the thickness and compactness of an oxide layer, plays roles of passivation and optimization and finishes the protection of a superconducting tunneling channel in a Josephson junction.
(VII) As shown in FIG. 2, the superconducting circuit structure is prepared: forming a pattern of the superconducting circuit structure by a photolithography process in which the Josephson junction pattern is protected by a photoresist, the step being performed by Ta2O5Compared with AlOxHas high stability in the photoetching process and can not generate failure.
(VIII) structural passivation of the superconducting circuit: soaking for 15min by using piranha solution, further removing residual glue, optimizing the surface of a Ta (110) film which is freshly exposed on the inner side of a channel in the structure, further increasing the thickness and compactness of an oxide layer in a newly exposed area, and finishing passivation.
(IX) As shown in FIG. 3, the air bridge is built up: deposition of SiO on the surface of structures by low temperature Plasma Enhanced Chemical Vapor Deposition (PECVD)2Sacrificial layer 5 of SiO2The sacrificial layer 5 is required to cover multiple josephson junctions and polished to SiO at the josephson junction region2Removing the sacrificial layer 5, and etching the superconducting circuit structure overlapped with the junction region by photoetching process to remove SiO on the surface2Etching the junction region and the superconducting circuit structure overlapped with the junction region by an ion etching process to remove the surface oxide layer, depositing a metal Ta wire, and finally removing SiO2And completing the construction of an air bridge between the junction and the superconducting circuit.
(X) soaking the Johnson fish in the piranha solution for 15min again, passivating the fresh exposed surface on the inner side of the air bridge, and finally completing passivation protection of the Josephson junction array.
Example 3
The embodiment provides a preparation method of a josephson junction array, which specifically comprises the following steps:
the method comprises the following steps of (I) preprocessing an A-surface sapphire substrate 1, wherein the preprocessing step comprises the following steps:
(a) in a 1200 ℃ tube furnace, in the atmosphere with oxygen flux of 100sccm, performing high-temperature annealing on the A-surface sapphire substrate 1 for 1h to obtain a smooth substrate surface with clear atomic steps;
(b) in a vacuum environment, coating a titanium film with the thickness of 80nm on the back surface of the A-surface sapphire substrate 1 obtained in the step (a) in advance;
(c) and (b) carrying out substrate cleaning on the A-surface sapphire substrate 1 obtained in the step (b): the first stage, in a high vacuum environment at 500 ℃, adopting oxygen plasma with oxygen flow of 1.0sccm and radio frequency power of 120W for treatment for 20min, wherein in the period, a filter screen filters out charged ions which damage a substrate; and in the second stage, stopping oxygen introduction, and carrying out annealing treatment for 20min in a pure high-temperature environment at 1000 ℃.
(II) As shown in FIG. 1, preparing a lower electrode Ta layer 2: the growth temperature is 700 ℃, the working pressure is 2mTorr, the direct current power is 120W, the target base distance is 120mm, and the lower electrode Ta layer 2 with the thickness of 150nm is grown.
(III) preparation of Ta2O5Layer 3: oxidizing the surface of the lower electrode Ta layer 2 at 600 ℃ in an oxygen pressure atmosphere of 1000Pa to form 4nm of Ta2O5Layer 3.
(IV) preparation of an upper electrode Ta layer 4: the growth temperature is 500 ℃, the working pressure is 20mTorr, the direct current power is 120W, the target base distance is 120mm, and the upper electrode Ta layer 4 with the thickness of 200nm is grown.
(V) processing the Josephson junction pattern as shown in FIG. 1: the method comprises the steps of carrying out organic cleaning on the whole structure by using acetone and isopropanol, then carrying out deionized water washing to ensure that the surface of the whole structure is clean and has no organic residues, carrying out a photoetching process after drying by using nitrogen, wherein the photoetching step comprises the steps of firstly heating a hot plate to remove water vapor, then carrying out glue homogenizing treatment, and then carrying out the working procedures of prebaking, exposing, developing, hardening, etching, removing glue and the like to prepare the Josephson junction.
(vi) josephson junction passivation treatment: soaking the fish in piranha solutionConsidering 10min, further removing residual glue and optimizing Ta (110)/Ta2O5The newly exposed surface in the structure of the/Ta (110) three-layer film further increases the thickness and compactness of an oxide layer, plays roles of passivation and optimization and finishes the protection of a superconducting tunneling channel in a Josephson junction.
(VII) As shown in FIG. 2, the superconducting circuit structure is prepared: forming a pattern of the superconducting circuit structure by a photolithography process in which the Josephson junction pattern is protected by a photoresist, the step being performed by Ta2O5Compared with AlOxHas high stability in the photoetching process and can not generate failure.
(VIII) structural passivation of the superconducting circuit: soaking for 10min by piranha solution, further removing residual glue, optimizing the surface of the Ta (110) film on the inner side of the channel in the structure, further increasing the thickness and compactness of an oxide layer in a new exposed area, and completing passivation.
(IX) As shown in FIG. 3, the air bridge is built up: deposition of SiO on the surface of structures by low temperature Plasma Enhanced Chemical Vapor Deposition (PECVD)2Sacrificial layer 5 of SiO2The sacrificial layer 5 is required to cover multiple josephson junctions and polished to SiO at the josephson junction region2Removing the sacrificial layer 5, and etching the superconducting circuit structure overlapped with the junction region by photoetching process to remove SiO on the surface2Etching the junction region and the superconducting circuit structure overlapped with the junction region by an ion etching process to remove the surface oxide layer, depositing a metal Ta wire, and finally removing SiO2And completing the construction of an air bridge between the junction and the superconducting circuit.
(X) soaking the Johnson fish in the piranha solution for 10min again, passivating the fresh exposed surface on the inner side of the air bridge, and finally completing passivation protection of the Josephson junction array.
Comparative example 1
This comparative example provides a method for manufacturing a josephson junction array, which is different from example 1 in that the a-plane sapphire substrate 1 is replaced with a C-plane sapphire substrate, and the remaining operations and steps are exactly the same as example 1.
Comparative example 2
This comparative example provides a method of manufacturing a josephson junction array, which is different from example 1 in that the a-plane sapphire substrate 1 is replaced with a C-plane sapphire substrate, and the method of manufacturing the lower electrode Ta layer 2 in this comparative example is: the growth temperature is 400 ℃, the working pressure is 15mTorr, the direct current power is 200W, the target base distance is 90mm, and the lower electrode Ta layer 2 with the thickness of 100nm is grown. The remaining operations and steps were exactly the same as in example 1.
The lower electrode Ta layer 2 prepared in examples 1 to 3 exhibited nearly single-orientation growth, and the film surface was flat.
The results of the atomic force microscopy tests of example 1, comparative example 1 and comparative example 2 are shown in fig. 4, fig. 5 and fig. 6, respectively, and the X-ray diffraction patterns of example 1, comparative example 1 and comparative example 2 are shown in fig. 7, fig. 8 and fig. 9. As can be seen, as shown in FIG. 4, the lower electrode Ta layer 2 (A-Al) in example 12O3Ta, i.e. Ta grown on a-plane sapphire substrate) exhibits nearly single-orientation growth with a flat film surface, and fig. 7 shows the corresponding X-ray diffraction pattern, with a high-quality (110) preferred-orientation growth of the Ta film. And the lower electrode Ta layer (C-Al) in comparative example 12O3Ta, i.e., Ta grows on C-plane sapphire substrate), because of the orientation limitation of the crystal plane of the substrate itself and the reason of high-temperature growth, the Ta film grows epitaxially along the C-plane substrate orientation, as is apparent from fig. 5, the Ta film in comparative example 1 shows a typical triple growth direction, and the X-ray diffraction result of comparative example 1 further confirms that the morphology result shown in fig. 5 is a Ta (111) phase structure (fig. 8), i.e., the Ta (110) phase structure cannot grow by using the C-plane sapphire substrate in comparative example 1; FIG. 6 shows a Ta layer (C-Al) of a lower electrode grown in comparative example 2 under severer growth process conditions than in example 12O3Ta, i.e., Ta grown on a C-plane sapphire substrate), the Ta (110) film surface exhibits a disordered orientation distribution due to the limited relation of the triple symmetry of the C-plane sapphire substrate itself, and often accompanies a mixed phase structure of Ta (110) and Ta (111) (fig. 9).
From the above examples and comparative examples, it can be seen that:
(1) the method adopts the A-surface sapphire substrate to grow the Ta epitaxial film and is applied to the preparation of a superconducting chip, and based on the small lattice mismatch degree and the symmetry relationship of the substrate, a high-quality quasi-monocrystalline Ta (110) film with almost single orientation can be epitaxially grown on the A-surface sapphire substrate. In the traditional scheme, the Ta superconducting film grows by adopting the C-plane sapphire substrate, and is limited in the triple symmetry relation of the C-plane sapphire substrate, so that the grown Ta film has different orientations, grows along the vertical direction of 100 or 111, and multiple grain boundaries are inevitably presented in the film. In the research of low-temperature superconducting circuits, high-quality single crystal epitaxial Ta films are more popular. The preparation method is suitable for magnetron sputtering technology, but is not limited to the magnetron sputtering technology, and is also applied to technologies such as molecular beam epitaxy, electron beam evaporation and the like, so that the preparation method has wider equipment compatibility, and technologies similar to the molecular beam epitaxy, the electron beam evaporation and the like cannot grow a Ta (110) film on C-plane sapphire due to the substrate matching relationship.
(2) The invention is based on that the Ta (110) film surface is easy to generate oxide (Ta) with compact, stable and nearly single valence state component2O5) Based on Ta is proposed2O5As a scheme of a josephson junction intermediate insulating layer. Is different from common AlOxIntermediate layer of Ta2O5Has higher stability, can be kept stable in the atmospheric environment and the photoetching process, and can be optimized through passivation treatment. Ta2O5The intermediate layer used as the Josephson junction can be prepared by oxidation or deposition method, and can realize stability and controllable thickness compared with AlOxLower dielectric losses in the low temperature superconducting bit.
(3) The invention provides a novel Josephson junction structure, wherein the upper and lower electrodes are homogeneous Ta superconducting layers, and Ta with low dielectric loss and high stability is sandwiched between the upper and lower electrodes2O5Layer, i.e. Ta/Ta2O5A structure of/Ta. Based on Ta2O5The Josephson junctions prepared may be treated by passivation, e.g. by selectionThe piranha solution can perform passivation optimization on a fresh exposed surface in the process of patterning a junction region under the condition of further removing residual glue, so that the protection of a superconducting tunneling channel in a Josephson junction is completed. The design scheme of the Josephson junction provided by the invention can realize the Josephson junction with high quality, high stability and controllable area by only utilizing a photoetching process.
(4) The invention provides a preparation scheme of a novel Josephson junction array, which is different from the traditional double-inclination evaporation method, and firstly, a plurality of Ta/Ta films are carried out on the basis of a Ta film with high superconducting transition temperature2O5And preparing a/Ta Josephson junction, and then etching the superconducting circuit structure. Compatible with conventional SiO2The preparation of the empty bridge is carried out during which the benefit is obtained from the surface-dense, stable Ta2O5The passivation layer can complete the conduction preparation of a plurality of necessary Josephson junction electrodes in the array on the premise of not damaging the Josephson junctions. The preparation scheme of the Josephson junction array provided by the invention has the advantages of simple process steps and reasonable design, and can finish the preparation of high-quality superconducting qubits.
The applicant declares that the above description is only a specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and it should be understood by those skilled in the art that any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are within the scope and disclosure of the present invention.

Claims (10)

1. A method of preparing a josephson junction, comprising:
preparing a lower electrode Ta layer on the A-surface sapphire substrate, and sequentially preparing Ta on the lower electrode Ta layer2O5And processing the Josephson junction graph to obtain the Josephson junction.
2. The method of claim 1, wherein the A-plane sapphire substrate is pretreated, and the pretreatment comprises substrate surface atomic step treatment, back surface pre-coating and active oxygen assisted surface cleaning which are sequentially carried out.
3. The method of claim 1, wherein the Ta layer of the lower electrode and the Ta layer of the upper electrode are formed by a deposition process;
said Ta2O5The layer may be formed by oxidation or deposition.
4. The method of preparing a josephson junction according to claim 3, wherein the deposition method comprises one or a combination of at least two of magnetron sputtering, molecular beam epitaxy or electron beam evaporation;
the lower electrode Ta layer and the upper electrode Ta layer are prepared in the same or different modes.
5. The method of preparing a josephson junction according to claim 3, wherein the oxidation process comprises a quasi-in-situ high temperature thermal oxidation process or a low temperature wet oxidation process.
6. A Josephson junction obtained by the method of manufacturing a Josephson junction according to any one of claims 1 to 5, wherein the structure of the Josephson junction comprises an A-plane sapphire substrate on which a lower electrode Ta layer and Ta layer are sequentially formed2O5A layer and an upper electrode Ta layer, the lower electrode Ta layer having a crystal orientation of Ta (110).
7. A Josephson junction array comprising Josephson junctions arranged in an array and a gap bridge structure for conducting junction electrodes, the Josephson junctions employing the Josephson junctions of claim 6.
8. A method of making the Josephson junction array of claim 7, comprising:
preparing Josephson junctions arranged in an array on the A-surface sapphire substrate, and processing a superconducting circuit pattern after passivation treatment and protection; and (4) building an air bridge after passivation treatment and protection, and conducting the junction electrode of the Josephson junction to prepare the Josephson junction array.
9. The method of claim 8, wherein the passivation process comprises chemical passivation.
10. Use of the josephson junction according to claim 6 in the field of superconducting chips.
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