CN113921527A

CN113921527A - Three-dimensional memory manufacturing method and three-dimensional memory

Info

Publication number: CN113921527A
Application number: CN202111212226.4A
Authority: CN
Inventors: 吴林春; 杨永刚; 周文犀
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-03-10
Filing date: 2020-03-10
Publication date: 2022-01-11
Also published as: CN111326522B; CN111326522A

Abstract

The invention provides a three-dimensional memory manufacturing method and a three-dimensional memory, wherein the method comprises the following steps: providing a substrate and forming a sacrificial layer, a first material layer and an etching stop layer on the substrate; forming a stack structure on the etching stop layer, wherein the first material layer, the second material layer and the etching stop layer are made of different materials; forming a second structure hole penetrating through the stack structure, wherein the second structure hole extends to the etching stop layer; removing the part of the etching stop layer at the bottom of the second structure hole; forming a channel hole including a second structure hole and extending into the substrate; a channel structure is formed in the channel hole. The etching stop layer is arranged in the stack structure of the three-dimensional memory and can be used as a stop layer for etching the second structure hole, and the position of the etching stop layer in the stack structure is determined, so that the bottom of the channel hole can be exactly positioned in the substrate, and the substrate cannot be perforated.

Description

Three-dimensional memory manufacturing method and three-dimensional memory

The invention is a divisional application with the application number of 202010161888.2, the application date of 2020, 03 and 10, and the title of the invention is "manufacturing method of three-dimensional memory and three-dimensional memory".

Technical Field

The present invention relates to a three-dimensional memory technology, and more particularly, to a three-dimensional memory and a method for manufacturing the same.

Background

With the rapid development of technologies such as big data, cloud computing, internet of things and the like, the requirements on the integration level and the storage density of the memory are also improved, and the traditional two-dimensional plane memory is difficult to meet the actual requirements and is gradually replaced by a three-dimensional memory.

In the related art, the three-dimensional memory comprises a substrate and a stack structure stacked on the substrate, wherein a channel hole penetrating through the substrate and a gate seam are arranged in the stack structure, a channel structure is arranged in the channel hole, and a common source contact is arranged in the gate seam; and the channel layer of the channel structure can be exposed from the sidewall of the channel hole and connected to the substrate.

However, the number of layers of the stack structure is large, so that the etching difficulty of the channel hole is high, and the etching depth is difficult to control.

Disclosure of Invention

The invention provides a three-dimensional memory manufacturing method and a three-dimensional memory, which aim to overcome the problem that the etching depth of a channel hole is difficult to control in the related technology.

An embodiment of the present invention provides a three-dimensional memory, including: the semiconductor device comprises a channel structure, a substrate, a semiconductor layer and a stack structure, wherein the substrate, the semiconductor layer and the stack structure are stacked; the stack structure comprises a plurality of insulating layers and conducting layers which are alternately arranged; the channel structure penetrates through the stack structure and the semiconductor layer and extends to the substrate, and the semiconductor layer is located between the substrate and the stack structure; at least one of the conductive layers has a recess near a side surface of the channel structure.

In some optional embodiments, the channel structure has a protrusion matching the recess.

In some optional embodiments, the recess comprises a first recess; the first recess is located on the conductive layer closest to the semiconductor layer.

In some optional embodiments, the stack structure further comprises a common source contact; the common source contact penetrates through the stack structure and extends into the semiconductor layer.

In some optional embodiments, the channel structure comprises a functional layer and a channel layer stacked on top of each other; the semiconductor layer is electrically connected to the channel layer.

In some optional embodiments, the functional layer is provided with an opening, and a part of the channel layer is exposed at the opening; the semiconductor layer extends to the opening and is electrically connected to the channel layer.

In some optional embodiments, the functional layer includes a barrier layer, a storage layer, and a tunneling insulating layer stacked on each other, and the storage layer is located between the barrier layer and the tunneling insulating layer.

The invention provides a manufacturing method of a three-dimensional memory, which comprises the following steps:

providing a substrate, and forming a sacrificial layer on the substrate;

forming at least one group of first material layers and etching stop layers which are arranged in pairs on the sacrificial layer;

alternately forming a first material layer and a second material layer on the etching stop layer, and forming a stack structure, wherein the materials of the first material layer, the second material layer and the etching stop layer are different;

forming a second structure hole penetrating through the stack structure, wherein the second structure hole extends to the etching stop layer, and the bottom of the second structure hole exposes the etching stop layer;

removing the part of the etching stop layer, which is positioned at the bottom of the second structure hole, so as to form a channel hole which comprises the second structure hole and extends into the substrate;

forming a channel structure in the channel hole;

removing the sacrificial layer to form a sacrificial gap;

a semiconductor layer is formed in the sacrificial gap, the semiconductor layer being electrically connected to a channel layer of the channel structure.

In some alternative embodiments, during the formation of the second structure hole through the stack structure; and the etching rates of the first material layer and the second material layer are greater than the etching rate of the etching stop layer.

In some optional embodiments, a portion of the etch stop layer at the bottom of the second structure hole is removed by wet etching, and a recess is formed on a side of the etch stop layer close to the second structure hole.

In some optional embodiments, forming the channel structure in the channel hole comprises: a functional layer and a channel layer are formed in the channel hole overlying one another.

In some optional embodiments, forming a functional layer and a channel layer in the channel hole one on top of the other includes:

forming a barrier layer, a memory layer and a tunneling insulating layer stacked on each other in the channel hole;

forming the channel layer on the tunneling insulating layer.

In some optional embodiments, after the step of "forming a channel structure in the channel hole" and before the step of "removing the sacrificial layer to form a sacrificial gap", further comprising:

and forming a gate gap penetrating through the stack structure and the etching stop layer, wherein the gate gap extends into the sacrificial layer.

In some optional embodiments, a first structure hole is formed through the stack structure, the first structure hole extends to the etching stop layer, and the bottom of the first structure hole exposes the etching stop layer;

removing the part of the etching stop layer at the bottom of the first structural hole;

removing the sacrificial layer opposite to the bottom of the first structure hole to extend the bottom of the first structure hole further into the sacrificial layer and form the gate seam.

In some optional embodiments, removing the sacrificial layer to form the sacrificial gap between the substrate and the etch stop layer;

removing the functional layer exposed in the sacrificial gap to extend the sacrificial gap further to a surface of the channel layer.

In some optional embodiments, a common source contact is formed in the gate seam and the common source contact extends to the semiconductor layer.

In some optional embodiments, further comprising: and replacing the second material of the second material layer and the barrier material of the etching stop layer with conductive materials to form a conductive layer.

In some optional embodiments, the barrier material is aluminum oxide.

The three-dimensional memory manufacturing method and the three-dimensional memory provided by the invention have the advantages that the etching stop layer is arranged in the stack structure of the three-dimensional memory and is used as the etching stop layer of the second structure hole, the process steps of etching the second structure hole can be further divided into a plurality of process steps of removing part of the stack structure at the top of the etching stop layer, removing part of the stack structure at the bottom of the etching stop layer and extending the second structure hole to the substrate, and the etching depth in the last process step can be reduced due to the position of the etching stop layer in the stack structure, so that the processing error is reduced, and the etching precision is accurately controlled.

Drawings

The following detailed description of the present invention is provided in conjunction with the accompanying drawings, and it is to be understood that the detailed description set forth herein is merely illustrative and explanatory of the present invention and is not restrictive of the invention as claimed below.

FIG. 1 is a schematic diagram of an overall structure of a three-dimensional memory according to an embodiment of the invention;

FIGS. 2-4 are flow charts illustrating the preparation of trench holes in embodiments of the present invention;

FIG. 5 is a flow chart illustrating the fabrication of a trench structure according to an embodiment of the present invention;

FIGS. 6-8 are flow charts illustrating the preparation of a first structured pore in an embodiment of the present invention;

FIG. 9 is a flow chart illustrating the preparation of a second substrate according to an embodiment of the present invention;

FIG. 10 is a flow chart illustrating a process for fabricating a gate replacement process according to an embodiment of the present invention;

FIG. 11 is a flow chart illustrating the fabrication of a common source contact in an embodiment of the present invention;

FIG. 12 is an enlarged view of a portion of FIG. 3 at A;

FIG. 13 is an enlarged view of a portion of FIG. 7 at B;

FIG. 14 is an enlarged view of a portion of FIG. 11 at C;

FIG. 15 is a block diagram of a process flow of a three-dimensional memory according to an embodiment of the invention;

figure 16 is a block diagram of a process flow for forming the semiconductor structure of figure 15.

Description of reference numerals:

110: a first substrate;

120: a second substrate;

130: a sacrificial layer;

140: an intermediate layer;

200: a stack structure;

210: an insulating layer;

220: a conductive layer;

221: a second recess;

222: a first recess;

230: a first structural aperture;

240: a channel hole;

250: a transition layer;

251: etching the stop layer;

260: a second structural hole;

300: a common source contact;

400: a functional layer;

410: a notch;

420: a barrier layer;

430: a storage layer;

440: tunneling through the insulating layer;

500: a channel layer;

600: a channel structure.

Detailed Description

Currently, in the manufacturing process of the three-dimensional memory, in order to electrically connect the channel layer in the channel hole to the common source contact in the gate slit, it is generally selected to first dispose a sacrificial layer between the stack structure and the substrate, and etch with the gate slit so that the gate slit extends into the sacrificial layer, and then remove the sacrificial layer and the functional layer located in the sacrificial layer and expose the channel layer from the sidewall of the channel hole, and then electrically connect the sidewall of the channel layer to the common source contact by reforming the semiconductor substrate between the stack structure and the substrate.

However, the number of stacked structures is large, the etching difficulty of the gate seams is high, the etching depth is difficult to control, the substrate at the bottom of the sacrificial layer is damaged when the depth is too large, and the sacrificial layer and the functional layer cannot be removed when the depth is too small. Moreover, the etching depth is difficult to control, so that the depth of each gate seam is different at each position, and the etching uniformity is poor.

In order to solve the above problems, embodiments of the present application provide a method for manufacturing a three-dimensional memory and a three-dimensional memory, where an etch stop layer is disposed in a stack structure of the three-dimensional memory, and a process step of etching a gate slit may be further divided into a plurality of process steps of removing a part of the stack structure at the top of the etch stop layer, removing a part of the stack structure at the bottom of the etch stop layer, and extending the gate slit into a sacrificial layer.

Fig. 1 is a schematic diagram of an overall structure of a three-dimensional memory according to an embodiment of the invention. As shown in fig. 1, the present embodiment provides a three-dimensional memory, including: the first substrate 110, the second substrate 120, and the stack structure 200 are sequentially stacked.

The first substrate 110 may be made of a semiconductor material, such as, but not limited to, silicon germanium, and silicon-on-insulator (SOI). Alternatively, the first substrate 110 may be made of single crystal silicon or the like.

The second substrate 120 is formed on the first substrate 110, and the second substrate 120 may be made of a semiconductor material, such as but not limited to silicon germanium, and silicon-on-insulator (SOI). Alternatively, the second substrate 120 may be made of at least one of single crystal silicon or polycrystalline silicon.

A stack structure 200 is formed on the second substrate 120, the stack structure 200 including insulating layers 210 and conductive layers 220 alternately disposed; the thickness of the insulating layer 210 may be the same as or different from that of the conductive layer 220. Optionally, conductive layer 220 is made of a conductive material including, but not limited to, tungsten, cobalt, copper, aluminum, doped silicon, and/or silicide. The insulating layer 210 is made of an insulating material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. Of course, in some alternative embodiments, a plurality of stack structures 200 may be sequentially stacked on the second substrate 120, which may be specifically configured according to practical situations.

The stack structure 200 has a channel hole, the channel structure 600 is disposed in the channel hole, the channel hole may penetrate through the stack structure 200 and the second substrate, and the bottom of the channel hole may extend in the first substrate 110, so that the channel structure 600 is formed to penetrate through the stack structure 200 and the second substrate 120 and extend to the first substrate 110.

Alternatively, the number of the channel structures 600 may be plural, and the plural channel structures 600 are arranged in the stack structure 200.

Each channel structure 600 includes a functional layer 400 and a channel layer 500 sequentially stacked in a channel hole; in some embodiments, the channel layer 500 may be made of amorphous, polycrystalline, or single crystal silicon. The functional layer 400 includes a barrier layer 420, a memory layer 430, and a tunnel insulating layer 440, which are sequentially stacked and disposed in the channel hole. The barrier layer 420 may be made of silicon oxide, silicon nitride, a high insulation constant insulating material, or a combination thereof. The memory layer 430 may be made of silicon nitride, silicon oxynitride, silicon, or a combination thereof. The tunneling insulating layer 440 may be made of silicon oxide, silicon nitride, or a combination thereof.

In some optional embodiments, the functional layer 400 located in the second substrate 120 has a notch 410, and the notch 410 may be a ring-shaped structure surrounding the channel layer 500, and the second substrate 120 extends into the notch 410 and is connected with the channel layer 500.

In addition, a first structure hole penetrating through the stack structure 200 and extending into the second substrate 120 is further disposed on the stack structure 200, and the common source contact 300 is disposed in the first structure hole.

Alternatively, the number of the three-dimensional memory common source contacts 300 may be one or more, and the shape thereof may be various, for example, each common source contact 300 may be a cylindrical shape or an elongated shape extending in a direction perpendicular to the paper in fig. 1, or the common source contact 300 may also be other patterned shapes such as a grid shape. In some embodiments, the common source contact 300 is made of a conductive material, including but not limited to titanium, tungsten, cobalt, copper, aluminum, and/or silicide, etc., in an alternative embodiment, the common source contact 300 may include a conductive body formed of silicon and a conductive portion coated outside the conductive body, the conductive portion may be formed of titanium nitride. Further alternatively, the top of the current conductor may also be provided with a conductive contact made of metallic tungsten.

The bottom of the common source contact 300 is in contact with the second substrate 120, and the second substrate 120 is also connected with the channel layer 500, it is understood that the second substrate 120 may have a doped region to electrically connect the channel layer 500 to the common source contact 300.

The embodiment also provides a manufacturing method of the three-dimensional memory, and the method can be used for manufacturing the three-dimensional memory. Fig. 2-4 are flow charts illustrating the preparation of trench holes in embodiments of the present invention. FIG. 15 is a block diagram of a process flow of a three-dimensional memory according to an embodiment of the invention; figure 16 is a block diagram of a process flow for forming the semiconductor structure of figure 15.

Referring to fig. 2 and 15, the method for manufacturing the three-dimensional memory may start at step S10. Step S10 includes forming a semiconductor structure. The semiconductor structure may include a first substrate 110, a sacrificial layer 130, and a stack structure 200 sequentially stacked; the stack structure 200 includes insulating layers 210 and transition layers 250 alternately disposed; and at least one transition layer 250 of the transition layers 250 adjacent to the sacrificial layer 130 is an etch stop layer 251 composed of a barrier material; and a first structure hole 230 having a bottom located at the etch stop layer 251 is disposed in the stack structure 200.

It is understood that the specific manner of forming the semiconductor structure may be various, and in an alternative embodiment, referring to fig. 16, step S10 may further include:

providing a first substrate 110, and then performing step S11 to form a sacrificial layer 130 on the first substrate 110; the sacrificial layer 130 may be made using a semiconductor material such as, but not limited to, silicon germanium, silicon-on-insulator (SOI). Alternatively, the first substrate 110 may be made of single crystal silicon. The process of forming the sacrificial layer 130 may use a thin film deposition process including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD). After the sacrificial layer 130 is formed, step S12 may be performed to alternately stack the insulating layer 210 and the transition layer 250 on the sacrificial layer 130 to form the stack structure 200.

Wherein the insulating layer 210 may be deposited from a first material; the plurality of transition layers 250 in the stack structure 200 may be composed of a barrier material or a second material, i.e., at least one of the transition layers 250 may be composed of a barrier material, such transition layer 250 may be referred to as an etch stop layer 251, and the remaining transition layers 250 may be composed of a second material different from the barrier material. And the first material, the second material and the barrier material are all different kinds of materials.

For convenience of description, in the following description, when only one etching stop layer 251 is disposed in the transition layer 250, step S12 may further include:

in step S1201, the insulating layer 210 is formed on the sacrificial layer 130 so that the insulating layer 210 can be in contact with the sacrificial layer 130. The insulating layer 210 may be a silicon oxide layer formed by a thin film deposition process.

After the insulating layer 210 is formed, step S1202 may be performed to form an etch stop layer 251 on the insulating layer 210 so that the etch stop layer 251 may be in direct contact with the insulating layer 210; among them, the etch stop layer 251 may be a structure formed by a thin film deposition process or the like using a barrier material.

After forming the etch stop layer 251, step S1203 may be further performed to further alternately stack and form the remaining insulating layers 210 and the transition layers 250 on the etch stop layer 251. The remaining transition layer 250 may be a silicon nitride layer formed by a thin film deposition process.

In summary, in the stack structure 200 formed through steps S1201-S1203, one transition layer 250 closest to the sacrificial layer 130 may be an etch stop layer 251 composed of a barrier material, and the remaining transition layers 250 formed after the etch stop layer 251 are all composed of a second material.

Of course, in other embodiments of step S12, the first material and the second material may be alternately stacked to form a first sub-stacked structure, where the bottom layer and the top layer of the first sub-stacked structure are both the insulating layer 210, and then the etch stop layer 251 may be formed on the first sub-stacked structure, and then the first material and the second material may be alternately stacked on the etch stop layer 251 to form the remaining insulating layer and the transition layer. In the present embodiment, the etch stop layer 251 is formed not as the one transition layer 250 closest to the sacrificial layer 130, but as a transition layer 250 closer to the sacrificial layer 130, for example, the etch stop layer 251 may be the second, third or fourth transition layer 250 from bottom to top.

Therefore, it should be understood that "at least one transition layer 250 adjacent to the sacrificial layer 130 in the semiconductor structure is an etch stop layer 251 made of a barrier material, and a total of N transition layers 250 are formed in the stacked structure 200, and are sequentially numbered 1, 2, 3, … …, N from bottom to top. The transition layer 250 adjacent to the sacrificial layer 130 may be labeled as M, which may be greater than or equal to 1 and less than N/2. Wherein M, N is a natural number.

The method for forming the insulating layer 210 and the transition layer 250 in step S12 includes, but is not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD).

In the above description of the method for forming only one etching stop layer 251 in the stack structure 200, when a plurality of etching stop layers 251 are provided in the stack structure 200, the plurality of etching stop layers 251 may be adjacent transition layers 250, or may be formed in a structure in which other transition layers 250 are provided with an interval therebetween, or at least a part of the etching stop layers 251 are adjacent to each other, and a part of the etching stop layers 251 may be provided with an interval therebetween with transition layers 250 made of the second material.

In some embodiments, the semiconductor structure formed in step S10 further includes a channel structure 600, the channel structure 600 extends through the stack structure 200 and extends to the first substrate 110, and after the optional step S12, the channel structure 600 may be formed in the stack structure 200, and in an optional embodiment, the step of forming the channel structure 600 may further include: the fabrication flow for forming channel holes in a stacked structure as shown in fig. 2-4.

The process of forming the channel hole starts at step S13, and as shown in fig. 2, a second structure hole 260 is formed on the stack structure 200, and the second structure hole 260 stops at the bottom of the etch stop layer 251. That is, a portion of the stacked structure 200 above the etch stop layer 251 within the second structure hole 260 is removed. The method for forming the second structure holes 260 may be one or more of photolithography, dry/wet etching, or mechanical processing.

Alternatively, the second structure hole 260 may remove the insulating layer 210 and the transition layer 250 on top of the etch stop layer 251 by etching to stop the bottom of the second structure hole 260 from the etch stop layer 251.

In a possible implementation manner, since the etching stop layer 251 and the rest of the transition layer 250 are made of different materials, an etching product generated by etching the barrier material may have a significant difference from an etching product generated by etching the first material and the second material, and when the etching product of the etching barrier material is detected to be present in the etching product, the etching may be stopped, so that the bottom of the second structure hole 260 may just contact with the upper surface of the etching stop layer 251, or may be etched into the etching stop layer 251 by a small amount.

In another possible implementation, the first material constituting the insulating layer 210, and the second material constituting the remaining transition layer 250 except the etch stop layer 251, both have a high etch selectivity with respect to the barrier material. The high etch selectivity ratio means that the etch rate for removing the first material and the second material is much greater than the etch stop material, and therefore, the first material and the second material layer can be removed by etching by selecting an etchant which is difficult to etch or only etches the barrier material by a small amount, so that the bottom of the second structure hole 260 can be just in contact with the upper surface of the etch stop layer 251 or etched into the etch stop layer 251 by a small amount.

Also, the step S13 may form a plurality of second structure holes 260 at the same time, and in addition, or the step S13 may be performed a plurality of times to form a plurality of second structure holes 260 on the stack structure 200.

Step S13 may be followed by step S14 of removing the etch stop layer 251 at the bottom of the second structure hole 260 and exposing the insulating layer 210 at the bottom of the etch stop layer 251, as shown in fig. 3. That is, the step extends the bottom of the second structure hole 260 further through to the etch stop layer 251.

This step may also be processed by one or a combination of photolithography, dry/wet etching, or machining methods, etc. It is understood that this step may remove only the barrier material at the bottom of the second structure hole 260 by selecting an etchant or a process method, and may not remove or only slightly remove the insulating layer 210 at the bottom of the etch stop layer 251.

Alternatively, the barrier material may be alumina. Step S14 is specifically to remove the etching stop layer 251 located at the bottom of the second structure hole 260 by wet etching. In addition, fig. 12 is a partial enlarged view at a in fig. 3; referring to fig. 12, due to the process limitation of the wet etching, not only the barrier material is removed in the direction perpendicular to the first substrate 110, but also a portion of the barrier material is removed in the direction parallel to the first substrate 110, so that the etching stop layer 251 forms a first recess 222 at the hole wall of the second structure hole 260. It is understood that, in some embodiments, since only the etch stop layer 251 is wet etched when the channel hole 240 is etched, the first recess 222 may exist only at a position where the sidewall of the channel hole 240 is opposite to the etch stop layer 251.

Step S14 may be followed by step S15 of extending the second structure 260 hole bottom further into the first substrate 110 to form the channel hole 240, as shown in fig. 4. That is, the step may remove the remaining stack structure 200, the sacrificial layer 130 and a portion of the first substrate 110 at the bottom of the etch stop layer 251 in the second structure hole 260. The specific implementation mode can be one or more combination of photoetching, dry/wet etching or mechanical processing methods and the like.

In summary, the trench hole 240 formed in step S13-15 may penetrate through the stack structure 200 and the sacrificial layer 130 and extend into the first substrate 110.

In this embodiment, by providing the etch stop layer 251, the process step of etching the channel hole 240 may be further divided into a plurality of process steps of removing the portion of the stack structure 200 on the top of the etch stop layer 251, removing the etch stop layer 251, and removing the portion of the stack structure 200 on the bottom of the etch stop layer 251 and extending the channel hole 240 into the first substrate 110, and since the position of the etch stop layer 251 in the stack structure is determined, the depth L1 of the lower surface of the etch stop layer 251 from the bottom of the channel hole 240 is known, and L1 is necessarily smaller than the depth L2 of the entire channel hole 240, that is, the etch depth L1 in the process step of removing the portion of the stack structure 200 on the bottom of the etch stop layer 251 and extending the channel hole 240 into the first substrate 110 is smaller than the etch depth L2 of one time of etching forming the channel hole in the related art, so that the process error may be reduced, the bottom of the channel hole may be located exactly in the first substrate 110, the first substrate 110 is not perforated. Moreover, the depth of each channel hole 240 is consistent, the uniformity is good, and the uniformity of the bottom voltage is improved.

Also, as the etch stop layer 251 is closer to the sacrificial layer 130, the smaller the size of the L1, and accordingly the smaller the etching error, the better the control of the etching depth of the trench hole 240.

It can be understood that, only one etching stop layer 251 is provided to illustrate the formation manner of the second structure hole, when a plurality of etching stop layers 251 are provided, for example, 2 etching stop layers 251 are provided, the bottom of the second structure hole 260 may be stopped in the upper first etching stop layer, then the first etching stop layer at the bottom of the second structure hole 260 is removed, then a part of the stack structure between the first etching stop layer and the lower second etching stop layer is removed, the bottom of the second structure hole 260 is stopped in the second etching stop layer, and then the second etching stop layer at the bottom of the second structure hole 260 is removed; finally, the bottom of the second structure hole 260 is extended into the first substrate 110. In addition, when the number of the etch stop layers 251 is greater than 2, the process can be analogized in this way, and the detailed description is omitted here. When the plurality of etching stop layers 251 are provided, the etching depth of the second structure hole may be controlled in a stepwise manner, so that the bottom of the second structure hole 260 is stopped at any position required for design.

Step S16 may be performed after step S15, and the functional layer 400 and the channel layer 500 are sequentially stacked and formed in the channel hole 240. FIG. 5 is a flow chart illustrating the fabrication of a trench structure according to an embodiment of the present invention; referring to fig. 5, step S16 may further include: sequentially stacking a barrier layer 420, a storage layer 430 and a tunneling insulating layer 440 in the channel hole 240; then, a channel layer 500 is stacked on the tunnel insulating layer 440.

Therein, in some embodiments, the functional layer 400 is a combination of layers including, but not limited to, a barrier layer 420, a storage layer 430, and a tunneling insulation layer 440. Alternatively, the material of the tunneling insulating layer 440 may be an insulating material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. Alternatively, storage layer 430 may include a material that can be used to store charge for the NAND operation. The memory layer 430 is made of a material including, but not limited to, silicon nitride, silicon oxynitride, or a combination of silicon oxide and silicon nitride, or a combination of the above materials. Alternatively, the barrier layer 420 may be an insulating material layer, such as a silicon oxide layer or a composite layer including silicon oxide/silicon nitride/silicon oxide (ONO). Further, the barrier layer 420 may include a high-K dielectric layer (e.g., aluminum oxide). In addition, the functional layer 400 and the channel layer 500 may be prepared using a chemical vapor deposition method (CVD), a physical vapor deposition method (PVD), or an atomic layer deposition method (ALD), and other suitable methods.

It is understood that, when the wet etching is performed in step S14, the first recess 222 is filled with the trench structure in step S16 to form a protrusion because the sidewall of the trench hole 240 has the first recess 222.

FIGS. 6-8 are flow charts illustrating the preparation of a first structured pore in an embodiment of the present invention; referring to fig. 6, after forming the channel structure in the stack structure, step S17 may be further performed to form a first structure hole 230 located at the bottom of the etch stop layer 251 in the stack structure 200. That is, a portion of the stacked structure 200 above the etch stop layer 251 within the first structure hole 230 is removed. The method for forming the first structure hole 230 may be one or more of photolithography, dry/wet etching, or mechanical processing.

Alternatively, the first structure hole 230 may be etched to remove the insulating layer 210 and the transition layer 250 on top of the etch stop layer 251 to stop the bottom of the first structure hole 230 from the etch stop layer 251.

In one possible implementation, it is understood that, since the etch stop layer 251 and the rest of the transition layer 250 are made of different materials, the etching products generated by etching the barrier material may be clearly different from the etching products generated by etching the first material and the second material, and when the etching products of etching the barrier material are detected to be present in the etching products, the etching may be stopped, so that the bottom of the first structure hole 230 may just contact the upper surface of the etch stop layer 251, or may be etched into the etch stop layer 251 by a small amount.

In another possible implementation, the first material constituting the insulating layer 210, and the second material constituting the remaining transition layer 250 except the etch stop layer 251, both have a high etch selectivity with respect to the barrier material. The high etch selectivity ratio means that the etch rate for removing the first material and the second material is much higher than the etch stop material, and therefore, the first material and the second material layer can be removed by etching by selecting an etchant which is difficult to etch or only etches the barrier material by a small amount, so that the bottom of the first structure hole 230 can just contact the upper surface of the etch stop layer 251 or etch into the etch stop layer 251 by a small amount.

In addition, the step S17 may simultaneously form a plurality of first structure holes 230, or may form a plurality of first structure holes 230 on the stack structure 200 by performing the step S17 a plurality of times.

Step S17 may be followed by step S20, referring to fig. 15 in combination with fig. 7, of removing the etch stop layer 251 at the bottom of the first structural hole 230 and exposing the insulating layer 210 at the bottom of the etch stop layer 251. That is, the step extends the bottom of the first structure hole 230 further through to the etch stop layer 251.

This step may also be processed by one or a combination of photolithography, dry/wet etching, or machining methods, etc. It is understood that this step may remove only the barrier material at the bottom of the first structural hole 230 by selecting an etchant or a process method, and may not remove or only slightly remove the insulating layer 210 at the bottom of the etch stop layer 251.

Alternatively, the blocking material may be aluminum oxide, and the step S20 is to remove the etching stop layer 251 located at the bottom of the first structural hole 230 by wet etching. In addition, fig. 13 is a partial enlarged view at B in fig. 7; referring to fig. 13, due to the process limitation of the wet etching, not only the barrier material is removed in the direction perpendicular to the first substrate 110, but also a portion of the barrier material is removed in the direction parallel to the first substrate 110, so that the second recess 221 is formed at the position of the hole wall of the first structure hole 230 surrounded by the etch stop layer 251. It is understood that, in some embodiments, since only the etch stop layer 251 is wet etched when the first structure hole 230 is etched, the second recess 221 may exist only at a position where the sidewall of the channel hole 240 is opposite to the etch stop layer 251.

Step S20 may be followed by step S30 of extending the first structure holes 230 further into the sacrificial layer 130 at the hole bottoms as shown in fig. 8. That is, this step may remove the remaining stack structure 200 and a portion of the sacrificial layer 130 at the bottom of the etch stop layer 251 within the first structure hole 230. The specific implementation mode can be one or more combination of photoetching, dry/wet etching or mechanical processing methods and the like.

In summary, the first structure hole 230 formed through steps S17, S20 and S30 may penetrate through the stack structure 200 and extend into the sacrificial layer 130.

In this embodiment, by providing the etch stop layer 251, the process steps of etching the first structure hole 230 can be further divided into a plurality of process steps of removing the portion of the stack structure 200 on the top of the etch stop layer 251, removing the etch stop layer 251, and removing the portion of the stack structure 200 on the bottom of the etch stop layer 251 and extending the first structure hole 230 into the sacrificial layer 130, and because the position of the etch stop layer 251 in the stack structure is determined, the depth H1 of the lower surface of the etch stop layer 251 from the bottom of the first structure hole 230 is known, and H1 is necessarily smaller than the depth H2 of the entire first structure hole 230, that is, the etch depth H1 in the process step of removing the portion of the stack structure 200 on the bottom of the etch stop layer 251 and extending the first structure hole 230 into the sacrificial layer 130 is smaller than the etch depth H2 of the gate slit formed by one etching in the related art, so that the process error can be reduced, the bottom of the first structure hole 230 may be located in the sacrificial layer 130, and may not be too shallow or too deep, so as to avoid the problem that the first substrate 110 may be damaged due to too deep etching, and the problem that the sacrificial layer 130 and the functional layer 400 may not be removed in the subsequent process due to too small etching depth may be avoided. Moreover, the depths of the first structure holes 230 or the different positions of the bottom of each first structure hole 230 are relatively consistent, and the etching uniformity is good. Meanwhile, the process is simple without adding a new mask layer and has low cost.

Also, as the etch stop layer 251 is closer to the sacrificial layer 130, the smaller the size of H1, and accordingly the smaller the etching error, the better the control of the etching depth of the first structure hole 230.

It is understood that, only one etching stop layer 251 is provided as an example to describe the formation manner of the first structural hole, when a plurality of etching stop layers 251 are provided, for example, 2 etching stop layers 251 are provided, the bottom of the first structural hole 230 may be stopped in the upper first etching stop layer, then the first etching stop layer at the bottom of the first structural hole 230 is removed, then a part of the stack structure between the first etching stop layer and the lower second etching stop layer is removed, the bottom of the first structural hole 230 is stopped in the second etching stop layer, and then the second etching stop layer at the bottom of the first structural hole 230 is removed; finally, the bottom of the first structure hole 230 is extended to the inside of the sacrificial layer 130. In addition, when the number of the etch stop layers 251 is greater than 2, the process can be analogized in this way, and the detailed description is omitted here. When the plurality of etching stopper layers 251 are provided, the etching depth of the first structural hole may be controlled in stages, so that the bottom of the first structural hole 230 is stopped at any position required for design.

Step S30 may be followed by step S40 of removing the sacrificial layer 130 to form a sacrificial gap. In some embodiments, when the semiconductor structure formed in step S10 has the channel structure 600 therein, step S40 may specifically include: the sacrificial layer 130 and the portion of the channel structure 600 in the sacrificial layer 130 are removed to form a sacrificial gap. FIG. 9 is a flow chart illustrating the preparation of a second substrate according to an embodiment of the present invention; referring to fig. 8-9, the removed portion of the channel structure 600 in step S40 may be the functional layer 400 at a location surrounded by the sacrificial layer 130. The removing method can be one or more of photoetching, dry/wet etching or mechanical processing methods.

In some optional embodiments, step 40 may specifically further include:

in step S41, the sacrificial layer 130 is removed to form a sacrificial gap between the first substrate 110 and the stack structure 200.

In this step, the sacrificial gap is formed only in the region surrounded by the first substrate 110 and the stack structure 200, and the outer surface of the functional layer 400.

In step S42, the functional layer 400 exposed in the sacrificial gap is removed to extend the sacrificial gap further to the surface of the channel layer 500.

That is, step S42 further removes the functional layer 400 constituting the boundary of the sacrificial gap on the basis of step S41, thereby expanding the boundary of the sacrificial gap to the outer surface of the channel layer 500.

When the functional layer 400 includes the barrier layer 420, the storage layer 430, and the tunneling insulating layer 440, which are sequentially stacked, removing the functional layer 400 exposed in the sacrificial gap may further include sequentially removing the barrier layer 420, the storage layer 430, and the tunneling insulating layer 440 exposed in the sacrificial gap.

The removing method in steps S41 and S42 may be one or more of photolithography, dry/wet etching, or mechanical processing method.

It is understood that, in steps S30 and 40, only the sacrificial layer 130 and a part of the functional layer 400 are removed, and the first substrate 110 is not damaged, therefore, referring to fig. 2, in some embodiments, in order to prevent the first substrate 110 from being damaged, at least one intermediate layer 140 may be further disposed between the first substrate 110 and the sacrificial layer 130, wherein the intermediate layer 140, as a thin layer for protecting the first substrate 110, is consumed in the process of removing the sacrificial layer 130 and the functional layer 400, so that the sacrificial gap finally formed in step S40 is directly contacted with the first substrate 110, that is, the intermediate layer 140 is removed along with the sacrificial layer 130 and the functional layer 400.

The intermediate layer may be made of silicon oxide or silicon nitride. The number of the intermediate layers may be a plurality of stacked structures of, for example, silicon oxide or silicon nitride, and the thickness of each layer may be set according to the actual situation. For example, referring to fig. 8, in some alternative embodiments, the intermediate layer may include a 2-layer structure of a silicon oxide layer in contact with the first substrate 110 and a silicon nitride layer over the silicon oxide layer.

After the sacrificial gap is formed, step S50 may be performed, referring to fig. 9, in which the second substrate 120 is formed in the sacrificial gap and the bottom of the first structure hole 230 is located in the second substrate 120.

Wherein the second substrate 120 may be formed using an epitaxial process that may grow silicon outward on a position having a silicon substrate, since the sacrificial gap formed at step S40 exposes the first substrate 110 and the channel layer 500, the second substrate 120 may be formed by simultaneously growing the channel layer 500 and the first substrate 110 outward to fill the sacrificial gap.

Of course, the grown second substrate 120 may fill the space of the original sacrificial layer 130, or may overflow the space, that is, the second substrate 120 may be partially located inside the first structure hole formed in fig. 8, at this time, the second substrate 120 inside the first structure hole 230 needs to be further removed, and the hole bottom of the first structure hole 230 is extended into the second substrate 120, so as to form the structure in fig. 9.

In some embodiments, the stacked structure 200 formed in step S10 may be formed by alternately stacking an insulating material and a conductive material, such as a stack of silicon and silicon oxide.

At this time, a gate replacement process is not required, and step S60 is executed after step S50, and fig. 11 is a flowchart illustrating the preparation of the common source contact according to the embodiment of the present invention; referring to fig. 11, a common source contact 300 is formed in the first structure hole 230. This step may be performed by forming a first dielectric layer of a non-conductive material in the first structure hole 230, removing the first dielectric layer at the bottom of the first structure hole 230, extending the bottom of the first structure hole into the second substrate 120, and forming the common source contact 300 in the first structure hole 230.

Among them, the process of forming the first dielectric layer and the common source contact 300 may be a thin film deposition process including, but not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD). The method for removing the first dielectric layer may be one or more of photolithography, dry/wet etching, or mechanical processing method. The first dielectric layer is composed of a material including, but not limited to, silicon oxide, silicon nitride, or a combination thereof.

In other embodiments, the stack structure 200 formed in step S10 may be formed by alternately stacking two dielectrics.

At this time, performing step S70, namely, the gate replacement process is required, may be further included between performing steps S50 and S60. FIG. 10 is a flow chart illustrating a process for fabricating a gate replacement process according to an embodiment of the present invention; referring to fig. 9-10, the material comprising the remaining transition layer, as well as the barrier material, is replaced with a metallic material. That is, the second material and the barrier material in the transition layer 250 are all replaced by the metal material, specifically, the method may include removing all the transition layers 250 to form a conductive gap between the insulating layers 210, and then forming the conductive layer 220 made of the metal material in the conductive gap through a thin film deposition process or an electroplating process, etc. In some alternatives, when the initially formed stack structure 200 is a stack of silicon oxide and silicon nitride, the silicon nitride may be replaced with a conductive material, such as "tungsten" or the like, by a gate replacement process.

In the above-mentioned method for manufacturing a three-dimensional memory, in the step of forming the semiconductor structure, the channel hole 240 and the first structure hole 230 are formed in the order of forming the channel hole 240 and the channel structure 600 and then forming the first structure hole 230, and in some alternative embodiments, the first structure hole 230 and then forming the channel hole 240 and the channel structure 600 may be formed, or the first structure hole 230 and the channel hole 240 may be formed at the same time and then forming the channel structure 600. And can be set according to actual conditions.

In some optional embodiments, the three-dimensional memory manufactured based on the above method may further have the following features.

FIG. 14 is an enlarged view of a portion of FIG. 11 at C; referring to fig. 12 and 14, since the etching stop layer 251 is removed by wet etching, so that the hole wall of the channel hole 240 has the first recess 222 at the position where the etching stop layer 251 is located, the channel structure 600 formed in the channel hole 240 in step S16 has a protrusion filled in the first recess 222, so that the finally formed three-dimensional memory is formed with the first recess 222 at the position of the hole wall of the channel hole 240 surrounded by the conductive layer 220. The conductive layer 220 is a conductive layer 220 replaced with a barrier material.

Therefore, when the stack structure formed in step S10 has at least one etching stop layer 251, the three-dimensional memory finally formed has a first recess 222 formed at a position of the hole wall of the trench hole 240 surrounded by the at least one conductive layer 220, and the trench structure has a protrusion filled in the first recess 222.

In an alternative mode, when one of the transition layers 250 closest to the first substrate 110 in the stack structure 200 formed in step S10 is used as the etching stop layer 251, the first recess 222 is formed at a position closest to the wall of the trench hole 240 surrounded by one of the conductive layers 220 of the second substrate 120 in the finally formed three-dimensional memory.

It is to be understood that although the second recess 221 is also present on the wall of the first structure hole 230 during the formation of the first structure hole 230, as shown in fig. 13, after the step S70 is performed to replace the material constituting the remaining transition layer 250 and the barrier material with the metal material, the second recess 221 is filled with the metal material, so that the finally formed common source contact 300 may not have a protrusion corresponding to the original etch stop layer 251 in the first structure hole 230.

In the description of the present invention, it is to be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; may be mechanically coupled, may be electrically coupled or may be in communication with each other; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

In the description above, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A three-dimensional memory, comprising: the semiconductor device comprises a channel structure, a substrate, a semiconductor layer and a stack structure, wherein the substrate, the semiconductor layer and the stack structure are stacked;

the stack structure comprises a plurality of insulating layers and conducting layers which are alternately arranged;

the channel structure penetrates through the stack structure and the semiconductor layer and extends to the substrate, and the semiconductor layer is located between the substrate and the stack structure;

at least one of the conductive layers has a recess near a side surface of the channel structure.

2. The three-dimensional memory according to claim 1, wherein the channel structure has a protrusion matching the recess.

3. The three-dimensional memory according to claim 1, wherein the recess comprises a first recess;

the first recess is located on the conductive layer closest to the semiconductor layer.

4. The three-dimensional memory according to claim 1, wherein the stack structure further comprises a common source contact;

the common source contact penetrates through the stack structure and extends into the semiconductor layer.

5. The three-dimensional memory according to claim 1,

the channel structure comprises a functional layer and a channel layer which are overlapped with each other;

the semiconductor layer is electrically connected to the channel layer.

6. The three-dimensional memory according to claim 5, wherein the functional layer is provided with an opening, and a portion of the channel layer is exposed at the opening;

the semiconductor layer extends to the opening and is electrically connected to the channel layer.

7. The three-dimensional memory according to claim 5, wherein the functional layer comprises a barrier layer, a storage layer, and a tunneling insulating layer stacked on each other, and the storage layer is located between the barrier layer and the tunneling insulating layer.

8. A method for manufacturing a three-dimensional memory is characterized by comprising the following steps:

providing a substrate, and forming a sacrificial layer on the substrate;

forming a channel structure in the channel hole;

removing the sacrificial layer to form a sacrificial gap;

9. The method of claim 8, wherein during the forming of the second structure hole through the stack structure;

and the etching rates of the first material layer and the second material layer are greater than the etching rate of the etching stop layer.

10. The method of manufacturing a three-dimensional memory according to claim 8,

and removing the part of the etching stop layer positioned at the bottom of the second structure hole by adopting wet etching, wherein a recess is formed at one side of the etching stop layer close to the second structure hole.

11. The method of claim 8, wherein forming a channel structure in the channel hole comprises:

a functional layer and a channel layer are formed in the channel hole to overlap each other.

12. The method of claim 11, wherein forming a functional layer and a channel layer in the channel hole overlying one another comprises:

forming the channel layer on the tunneling insulating layer.

13. The method of claim 11, further comprising, after the step of forming a channel structure in the channel hole and before the step of removing the sacrificial layer to form a sacrificial gap:

14. The method of manufacturing a three-dimensional memory according to claim 13,

forming a first structure hole penetrating through the stack structure, wherein the first structure hole extends to the etching stop layer, and the etching stop layer is exposed at the bottom of the first structure hole;

15. The method of manufacturing a three-dimensional memory according to claim 14,

removing the sacrificial layer to form the sacrificial gap between the substrate and the etch stop layer;

16. The method of manufacturing a three-dimensional memory according to claim 15,

a common source contact is formed in the gate seam and extends to the semiconductor layer.

17. The three-dimensional memory manufacturing method according to any one of claims 8 to 16, further comprising:

and replacing the second material of the second material layer and the barrier material of the etching stop layer with conductive materials to form a conductive layer.

18. The method of claim 17, wherein the barrier material is aluminum oxide.