CN113921428A - Classification packaging method for wafer multi-level chips - Google Patents

Classification packaging method for wafer multi-level chips Download PDF

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Publication number
CN113921428A
CN113921428A CN202111176439.6A CN202111176439A CN113921428A CN 113921428 A CN113921428 A CN 113921428A CN 202111176439 A CN202111176439 A CN 202111176439A CN 113921428 A CN113921428 A CN 113921428A
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chip
chips
substrate
grade
different
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刘传喜
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Payton Technology Shenzhen Co ltd
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Payton Technology Shenzhen Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67294—Apparatus for monitoring, sorting or marking using identification means, e.g. labels on substrates or labels on containers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K17/00—Methods or arrangements for effecting co-operative working between equipments covered by two or more of main groups G06K1/00 - G06K15/00, e.g. automatic card files incorporating conveying and reading operations
    • G06K17/0022—Methods or arrangements for effecting co-operative working between equipments covered by two or more of main groups G06K1/00 - G06K15/00, e.g. automatic card files incorporating conveying and reading operations arrangements or provisions for transferring data to distant stations, e.g. from a sensing device
    • G06K17/0025—Methods or arrangements for effecting co-operative working between equipments covered by two or more of main groups G06K1/00 - G06K15/00, e.g. automatic card files incorporating conveying and reading operations arrangements or provisions for transferring data to distant stations, e.g. from a sensing device the arrangement consisting of a wireless interrogation device in combination with a device for optically marking the record carrier
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q50/00—Information and communication technology [ICT] specially adapted for implementation of business processes of specific business sectors, e.g. utilities or tourism
    • G06Q50/04—Manufacturing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67271—Sorting devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67276—Production flow monitoring, e.g. for increasing throughput
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/30—Computing systems specially adapted for manufacturing

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

The invention discloses a classification packaging method for wafer multi-level chips, which belongs to the field of wafers and comprises the following steps: the method comprises the following steps: testing the wafer, grading the chip, generating a distribution graph, and simultaneously engraving corresponding two-dimensional codes on the substrate; step two: producing chips of different grades by using a work order; step three: and putting the base plate into a chip mounting station, carrying out chip mounting operation on all chips, recording the grade of each product of the base plate corresponding to the chip during the operation, and generating a base plate map. The chip is classified by applying the two-dimensional code tracking system and the classifier, the chip is moved from the chip mounting station to the packaging station, the chip mounting machine is packaged, the use efficiency of the chip mounting machine is greatly improved, meanwhile, the loss of materials such as a substrate (PCB) can be reduced, and the production cost is reduced.

Description

Classification packaging method for wafer multi-level chips
Technical Field
The invention relates to the technical field of wafers, in particular to a classification packaging method for wafer multi-level chips.
Background
After the wafer production is completed, a wafer test (CP test for short) is performed, and according to different test results, the chips are divided into multiple levels and transmitted to a packaging factory in the form of a wafer map (wafer mapping). When packaging, customers can require that chips of different grades must be packaged and shipped separately, and 2. the chip packaging process of different grades is consistent, but in order to separate the chips of different grades, the chips need to be produced according to the different grades of the chips in a Die Bonding station. In actual production, a wafer is produced for multiple times, the high-level chip accounts for more than 80%, the low-level chip accounts for 20%, and the low-level chip accounts for about 5% in multiple different levels. When producing low-grade chips, the machine efficiency is much lower than that of high-grade chips because of the small number. The packaging cost is increased dramatically. This mode of production is not suitable for mass production from the point of view of efficiency.
Disclosure of Invention
The invention aims to solve the defects in the prior art and provides a classification packaging method for wafer multi-level chips.
In order to achieve the purpose, the invention adopts the following technical scheme:
a classification packaging method for wafer multi-level chips comprises the following steps:
the method comprises the following steps: testing the wafer, grading the chip, generating a distribution graph, and simultaneously engraving corresponding two-dimensional codes on the substrate;
step two: producing chips of different grades by using a work order;
step three: putting the base plate into a chip mounting work station, carrying out chip mounting operation on all chips, recording the grade of each product of the base plate corresponding to the chip during the operation, and generating a base plate map;
step four: putting the substrate map into a lettering work station, and lettering different character numbers according to different chip grades corresponding to the substrate map in the step so as to distinguish different chip grades;
step five: classifying different chips by using a classifier according to different lettering contents;
step six: carrying out appearance detection on the classified chips of different grades, and packaging;
step seven: and after the packaging is finished, delivering the product.
Further, the process of the patch station comprises the following steps:
after the substrate is fed, reading the two-dimensional code of the substrate to obtain a distribution map of the corresponding grade chip;
carrying out surface mounting on the substrate and the wafer chip, and recording the chip grade of the surface mounting;
corresponding the chip grade to the distribution diagram, and producing a substrate map, wherein each grade of chip is displayed on the substrate map;
and uploading the substrate map data to a server to finish the patch mounting.
Further, the process of the lettering work station comprises the following steps:
after the substrate is fed, reading the two-dimensional code of the substrate, and acquiring the grade information of the chip from a server;
numbering different batch number contents and characters of different grade chips according to the distribution mode of a substrate map;
and completing lettering.
Further, the appearance detection and classification process comprises the following steps:
feeding the chip subjected to surface mounting and lettering;
identifying the grading information of the chip by using the character identification function of the optical character identification system and generating a distribution diagram;
selecting and classifying the chips according to characters corresponding to different grades;
and classifying the chips of each grade together respectively to finish classification.
Further, the lettering content used for chips of different grades: the chips in different grades correspond to the grades according to A, B, C, D letters, the grade A is the optimal chip, the grade B is the optimal chip, and the rest is done in the same way, after a distribution diagram is generated, each grade is displayed on the base map by using a corresponding color.
Further, the method is used for generating the substrate map in the third step, the substrate map is generated by a two-dimensional code tracking system, the substrate map is distributed in a rectangular table with the aspect ratio of 6:15, and the chip grade in the aspect queue is recorded.
Further, the server is a baseboard management server, and the server is in data connection with each work station.
Compared with the prior art, the invention has the beneficial effects that: the chip is classified by applying the two-dimensional code tracking system and the classifier, the chip is moved from the chip mounting station to the packaging station, the chip mounting machine is packaged, the use efficiency of the chip mounting machine is greatly improved, meanwhile, the loss of materials such as a substrate (PCB) can be reduced, and the production cost is reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention.
FIG. 1 is a flowchart illustrating a method for sorting and packaging multi-level chips on a wafer according to the present invention;
FIG. 2 is a logic diagram of a sorting and packaging method for wafer multi-level chips according to the present invention;
FIG. 3 is a flow chart of a chip mounting station of the present invention for a classified packaging method of wafer multi-level chips;
FIG. 4 is a flowchart of a lettering station of the classified packaging method for wafer multi-level chips according to the present invention;
FIG. 5 is a schematic logic diagram of a sorting machine for sorting and packaging wafer multi-level chips according to the present invention;
FIG. 6 is a flowchart illustrating the steps of the method for classifying and packaging chips of a wafer according to the present invention;
FIG. 7 is a schematic diagram of a substrate map for a classified packaging method of wafer multi-level chips according to the present invention;
fig. 8 is a schematic diagram illustrating classification of a substrate map for a classification packaging method of wafer multi-level chips according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.
Referring to fig. 1-2, a sorting and packaging method for wafer multi-level chips includes the following steps:
step S101: testing the wafer, grading the chip, generating a distribution graph, and simultaneously engraving corresponding two-dimensional codes on the substrate;
step S103: producing chips of different grades by using a work order;
step S105: putting the base plate into a chip mounting work station, carrying out chip mounting operation on all chips, recording the grade of each product of the base plate corresponding to the chip during the operation, and generating a base plate map;
step S107: putting the substrate map into a lettering work station, and lettering different character numbers according to different chip grades corresponding to the substrate map in the step so as to distinguish different chip grades;
step S109: classifying different chips by using a classifier according to different lettering contents;
step S111: carrying out appearance detection on the classified chips of different grades, and packaging;
step S113: and after the packaging is finished, delivering the product.
Referring to fig. 3, in one embodiment, the process of the placement station includes the following steps:
after the substrate is fed, reading the two-dimensional code of the substrate to obtain a distribution map of the corresponding grade chip;
carrying out surface mounting on the substrate and the wafer chip, and recording the chip grade of the surface mounting;
corresponding the chip grade to the distribution diagram, and producing a substrate map, wherein each grade of chip is displayed on the substrate map;
and uploading the substrate map data to a server to finish the patch mounting.
Referring to fig. 4, in one embodiment, the process of the lettering station includes the following steps:
after the substrate is fed, reading the two-dimensional code of the substrate, and acquiring the grade information of the chip from a server;
numbering different batch number contents and characters of different grade chips according to the distribution mode of a substrate map;
and completing lettering.
Referring to fig. 5-6, in one embodiment, the appearance detection classification process includes the following steps:
step S201, feeding the chip which is subjected to surface mounting and lettering;
step S203, identifying the grading information of the chip by using the character identification function of the optical character identification system and generating a distribution diagram;
s205, selecting and classifying the chips according to the characters corresponding to different grades;
and step S207, classifying the chips of each grade together respectively to finish classification.
Referring to fig. 7-8, in one embodiment, lettering for different levels of chips: the chips in different grades correspond to the grades according to A, B, C, D letters, the grade A is the optimal chip, the grade B is the optimal chip, and the rest is done in the same way, after a distribution diagram is generated, each grade is displayed on the base map by using a corresponding color.
Referring to fig. 7-8, in one embodiment, the method is used for generating the substrate map generated by the two-dimensional code tracking system in step S105, the substrate map is distributed in a rectangular table with an aspect ratio of 6:15, and chip levels in the vertical and horizontal queues are recorded.
In one embodiment, the server is a baseboard management server, and the server is in data connection with each work station.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.

Claims (7)

1. A classification packaging method for wafer multi-level chips is characterized by comprising the following steps:
the method comprises the following steps: testing the wafer, grading the chip, generating a distribution graph, and simultaneously engraving corresponding two-dimensional codes on the substrate;
step two: producing chips of different grades by using a work order;
step three: putting the base plate into a chip mounting work station, carrying out chip mounting operation on all chips, recording the grade of each product of the base plate corresponding to the chip during the operation, and generating a base plate map;
step four: putting the substrate map into a lettering work station, and lettering different character numbers according to different chip grades corresponding to the substrate map in the step so as to distinguish different chip grades;
step five: classifying different chips by using a classifier according to different lettering contents;
step six: carrying out appearance detection on the classified chips of different grades, and packaging;
step seven: and after the packaging is finished, delivering the product.
2. The method for classifying and packaging wafer multi-level chips as claimed in claim 1, wherein the process of the chip mounting station comprises the following steps:
after the substrate is fed, reading the two-dimensional code of the substrate to obtain a distribution map of the corresponding grade chip;
carrying out surface mounting on the substrate and the wafer chip, and recording the chip grade of the surface mounting;
corresponding the chip grade to the distribution diagram, and producing a substrate map, wherein each grade of chip is displayed on the substrate map;
and uploading the substrate map data to a server to finish the patch mounting.
3. The method as claimed in claim 1, wherein the process of the lettering station comprises the following steps:
after the substrate is fed, reading the two-dimensional code of the substrate, and acquiring the grade information of the chip from a server;
numbering different batch number contents and characters of different grade chips according to the distribution mode of a substrate map;
and completing lettering.
4. The method as claimed in claim 1, wherein the visual inspection and classification process comprises the following steps:
feeding the chip subjected to surface mounting and lettering;
identifying the grading information of the chip by using the character identification function of the optical character identification system and generating a distribution diagram;
selecting and classifying the chips according to characters corresponding to different grades;
and classifying the chips of each grade together respectively to finish classification.
5. The method as claimed in claim 3, wherein the lettering contents for different levels of chips are as follows: the chips in different grades correspond to the grades according to A, B, C, D letters, the grade A is the optimal chip, the grade B is the optimal chip, and the rest is done in the same way, after a distribution diagram is generated, each grade is displayed on the base map by using a corresponding color.
6. The method as claimed in claim 1, wherein the method is used for generating a substrate map in the third step, the substrate map is generated by a two-dimensional code tracking system, the substrate map is distributed in a rectangular table with an aspect ratio of 6:15, and the chip levels in the vertical and horizontal queues are recorded.
7. The method as claimed in claim 2, wherein the server is a baseboard management server, and the server is in data connection with each workstation.
CN202111176439.6A 2021-10-09 2021-10-09 Classification packaging method for wafer multi-level chips Pending CN113921428A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111176439.6A CN113921428A (en) 2021-10-09 2021-10-09 Classification packaging method for wafer multi-level chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111176439.6A CN113921428A (en) 2021-10-09 2021-10-09 Classification packaging method for wafer multi-level chips

Publications (1)

Publication Number Publication Date
CN113921428A true CN113921428A (en) 2022-01-11

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Application Number Title Priority Date Filing Date
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