CN113921074A

CN113921074A - Test device and method for automatically generating DDR optimal efficiency configuration parameters

Info

Publication number: CN113921074A
Application number: CN202111337312.8A
Authority: CN
Inventors: 潘毅
Original assignee: Xinhe Semiconductor Technology Wuxi Co Ltd
Current assignee: Xinhe Semiconductor Technology Wuxi Co Ltd
Priority date: 2021-11-12
Filing date: 2021-11-12
Publication date: 2022-01-11

Abstract

The invention relates to the technical field of testing, in particular to a testing device for automatically generating DDR optimal efficiency configuration parameters, which comprises a bus excitation generator, a bus monitoring analysis logic device, an efficiency analysis logic device, an address mapping configuration logic device and a DDR logic device, wherein the bus excitation generator is used for generating access excitation to the DDR logic device, the bus monitoring analysis logic device monitors the read-write behavior of the bus excitation generator to the DDR logic device in real time and outputs related monitoring data, the efficiency analysis logic device collects the data generated by the bus monitoring analysis logic device, calculates the efficiency condition and then outputs the related data, and the address mapping configuration logic device collects the data generated by the efficiency analysis logic device for analysis and determines whether to adjust the configuration parameters to restart the testing. According to the DDR address mapping configuration method, the DDR address mapping configuration parameters are automatically adjusted according to the test results until the DDR optimal efficiency configuration parameters are output, and information exchange errors between upstream and downstream test personnel of the DDR can be avoided.

Description

Test device and method for automatically generating DDR optimal efficiency configuration parameters

Technical Field

The invention relates to the technical field of testing, in particular to a testing device and a method for automatically generating DDR optimal efficiency configuration parameters.

Background

The efficiency of the DDR is one of core factors influencing the performance of the chip, and the efficiency of the DDR is related to various factors such as the working frequency, the particle model, the capacity, the software parameter configuration, the system architecture, the use scene and the like. Under the condition of hardware determination, the factor influencing the DDR efficiency to the greatest extent is equal to the software configuration parameter of the DDR, and for the same DDR, the improper software configuration may cause great performance reduction, and the expected index cannot be reached. Among all software configuration parameters of the DDR, one key configuration that affects the performance of the DDR is a configuration of address mapping, where the address mapping means that a bus address sent by an upstream master during access to the DDR is converted into a memory address of a DDR grain by a DDR controller according to a certain rule, the memory address is composed of three dimensions, namely, a Column (Column), a Row (Row), and a page (Bank), where the Column and the Row are similar to a Column and a Row of a table, and the Bank is similar to a page of the table, and the Bank of the DDR is a Logical Bank (L-Bank for short), and most DDR chips are designed with 4L-banks at present. If DDR needs to be accessed, the addressing flow is to designate the L-Bank address first, then designate the Row address, and then designate the Column address. In practice, the L-Bank address and the corresponding Row address are issued simultaneously, this command is called "Row Active" or "Row Active" (Row Active), after which the column addressing command and the specific operation command (whether read or write) are issued simultaneously, so the column addressing is generally indicated by "read/write command". According to the DDR protocol specification, the interval from "row active" to "read/write command" issue is defined as tRCD, RAS to CAS Delay (RAS to CAS Delay, RAS is the row address strobe, CAS is the column address strobe). For a read operation, after the column address is selected, a data transfer is triggered, but a certain time is still needed from the output of the memory cell to the actual presence of the memory grain I/O interface, and this time is called CL (CAS Latency, column address strobe Latency), and CL is only for a read operation, and the write operation is without Latency. In addition, if two operations are performed in a Row, a different Row (Row) needs to be opened, and according to the design principle of DDR, an existing working Row needs to be closed first, and then a new working Row needs to be opened, and this time interval is called as tRP (Row Precharge command Period). From the above description, the three parameters tRCD, CL and tRP are critical to DDR performance impact. Taking the most important operation of DDR, i.e. read operation as an example, when reading an address, there are the following three cases: 1) row and L-Bank to be addressed are free, and at this time a line valid command can be sent directly, the total time taken before data read is tRCD + CL, which is called Page Hit (PH); 2) the row to be addressed is exactly the existing working row, at which time the column addressing command can be sent directly, the total time consumption before data reading is only CL, so-called Back-to-Back (Back to Back) addressing, which is called Page Fast Hit (PFH); 3) the phenomenon that one row is already active in the L-Bank where the row to be addressed is located is called an addressing conflict, and at this time, it is necessary to precharge and close the working row and send a row valid command to the new row, and the total time consumption is tRP + tRCD + CL, and this is called a Page Miss (PM, Page Miss). As can be seen from the above analysis, the more the Page Fast Hit (PFH) is, the shorter the access DDR takes, the higher the efficiency, and the more the Page Miss (PM) is, the longer the access DDR takes, the worse the efficiency. The distribution of the three access conditions is closely related to the address distribution sent by the master, if the continuity of the [ bank, row, column ] address generated after mapping is good, and the proportion of PFH access is large, the efficiency performance of DDR will be good, otherwise, the DDR is poor. By adjusting the address mapping configuration, the probability of generating PM is reduced, and the probability of PFH and PH is increased, so that the access efficiency of DDR is improved.

However, it is a difficult problem how to obtain a proper DDR address mapping configuration parameter, and firstly, the address mapping configuration is not as standard as specified by other DDR parameters, and whether its configuration is reasonably related to the access behavior of the upstream master, and it is necessary to have a certain knowledge about both the DDR and the upstream master to be able to give a reasonable configuration. However, in reality, different persons usually take charge of the verification or test of the DDR and the upstream master, and the modules in charge of the both parties are generally unknown to each other. Obviously, there are many problems with this approach:

1) whether the obtained relatively optimal configuration is a real optimal solution or not is difficult to determine, and whether more optimal configuration exists or not can better discover the DDR performance;

2) the address access distribution provided by the master tester is not completely consistent with the actual situation, and the DDR tester gives unreasonable address mapping configuration based on inaccurate address distribution, so that the DDR efficiency is reduced;

3) every time a new address mapping configuration is changed and tried, upstream and downstream testers need to communicate again, and DDR efficiency performance is retested, contrastively analyzed, and a large amount of labor and time cost is consumed.

In summary, the above problems are often encountered in the performance test of DDR, but an effective solution is lacking.

Disclosure of Invention

The invention provides a testing device and a method for automatically generating DDR optimal efficiency configuration parameters.

In order to achieve the purpose of the invention, the test device for automatically generating DDR optimal efficiency configuration parameters comprises a bus excitation generator, a bus monitoring analysis logic device, an efficiency analysis logic device, an address mapping configuration logic device and a DDR logic device, wherein the bus excitation generator is used for generating access excitation to the DDR logic device, the bus monitoring analysis logic device monitors the read-write behavior of the bus excitation generator to the DDR logic device in real time and outputs related monitoring data, the efficiency analysis logic device collects the data generated by the bus monitoring analysis logic device, calculates the efficiency condition and then outputs the related data, and the address mapping configuration logic device collects the data generated by the efficiency analysis logic device for analysis and determines whether to adjust the configuration parameters to restart the test.

In order to achieve the purpose of the invention, a method for testing a testing device which automatically generates DDR optimal efficiency configuration parameters comprises the following steps:

1) the bus monitoring and analyzing logic device converts the bus address generated by the bus excitation generator according to the existing address mapping configuration, analyzes the conversion condition of the bus address and records the conversion condition; the bus monitoring and analyzing logic device counts the consumption time of the bus excitation generator for accessing and exciting the DDR logic device;

2) the efficiency analysis logic device calculates and counts the proportion of three accesses of PH, PFH and PM in one round of test according to the distribution condition of the conversion address output by the bus monitoring analysis logic device; the efficiency analysis logic device obtains the consumption time data output by the bus monitoring analysis logic device, and calculates the average consumption time, the maximum consumption time and the bandwidth of reading and writing in one round of test;

3) the address mapping configuration logic unit automatically generates new address mapping configuration according to the comprehensive efficiency performance output by the efficiency analysis logic unit by combining the PH, PFH and PM distribution conditions generated by the bus monitoring analysis logic unit, writes the configuration into the configuration parameters of the DDR logic unit, and automatically starts the bus excitation generator to perform a new test; and the address mapping configuration logic device automatically compares with the test result of the previous round, records the configuration parameters with better efficiency performance, and repeatedly tests until the efficiency is not obviously improved, and then exits the test cycle.

As an optimization scheme of the invention, after the efficiency analysis logic device obtains average consumption time, maximum consumption time and bandwidth indexes of reading and writing, the priority of each index is set according to specific requirements, and the comprehensive efficiency condition of DDR test in the current round is calculated:

e ═ BW, LATavr, LATmax, LATpercent equation 1

In equation 1, E represents the integrated efficiency, BW represents the bandwidth, LATavr represents the average elapsed time, LATmax represents the maximum elapsed time, and LATpercent represents the elapsed time distribution.

The invention has the positive effects that: 1) the invention can find the address mapping configuration which enables the DDR efficiency to be optimal, and solves the defect that the traditional method uses experience values;

2) the method provided by the invention can avoid the information exchange error between upstream and downstream test personnel of the DDR, the upstream test personnel can be separated from the guidance of the DDR test personnel, and the method is independently used for obtaining the optimal address mapping configuration, so that the efficiency test result is matched with the actual situation to the maximum extent;

3) the testing method provided by the invention can be operated in a full-automatic manner, is unattended, greatly saves manpower, and reduces the time wasted on efficiency analysis by the traditional method.

Drawings

The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

FIG. 1 is an overall schematic block diagram of the present invention;

FIG. 2 is a functional block diagram of bus guardian analysis logic;

FIG. 3 is a functional block diagram of efficiency analysis logic;

FIG. 4 is a functional block diagram of address mapping configuration logic.

Wherein: 1. the bus excitation generator 2, the bus monitoring analysis logic 3, the efficiency analysis logic 4, the address mapping configuration logic 5 and the DDR logic.

Detailed Description

The implementation of the invention is described in further detail below with reference to the attached drawing figures:

as shown in fig. 1, the present invention discloses a testing apparatus for automatically generating optimal DDR efficiency configuration parameters, which includes a bus excitation generator 1, a bus monitoring and analyzing logic device 2, an efficiency analyzing logic device 3, an address mapping and configuring logic device 4 and a DDR logic device 5, where the bus excitation generator 1 is configured to generate an access excitation to the DDR logic device 5, the bus monitoring and analyzing logic device 2 monitors the read-write behavior of the bus excitation generator 1 to the DDR logic device 5 in real time and outputs related monitoring data, the efficiency analyzing logic device 3 collects data generated by the bus monitoring and analyzing logic device 2 and calculates the efficiency condition and then outputs the related data, and the address mapping and configuring logic device 4 collects data generated by the efficiency analyzing logic device 3 to analyze and determine whether to adjust the configuration parameters to restart the test.

The bus excitation generator 1 is logic for generating specific access excitation to DDR, the logic can generate excitation corresponding to address distribution after a tester gives an address distribution rule, and a real master can be used for replacement;

as shown in fig. 2, the bus monitoring and analyzing logic 2 mainly implements the following functions:

1. the bus address generated by the bus excitation generator 1 is converted according to the existing address mapping configuration, and the conversion condition of each access address is analyzed and recorded. The address conversion here is to convert the bus address into the DDR actual storage address [ Bank, Row, Column ], and common address mapping manners include BRC (Bank/Row/Column) and RBC (Row/Bank/Column), assuming that the bus address is a 32-bit address Addr [31:0], and may be Bank Addr [28:27]/Row Addr [26:11]/Col Addr [10:2] after the BRC mapping, and may be Row Addr [28:13]/Bank Addr [12:11]/Col [10:2] after the RBC mapping. The two are the most common mapping methods, and in practice, the DDR controller may support more complicated mapping methods, such as Row [15:2] ═ Addr [28:15]/Col [9:8] ═ Addr [14:13]/Bank [1] ═ Addr [12]/Row [1:0] ═ Addr [11:10]/Col [7:0] ═ Addr [9:3]/Bank [0] ═ Addr [2], each of which may cause a significant change in DDR efficiency. The bus address is decomposed into [ bank, row, column ] addresses according to preset address mapping configuration, the corresponding relation is recorded, and the distribution condition of the converted address is obtained for subsequent calculation and analysis;

2. and counting the latency (latency) of each access, wherein the latency of each read and write is calculated by monitoring the time when the master sends a read and write command and receives the return time of the DDR.

As shown in fig. 3, the efficiency analysis logic 3 mainly implements the following functions:

(1) after the round of test is finished, calculating and counting the proportion of three accesses of PH, PFH and PM in a round of test according to the distribution condition of the conversion address output by the bus monitoring and analyzing logic device 2, wherein the change condition of Row and Bank of a plurality of adjacent accesses is analyzed to judge which access belongs to and count the times, and finally obtaining a proportion of the three accesses;

(2) after the test of the round is finished, the latency data output by the bus monitoring and analyzing logic device 2 is obtained, the average latency and the maximum latency of reading and writing in the test of the round and the bandwidth are calculated, the average latency can reflect the average efficiency of the DDR, the maximum latency can reflect the worst access condition of the DDR, the two indexes are counted based on the fact that the requirements of different masters for the performance are possibly different, some masters compare the average latency, and some masters require the worst condition not to exceed the latency, and the priorities can be set for the two indexes according to the different requirements of the masters. The bandwidth is an expression index of the DDR efficiency, generally, the DDR access by a master has a bandwidth requirement, theoretically, the average latency is smaller, the bandwidth is larger, the first bandwidth is calculated to see whether the command flow generated by the bus excitation generator is enough, and if the command flow does not need to be adjusted, the second bandwidth can visually reflect whether the DDR access path meets the bandwidth requirement of the master. After the read-write average latency, the maximum latency, the bandwidth and other parameters are calculated, the priorities of all indexes are set according to specific requirements, and the comprehensive efficiency condition of the DDR test in the round is calculated:

e ═ BW, LATavr, LATmax, LATpercent equation 1

The parameter represents the proportion of accesses which take more time than LATavr in one round of test, and may determine the distribution condition of latency by presetting a proportion, for example, setting the target LATpercent to 30%, which means that 70% of accesses will be less than LATavr, but may also cause the condition of LATmax to be worse. The priority of the bandwidth is set to be the highest, LATavr and LATmax are set according to actual requirements, and optimization is preferentially carried out towards the direction meeting the index with the highest priority in the process of efficiency comparison analysis.

As shown in fig. 4, the address mapping configuration logic 4 mainly implements the following functions:

1. according to the comprehensive efficiency performance output by the efficiency analysis logic device 3, combining the PH, PFH and PM distribution conditions generated by the bus monitoring analysis logic device 2 to automatically generate new address mapping configuration, and writing the configuration into DDR configuration parameters;

2. automatically starting a bus excitation to develop a new round of test according to a generator;

3. and automatically comparing the test results of the current round with the test results of the previous round, recording the configuration parameters with better efficiency performance, and repeatedly testing until the test cycle is exited when the efficiency is not obviously improved.

The method for testing by adopting the testing device for automatically generating the optimal DDR efficiency configuration parameters comprises the following steps:

1) the bus monitoring and analyzing logic device 2 converts the bus address generated by the bus excitation generator 1 according to the existing address mapping configuration, analyzes the conversion condition of the bus address and records the conversion condition; the bus monitoring and analyzing logic device 2 counts the consumption time of the bus excitation generator 1 for accessing and exciting the DDR logic device 5;

2) the efficiency analysis logic device 3 calculates and counts the proportion of three accesses of PH, PFH and PM in one round of test according to the distribution condition of the conversion address output by the bus monitoring analysis logic device 2; the efficiency analysis logic device 3 acquires the consumption time data output by the bus monitoring analysis logic device 2, and calculates the average consumption time, the maximum consumption time and the bandwidth of reading and writing in one round of test;

3) the address mapping configuration logic device 4 automatically generates new address mapping configuration according to the comprehensive efficiency performance output by the efficiency analysis logic device 3 by combining the PH, PFH and PM distribution conditions generated by the bus monitoring analysis logic device 2, writes the configuration into the configuration parameters of the DDR logic device 5, and automatically starts the bus excitation generator 1 to develop a new round of test; and the address mapping configuration logic device 4 automatically compares the test result with the test result of the previous round, records the configuration parameters with better efficiency performance, and repeatedly tests until the efficiency is not obviously improved, and exits the test cycle.

The above-mentioned embodiments only express the embodiments of the present invention, and the description thereof is more specific and detailed, and therefore, the present invention should not be construed as limiting the scope of the present invention. It should be noted that several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention.

Claims

1. A test device for automatically generating DDR optimal efficiency configuration parameters is characterized in that: the DDR bus test system comprises a bus excitation generator (1), a bus monitoring analysis logic device (2), an efficiency analysis logic device (3), an address mapping configuration logic device (4) and a DDR logic device (5), wherein the bus excitation generator (1) is used for generating access excitation to the DDR logic device (5), the bus monitoring analysis logic device (2) monitors the read-write behavior of the bus excitation generator (1) to the DDR logic device (5) in real time and outputs related monitoring data, the efficiency analysis logic device (3) collects data generated by the bus monitoring analysis logic device (2), calculates the efficiency condition and then outputs the related data, and the address mapping configuration logic device (4) collects data generated by the efficiency analysis logic device (3) for analysis and determines whether to adjust configuration parameters to restart the test.

2. The method for testing by using the testing device for automatically generating the optimal efficiency configuration parameters of the DDR as claimed in claim 1, wherein: the method comprises the following steps:

1) the bus monitoring and analyzing logic device (2) converts the bus address generated by the bus excitation generator (1) according to the existing address mapping configuration, analyzes the conversion condition of the bus address and records the conversion condition; the bus monitoring and analyzing logic device (2) counts the consumption time of the bus excitation generator (1) for accessing excitation of the DDR logic device (5);

2) the efficiency analysis logic device (3) calculates and counts the proportion of three accesses of PH, PFH and PM in one round of test according to the distribution condition of the conversion address output by the bus monitoring analysis logic device (2); the efficiency analysis logic device (3) acquires the consumption time data output by the bus monitoring analysis logic device (2), and calculates the average consumption time, the maximum consumption time and the bandwidth of reading and writing in one round of test;

3) the address mapping configuration logic device (4) automatically generates new address mapping configuration according to the comprehensive efficiency performance output by the efficiency analysis logic device (3) by combining the PH, PFH and PM distribution conditions generated by the bus monitoring analysis logic device (2), writes the configuration into the configuration parameters of the DDR logic device (5), and automatically starts the bus excitation generator (1) to perform a new round of test; and the address mapping configuration logic device (4) automatically compares with the test result of the previous round, records the configuration parameters with better efficiency performance, and repeatedly tests until the efficiency is not obviously improved, and then exits the test cycle.

3. The method for testing the automatic generation of the optimal efficiency configuration parameters for DDR according to claim 2, wherein: after the efficiency analysis logic device (3) acquires the average consumption time, the maximum consumption time and the bandwidth index of reading and writing, the priority of each index is set according to specific requirements, and the comprehensive efficiency condition of the DDR test in the current round is calculated:

e ═ BW, LATavr, LATmax, LATpercent equation 1