CN113918498A - Server and data center - Google Patents
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- CN113918498A CN113918498A CN202111516229.7A CN202111516229A CN113918498A CN 113918498 A CN113918498 A CN 113918498A CN 202111516229 A CN202111516229 A CN 202111516229A CN 113918498 A CN113918498 A CN 113918498A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/409—Mechanical coupling
Abstract
The invention discloses a server, comprising: the chassis comprises a chassis back plate, wherein a main back plate adapter and a plurality of slave back plate adapters are arranged on the chassis back plate, and each slave back plate adapter is connected with the main back plate connector; the mainboard is positioned in the case and is provided with a plurality of optical ports, an FPGA (field programmable gate array) connected with each optical port and a mainboard-backplane connector connected with the FPGA, and the mainboard-backplane connector is connected with the mainboard-backplane adapter; each hard disk backboard comprises a slave backplane connector, a plurality of exchange chips and a plurality of hard disk slots, each exchange chip is connected with the slave backplane connector, and each exchange chip is connected with a plurality of hard disk slots in the plurality of hard disk slots; each slave backplane adapter is connected with a slave backplane connector of one hard disk backplane. The invention further provides a data center. According to the scheme provided by the invention, the server framework is formed by the hard disk back plate, the case back plate and the main board, so that the structure of the storage server is simplified.
Description
Technical Field
The invention relates to the field of servers, in particular to a server and a data center.
Background
Currently, the access mode of the full flash memory is mainly JBOD, which is generally used to extend PCIE in the rack to extend storage. JBOF and EBOF may use NVMe-oF to extend storage between data centers. JBOF uses PCIe switches to extend SSD, while EBOF uses ethernet switches to extend SSD.
Take a dual-channel storage server supporting 48 NVME hard disks based on an Intel Birtch Stream platform as an example. As shown in fig. 1, a single CPU of a Birtch Stream platform has 6 sets of PCIE GEN 5X 16 channels, where 1 set of PCIE X16 channels is used to connect OCP NIC, BMC, and m.2 boot hard disk. The other 5 sets of PCIE X16 channels are used to extend NVME SSD hard disks. Usually, each hard disk needs to use a PCIE X4 channel, and 5 sets of PCIE X16 can only be connected to 20 NVME hard disks. Even if the CPU is in double-circuit, only 40 NVME hard disks can be connected. Therefore, each CPU needs to use one uplink PCIE X16 and PCIE SWTICH of a downlink PCIE X32 channel to expand a PCIE bus, so that each CPU can hang down 24 NVME hard disks, and a two-way CPU system can realize the storage requirement of 48 NVME hard disks.
Fig. 2 shows the NVME hard disk backplane of the universal storage server, wherein PCIE SWTICH chips and NVME hard disk connectors are located on the hard disk backplane, and each hard disk backplane can provide up to 24 NVME hard disk interfaces. The hard disk backplane comprises 5 Slimline PCIE X16 connectors, and 5 sets of PCIE X16 buses of the mainboard CPU are connected to the Slimline connectors of the hard disk backplane through cables. Two hard disk backplanes shown in fig. 2 are configured to meet the configuration requirements of 48 NVME hard disks.
Therefore, in the current scheme of expanding the hard disk by adopting the PCIE Switch, the hard disk backplane supports a design of 24 disks to the maximum, and when the hard disk requirement of 96 disks or a larger capacity is met, only the hard disk backplane with the PCIE Switch can be continuously stacked, and the PCIE Switch high-channel product has a high cost, a complex cluster system, and a complex cable.
Disclosure of Invention
In view of the above, in order to overcome at least one aspect of the above problems, an embodiment of the present invention provides a server, including:
the chassis comprises a chassis back plate, wherein a main back plate adapter and a plurality of slave back plate adapters are arranged on the chassis back plate, and each slave back plate adapter is connected with the main back plate adapter;
the mainboard is positioned in the case and is provided with a plurality of optical ports, an FPGA (field programmable gate array) connected with each optical port and a main backplane connector connected with the FPGA, and the main backplane connector is connected with the main backplane adapter;
each hard disk backboard comprises a slave backboard connector, a plurality of exchange chips and a plurality of hard disk slots, each exchange chip is connected with the slave backboard connector, and each exchange chip is connected with a plurality of hard disk slots in the plurality of hard disk slots;
each slave backplane adapter is connected with a slave backplane connector of one hard disk backplane.
In some embodiments, the host backplane adapter is located inside the chassis backplane;
the plurality of slave backplane adapters are arranged on the outer side of the chassis backplane according to a preset arrangement mode.
In some embodiments, each of the optical ports is connected to the FPGA through a first Serdes signal, where a channel of the first Serdes signal is a first preset channel and a bandwidth is a first preset bandwidth;
the FPGA is connected with the main backplane connector through a second Serdes signal, channels of the second Serdes signal are 2 times the number of first preset channels times the number of optical ports, and the bandwidth is one half of the first preset bandwidth;
the main backplane connector is connected to the main backplane adapter via the second Serdes signal.
In some embodiments, the master backplane adapter is connected to the slave backplane adapter via a third Serdes signal, wherein the channels of the third Serdes signal are 2 × first predetermined channels × number of optical ports/number of slave backplane adapters, and the bandwidth is one-half of the first predetermined bandwidth;
the slave backplane adapter is connected with a slave backplane connector of the hard disk backplane through the third Serdes signal.
In some embodiments, the slave backplane connector of the hard disk backplane is connected to each of the switch chips via a fourth Serdes signal, wherein the channels of the fourth Serdes signal are 2 × the number of first predetermined channels × the number of optical ports/(the number of slave backplane adapters × the number of switch chips), and the bandwidth is one half of the first predetermined bandwidth.
In some embodiments, the switch chip is configured to convert the fourth Serdes signal to a PCIE signal;
the hard disk slot is connected with the corresponding exchange chip through the PCIE signal, wherein a channel of the PCIE signal is a second preset channel, and the sum of bandwidths of the PCIE signal corresponding to the hard disk slot connected with the same exchange chip is smaller than the bandwidth of the fourth Serdes signal.
In some embodiments, the switch chip is a Fabric chip.
In some embodiments, further comprising:
managing the network port;
a PHY connected to the management portal;
a BMC connected to the PHY.
In some embodiments, the BMC is coupled to the FPGA, and the BMC is further configured to receive a management signal through a management portal to manage the FPGA.
Based on the same inventive concept, embodiments of the present invention further provide a data center including the server according to any one of the above embodiments.
The invention has one of the following beneficial technical effects: according to the scheme provided by the embodiment of the invention, the server framework is formed by the hard disk backboard, the case backboard and the mainboard, so that the structure of the storage server is simplified, the redundant cables are reduced, the long-distance storage can be realized, and the storage expandability and sharability are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic diagram of a two-way storage server architecture in the prior art;
fig. 2 is a schematic structural diagram of a 24-slot NVME hard disk backplane in the prior art;
fig. 3 is a schematic structural diagram of a server according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a server motherboard according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a hard disk backplane according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
According to an aspect of the present invention, an embodiment of the present invention provides a server, as shown in fig. 3, the server includes a chassis, a motherboard, and a plurality of hard disk backplanes.
The chassis comprises a chassis back plate, a main back plate adapter and a plurality of slave back plate adapters are arranged on the chassis back plate, and each slave back plate adapter is connected with the main back plate adapter.
In some embodiments, as shown in fig. 3 and 4, the motherboard is located inside the chassis, and is provided with a plurality of optical ports (QSFP-DD), an FPGA connected to each of the optical ports, and a motherboard connector connected to the FPGA, and the motherboard connector is connected to the motherboard adapter.
In some embodiments, as shown in fig. 5, each hard disk backplane shown in fig. 3 includes a slave backplane connector, a plurality of switch chips (fabrics), and a plurality of hard disk slots (slots), each switch chip being connected to the slave backplane connector, each switch chip being connected to a plurality of hard disk slots of the plurality of hard disk slots; as shown in fig. 3, each slave backplane adapter is connected to a slave backplane connector of one hard disk backplane.
According to the scheme provided by the embodiment of the invention, the server framework is formed by the hard disk backboard, the case backboard and the mainboard, so that the structure of the storage server is simplified, the redundant cables are reduced, the long-distance storage can be realized, and the storage expandability and sharability are improved.
In some embodiments, the host backplane adapter is located inside the chassis backplane;
the plurality of slave backplane adapters are arranged on the outer side of the chassis backplane according to a preset arrangement mode.
Specifically, as shown in fig. 3, the main backplane adapter is located inside the chassis backplane and connected to the main backplane connector of the motherboard, and the slave backplane adapters are disposed outside the chassis backplane in a predetermined arrangement, for example, at equal intervals.
In some embodiments, each of the optical ports is connected to the FPGA through a first Serdes signal, where a channel of the first Serdes signal is a first preset channel and a bandwidth is a first preset bandwidth;
the FPGA is connected with the main backplane connector through a second Serdes signal, channels of the second Serdes signal are 2 times the number of first preset channels times the number of optical ports, and the bandwidth is one half of the first preset bandwidth;
the main backplane connector is connected to the main backplane adapter via the second Serdes signal.
Specifically, as shown in fig. 4, the number of the optical ports may be 2. The bandwidth of each optical port can be set according to actual requirements, for example, the bandwidth of each optical port is 200G. Thus, the upstream channel of the FPGA is connected to each of the optical ports, for example, via a first Serdes signal. The channel of the first Serdes signal is a first predetermined channel, and the bandwidth is a first predetermined bandwidth, for example, when the bandwidth of each optical port is 200G, the bandwidth of the first Serdes signal may be 25G, and the channel may be 8 channels. And the uplink channel of the FPGA is connected with the main backplane connector through the second Serdes signal, and the same main backplane connector is connected with the main backplane adapter through the second Serdes signal. The second Serdes signal channel is 2 × the number of the first predetermined channels × the number of the optical ports, and the bandwidth is one half of the first predetermined bandwidth, for example, the second Serdes signal channel may be 2 × 8 × 2=32, and the bandwidth is 25G/2= 12.5G.
In some embodiments, the master backplane adapter is connected to the slave backplane adapter via a third Serdes signal, wherein the channels of the third Serdes signal are 2 × first predetermined channels × number of optical ports/number of slave backplane adapters, and the bandwidth is one-half of the first predetermined bandwidth;
the slave backplane adapter is connected with a slave backplane connector of the hard disk backplane through the third Serdes signal.
Specifically, since the slave backplane adapters are equivalent to branches from the master backplane adapter, the channels of the third Serdes signal are 2 × the first predetermined channels × the number of optical ports/the number of slave backplane adapters, and the bandwidth is one half of the first predetermined bandwidth, for example, when the number of slave backplane adapters is 2, the third Serdes signal channel may be 2 × 8 × 2/2=16, and the bandwidth is 25G/2= 12.5G.
In some embodiments, the slave backplane connector of the hard disk backplane is connected to each of the switch chips via a fourth Serdes signal, wherein the channels of the fourth Serdes signal are 2 × the number of first predetermined channels × the number of optical ports/(the number of slave backplane adapters × the number of switch chips), and the bandwidth is one half of the first predetermined bandwidth.
Specifically, as shown in fig. 3 and 5, the slave backplane connector of the hard disk backplane is connected to a slave backplane adapter via a third Serdes signal, and then the received third Serdes signal is converted into a plurality of fourth Serdes signals, which are further connected to each switch chip. Thus, the channels of the fourth Serdes signal are 2 × the first predetermined channels × the number of optical ports/(the number of backplane adapters × the number of switching chips), and the bandwidth is one half of the first predetermined bandwidth, which may be, for example, 2 × 8 × 2/(2 × 8) =2, and the bandwidth is 12.5G.
In some embodiments, the switch chip is configured to convert the fourth Serdes signal to a PCIE signal;
the hard disk slot is connected with the corresponding exchange chip through the PCIE signal, wherein a channel of the PCIE signal is a second preset channel, and the sum of bandwidths of the PCIE signal corresponding to the hard disk slot connected with the same exchange chip is smaller than the bandwidth of the fourth Serdes signal.
Specifically, the switching chip can complete the conversion from the high-speed Serdes signal to the PCIE bus without signal crossing function. The upstream of the switch chip is connected to the slave backplane connector through a fourth Serdes signal, that is, the upstream channel may be 2 and the upstream bandwidth may be 12.5G, the downstream may support 12-channel PCIE GEN4, the downstream bandwidth is 24Gbps, and a 1G bandwidth is reserved, that is, the upstream bandwidth is supplemented by payload information. Thus, when the NVME hard disk is a 4-channel PCIE GEN4 structure, one switch chip can hang down 3 NVME hard disks. The hard disk backplane shown in fig. 5 may include 8 switch chips, and may be full of 24 NVME hard disks.
In some embodiments, the switch chip is a Fabric chip.
In some embodiments, as shown in fig. 4, the motherboard further comprises:
managing the network port;
a PHY connected to the management portal;
a BMC connected to the PHY.
In some embodiments, the BMC is coupled to the FPGA, and the BMC is further configured to receive a management signal through a management portal to manage the FPGA.
Specifically, the BMC provides a server out-of-band management function, can detect the running state of the current storage server, and provides an RJ45 management port to the outside. Thus, the BMC can receive the management information of the FPGA through the RJ45 management network port so as to manage the FPGA.
According to the scheme provided by the embodiment of the invention, the server framework is formed by the hard disk backboard, the case backboard and the mainboard, so that the structure of the storage server is simplified, the redundant cables are reduced, the long-distance storage can be realized, and the storage expandability and sharability are improved.
Based on the same inventive concept, an embodiment of the present invention further provides a data center, including a plurality of servers, where each server includes:
the chassis comprises a chassis back plate, wherein a main back plate adapter and a plurality of slave back plate adapters are arranged on the chassis back plate, and each slave back plate adapter is connected with the main back plate connector;
the mainboard is positioned in the case and is provided with a plurality of optical ports, an FPGA (field programmable gate array) connected with each optical port and a main backplane connector connected with the FPGA, and the main backplane connector is connected with the main backplane adapter;
each hard disk backboard comprises a slave backboard connector, a plurality of exchange chips and a plurality of hard disk slots, each exchange chip is connected with the slave backboard connector, and each exchange chip is connected with a plurality of hard disk slots in the plurality of hard disk slots;
each slave backplane adapter is connected with a slave backplane connector of one hard disk backplane.
In some embodiments, the host backplane adapter is located inside the chassis backplane;
the plurality of slave backplane adapters are arranged on the outer side of the chassis backplane according to a preset arrangement mode.
In some embodiments, each of the optical ports is connected to the FPGA through a first Serdes signal, where a channel of the first Serdes signal is a first preset channel and a bandwidth is a first preset bandwidth;
the FPGA is connected with the main backplane connector through a second Serdes signal, channels of the second Serdes signal are 2 times the number of first preset channels times the number of optical ports, and the bandwidth is one half of the first preset bandwidth;
the main backplane connector is connected to the main backplane adapter via the second Serdes signal.
In some embodiments, the master backplane adapter is connected to the slave backplane adapter via a third Serdes signal, wherein the channels of the third Serdes signal are 2 × first predetermined channels × number of optical ports/number of slave backplane adapters, and the bandwidth is one-half of the first predetermined bandwidth;
the slave backplane adapter is connected with a slave backplane connector of the hard disk backplane through the third Serdes signal.
In some embodiments, the slave backplane connector of the hard disk backplane is connected to each of the switch chips via a fourth Serdes signal, wherein the channels of the fourth Serdes signal are 2 × the number of first predetermined channels × the number of optical ports/(the number of slave backplane adapters × the number of switch chips), and the bandwidth is one half of the first predetermined bandwidth.
In some embodiments, the switch chip is configured to convert the fourth Serdes signal to a PCIE signal;
the hard disk slot is connected with the corresponding exchange chip through the PCIE signal, wherein a channel of the PCIE signal is a second preset channel, and the sum of bandwidths of the PCIE signal corresponding to the hard disk slot connected with the same exchange chip is smaller than the bandwidth of the fourth Serdes signal.
In some embodiments, the switch chip is a Fabric chip.
In some embodiments, further comprising:
managing the network port;
a PHY connected to the management portal;
a BMC connected to the PHY.
In some embodiments, the BMC is coupled to the FPGA, and the BMC is further configured to receive a management signal through a management portal to manage the FPGA.
According to the scheme provided by the embodiment of the invention, the server framework is formed by the hard disk backboard, the case backboard and the mainboard, so that the structure of the storage server is simplified, the redundant cables are reduced, the long-distance storage can be realized, and the storage expandability and sharability are improved.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A server, comprising:
the chassis comprises a chassis back plate, wherein a main back plate adapter and a plurality of slave back plate adapters are arranged on the chassis back plate, and each slave back plate adapter is connected with the main back plate adapter;
the mainboard is positioned in the case and is provided with a plurality of optical ports, an FPGA (field programmable gate array) connected with each optical port and a main backplane connector connected with the FPGA, and the main backplane connector is connected with the main backplane adapter;
each hard disk backboard comprises a slave backboard connector, a plurality of exchange chips and a plurality of hard disk slots, each exchange chip is connected with the slave backboard connector, and each exchange chip is connected with a plurality of hard disk slots in the plurality of hard disk slots;
each slave backplane adapter is connected with a slave backplane connector of one hard disk backplane.
2. The server of claim 1, wherein the main backplane adapter is located inside the chassis backplane;
the plurality of slave backplane adapters are arranged on the outer side of the chassis backplane according to a preset arrangement mode.
3. The server according to claim 1, wherein each of the optical ports is connected to the FPGA through a first Serdes signal, wherein a channel of the first Serdes signal is a first predetermined channel, and a bandwidth is a first predetermined bandwidth;
the FPGA is connected with the main backplane connector through a second Serdes signal, channels of the second Serdes signal are 2 times the number of first preset channels times the number of optical ports, and the bandwidth is one half of the first preset bandwidth;
the main backplane connector is connected to the main backplane adapter via the second Serdes signal.
4. The server of claim 3, wherein the master backplane adapter is connected to the slave backplane adapter via a third Serdes signal, wherein the third Serdes signal has 2 x a first predetermined number of lanes optical ports/number of slave backplane adapters and a bandwidth of one half of a first predetermined bandwidth;
the slave backplane adapter is connected with a slave backplane connector of the hard disk backplane through the third Serdes signal.
5. The server according to claim 4, wherein the slave backplane connector of the hard disk backplane is connected to each of the switch chips via a fourth Serdes signal, wherein the fourth Serdes signal has 2 × first predetermined lanes × number of optical ports/(number of slave backplane adapters × number of switch chips), and a bandwidth of one half of the first predetermined bandwidth.
6. The server of claim 5, wherein the switch chip is configured to convert the fourth Serdes signal to a PCIE signal;
the hard disk slot is connected with the corresponding exchange chip through the PCIE signal, wherein a channel of the PCIE signal is a second preset channel, and the sum of bandwidths of the PCIE signal corresponding to the hard disk slot connected with the same exchange chip is smaller than the bandwidth of the fourth Serdes signal.
7. The server of claim 1, wherein the switch chip is a Fabric chip.
8. The server of claim 1, further comprising:
managing the network port;
a PHY connected to the management portal;
a BMC connected to the PHY.
9. The server of claim 8, wherein the BMC is coupled to the FPGA, the BMC further configured to receive a management signal through a management portal to manage the FPGA.
10. A data center comprising a server according to any one of claims 1-9.
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| CN209560436U (en) * | 2019-04-16 | 2019-10-29 | 苏州浪潮智能科技有限公司 | A kind of NVMe hard disk backboard |
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| CN103529919A (en) * | 2012-07-05 | 2014-01-22 | 鸿富锦精密工业（深圳）有限公司 | Server expander circuit and server system |
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