CN113918494A

CN113918494A - Sub-board

Info

Publication number: CN113918494A
Application number: CN202111182859.5A
Authority: CN
Inventors: 祝贺; 王帅; 周珏嘉; 陈虹雨
Original assignee: Beijing Xiaomi Mobile Software Co Ltd
Current assignee: Beijing Xiaomi Mobile Software Co Ltd
Priority date: 2021-10-11
Filing date: 2021-10-11
Publication date: 2022-01-11

Abstract

The utility model relates to a daughter board belongs to electron technical field, can improve development platform's expanded ability, the daughter board includes: a substrate; the daughter board communication interface is positioned on the substrate and is matched with a mother board communication interface on a daughter board slot position of the mother board and/or a communication interface on other daughter boards, the daughter board communication interface comprises a low-speed bus pin and a high-speed bus pin, the low-speed bus pin is used for carrying out low-speed communication, and the high-speed bus pin is used for carrying out high-speed communication; and the functional circuit is positioned on the substrate and used for realizing the function corresponding to the daughter board.

Description

Sub-board

Technical Field

The present disclosure relates to the field of electronic technology, and more particularly, to a daughter board.

Background

In the related art, a development platform includes a motherboard and a daughter board, which are generally applied to teaching experiment projects in a certain field, can only complete designed experiment contents, cannot expand an application range, and does not have development capability.

Disclosure of Invention

To overcome the problems in the related art, the present disclosure provides a subplate.

According to a first aspect of embodiments of the present disclosure, there is provided a seed board comprising: a substrate; the daughter board communication interface is positioned on the substrate and is matched with a mother board communication interface on a daughter board slot position of the mother board and/or a communication interface on other daughter boards, the daughter board communication interface comprises a low-speed bus pin and a high-speed bus pin, the low-speed bus pin is used for carrying out low-speed communication, and the high-speed bus pin is used for carrying out high-speed communication; and the functional circuit is positioned on the substrate and used for realizing the function corresponding to the daughter board.

Optionally, the daughter board communication interface has pins located on an upper surface of the substrate and pins located on a lower surface of the substrate, and the pins on the upper surface and the pins on the lower surface are in electrical communication.

Optionally, the daughter board further includes an electromagnetic shielding component for preventing the daughter board from electromagnetic interference.

Optionally, the electromagnetic protection component is a transparent housing and/or an electromagnetic protection circuit, wherein an opening required by the daughter board is left in the transparent housing.

Optionally, the daughter board is a microphone daughter board, and then, the transparent housing is a closed transparent housing, and a sound transmission hole is left at the microphone.

Optionally, the functions corresponding to the daughter board are distinguished by at least one of a daughter board size, a daughter board shape, and a substrate color.

Optionally, the daughter board further includes a magnetic foot disposed on the substrate, and the magnetic foot is used to fix the daughter board with the daughter board slot of the motherboard and/or the other daughter boards in a magnetic adsorption manner.

Optionally, the magnetic attraction foot is a magnetic attraction foot adopting a fool-proof design.

Optionally, if the daughter board is a compute and store daughter board, the daughter board further includes a debug interface located on the substrate for implementing debugging of the daughter board, where the daughter board communication interface and the debug interface are disposed on opposite sides of the substrate.

Optionally, a master-slave switching component is further included on the compute and storage daughter board for switching between the compute and storage daughter board being used as a master device and a slave device.

By adopting the technical scheme, the daughter board communication interface comprises the low-speed bus pin capable of carrying out low-speed communication and the high-speed bus pin capable of carrying out high-speed communication, so that the daughter board according to the embodiment of the disclosure has high-speed and low-speed communication capabilities, and high-speed and low-speed communication can be carried out simultaneously, so that the development platform can support more chips, can expand the application range (for example, transmitting video), build more complex applications (for example, developing products such as smart televisions) and the like, and enhance the expansion capability and development capability of the development platform.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.

FIG. 1 is a schematic diagram illustrating a development platform in accordance with an exemplary embodiment.

FIG. 2 is yet another schematic diagram illustrating a development platform in accordance with an illustrative embodiment.

Figure 3 is a schematic diagram of a daughterboard according to an exemplary embodiment.

FIG. 4 is a schematic diagram illustrating an adapter according to an exemplary embodiment.

Figure 5 is a schematic diagram of a power daughter board shown in accordance with an exemplary embodiment.

Figure 6 is yet another schematic diagram of a power daughter board shown in accordance with an exemplary embodiment.

Figure 7 is yet another schematic diagram of a power daughter board shown in accordance with an exemplary embodiment.

Fig. 8 is a schematic diagram of a power supply daughter board using a solar panel charging a power supply daughter board using a rechargeable battery.

FIG. 9 is a schematic diagram of a development platform shown in accordance with an exemplary embodiment.

FIG. 10 is a schematic diagram illustrating a motherboard communication interface and a daughterboard communication interface of a development platform, according to an example embodiment.

Fig. 11 to 15 are schematic layout diagrams illustrating high and low speed pins of a motherboard communication interface and a daughterboard communication interface of a development platform according to an exemplary embodiment.

Figure 16 is a schematic diagram of a daughter board shown in accordance with an exemplary embodiment.

Figure 17 is a schematic diagram illustrating a daughter board stack connection according to an exemplary embodiment.

Figure 18 is a schematic diagram illustrating a daughter board having a pin down daughter board communications interface in accordance with an exemplary embodiment.

Figures 19a and 19b are daughter board schematic diagrams illustrating a daughter board communications interface having an up pin and a down pin according to an exemplary embodiment.

FIG. 20 is a schematic diagram of an electromagnetic protection circuit for electromagnetically protecting a daughter board, shown in accordance with an exemplary embodiment.

Fig. 21 and 22 show a foolproof design of the daughter board.

Fig. 23-26 are schematic views of daughterboards of different size and shape shown according to an exemplary embodiment.

FIG. 27 is a schematic diagram of a motherboard shown in accordance with an exemplary embodiment.

FIG. 28 is a schematic system block diagram of a motherboard shown in accordance with an exemplary embodiment.

FIG. 29 is yet another schematic diagram of a motherboard shown in accordance with an exemplary embodiment.

FIG. 30 is a schematic diagram of a stand-alone motherboard shown in accordance with an exemplary embodiment.

FIG. 31 is yet another schematic diagram of a separate motherboard shown in accordance with an exemplary embodiment.

Figure 32 is a schematic diagram of a daughter board shown in accordance with an exemplary embodiment.

FIG. 33 is a block diagram illustrating a schematic functional structure of a compute and memory daughter board in accordance with an exemplary embodiment.

Fig. 34 is a schematic functional block diagram of a communication daughter board shown according to an exemplary embodiment.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

An Artificial Intelligence Internet of Things (AIOT) development platform is an intelligent embedded hardware platform, and can be any type of platform capable of teaching practical training and verification development, such as a practical training box. The development platform mainly comprises a motherboard and a daughter board. The motherboard supplies power to the daughter boards, and carries communication between the daughter boards. The daughter boards comprise a calculation and storage daughter board, a communication daughter board, a sensor daughter board, an actuator daughter board and the like. Based on the development platform, different daughter boards can be combined to carry out teaching practical training and development verification.

FIG. 1 is a schematic diagram illustrating a development platform in accordance with an exemplary embodiment. The development platform can be applied to teaching training and can also be applied to application and development verification, under the condition, developers can select appropriate daughter boards to simulate and build products on the development platform, further, the structure, algorithm, program, function and the like of product development are verified, and the waste of manpower, material resources, financial resources and time in the repeated board-making process in the conventional development process is avoided.

As shown in fig. 1, the development platform includes a box 100, a motherboard 200, and a daughter board 300, wherein the motherboard 200 includes thereon a low speed bus, a high speed bus, and a motherboard communication interface (see the detailed description for the motherboard below), the daughter board includes a daughter board communication interface (see the detailed description for the daughter board below), the motherboard communication interface is adapted to the daughter board communication interface and each includes a low speed bus pin and a high speed bus pin, wherein the low speed bus is used for low speed communication and connected to the low speed bus pin of the motherboard communication interface, and the high speed bus is used for high speed communication and connected to the high speed bus pin of the motherboard communication interface.

The motherboard communication interface is matched with the daughter board communication interface, that is, the motherboard communication interface and the daughter board communication interface can be electrically connected with each other to realize data transmission.

The high speed communication may be USB communication and other high speed communication types that enable video transmission. The low speed communications may be I2C communications, UART communications, SPI communications, RS485 communications, and other low speed communications types.

Since the high-speed communication is realized by the high-speed bus and the low-speed communication is realized by the low-speed bus, that is, the high-speed communication and the low-speed communication are realized by different communication buses, the high-speed communication and the low-speed communication can be simultaneously carried out.

Furthermore, it should be noted that the motherboard 200 may be implemented by any motherboard, and the daughter board 300 may be implemented by any daughter board, which are described in detail below.

By adopting the technical scheme, the motherboard comprises the low-speed bus and the high-speed bus, the motherboard communication interface on the motherboard is matched with the daughter board communication interface on the daughter board and respectively comprises the low-speed bus pin and the high-speed bus pin, the low-speed bus is connected to the low-speed bus pin of the motherboard communication interface, and the high-speed bus is connected to the high-speed bus pin of the motherboard communication interface, so that the development platform has high-speed and low-speed communication capability, and high-speed and low-speed communication can be carried out simultaneously, so that the development platform can support more chips, can expand the application range (such as transmitting video), build more complex applications (such as developing products like intelligent televisions) and enhance the expansion capability and development capability of the development platform.

In some embodiments, as shown in fig. 1, the housing 100 includes a daughter board receiving area 11, a power receiving area 12, and a motherboard receiving area 14, and the receiving areas are separately disposed. The daughter board receiving area 11 is used for receiving the daughter board 300, the power receiving area 12 is used for receiving power for supplying power to the development platform, and the motherboard receiving area 14 is used for receiving the motherboard 200. Although the daughter board receiving area 11 shown in fig. 1 includes 6 daughter board receiving slots and the mother board receiving area 14 includes 1 mother board receiving slot, it should be understood by those skilled in the art that the number of receiving slots in the mother board receiving area 14 and the daughter board receiving area 11 are only examples and do not constitute a limitation of the present disclosure.

The daughter board receiving area 11 may be located on the lid of the box body 100 or may be located on the bottom of the box body 100. For example, it may be disposed in a left or right region of the cover of the case 100.

The daughter board 300 has an outer shape matching the outer shape of the notch of the daughter board receiving area 11 to be fixed in the notch of the daughter board receiving area 11. That is, by catching the daughter board 300 in the notch of the daughter board receiving area 11, the daughter board 300 can be conveniently and quickly fixed in the daughter board receiving area 11. In addition, a buckle can be arranged at the notch of the daughter board receiving area 11, so that the daughter board 300 can be taken conveniently.

The mother board storage area 14 may be located on the bottom of the case 100, for example, in a left area or a right area of the bottom, so that the mother board 200 can be directly placed in the mother board storage area 14 for use without being taken out for use, thereby increasing convenience in use. Of course, it is also possible to take the motherboard 200 out for use.

Still referring to fig. 1, the case 100 may further include a connecting wire receiving area 13 for receiving various connecting wires, such as a display screen connecting wire.

The housing 100 may further include a display screen receiving area 15 for receiving a display screen. The display screen receiving area 15 may be located on a cover of the case 100, for example, may be located in a left area or a right area of the cover. Therefore, the display screen can be directly placed in the display screen storage area 15 for use without being taken out for use, and the use convenience is improved.

The shape of the display screen matches the shape of the notch of the display screen receiving area 15 to be fixed in the display screen receiving area 15. That is to say, through blocking the display screen in the notch of display screen storage area 15, just can fix the display screen in display screen storage area 15 convenient and fast ground. In addition, the notch of display screen storage area 15 department can set up the attacker, makes things convenient for taking of display screen. The display screen is provided with a wiring port, and the display screen can be connected with the corresponding daughter board 300 through a connecting wire during use.

The daughter board 300 and the display screen can be attracted to the respective receiving areas in a magnetic attraction manner. Like this, through multiple fixed (also inhale the fixed mode of absorption and the fixed mode of buckle by magnetism), guaranteed the steadiness of accomodating, avoid opening and shutting and the drop of in transportation daughter board 300 and display screen.

Through carrying out the subregion and accomodating, can maximize the inner space of utilizing box 100, make things convenient for taking of each part, avoid piling up the confusion, damage each part.

In some embodiments, as shown in FIG. 2, the motherboard receiving area 14 may include an upper motherboard receiving area 1401 and a lower motherboard receiving area 1402, i.e., the motherboard receiving area 14 is divided into upper and lower layers. The upper motherboard receiving area 1401 is used for receiving the motherboard 200, and the lower motherboard receiving area 1402 is used for receiving the daughter board 300. The daughter board 300 may be stacked and received in the lower motherboard receiving area 1402 by its own magnetic pins. Thus, the internal use space of the housing 100 is increased, and more daughter boards 300 can be housed. In addition, although the lower mother board receiving area 1402 is shown to be divided into 6 cells in fig. 2, it should be understood by those skilled in the art that the number of cells is not limited in the present disclosure, that is, the number of cells and the size of cells may be set as appropriate according to the size of the sub board 300 and the size of the lower mother board receiving area 1402.

In some embodiments, the housing 100 may further include a conventional daughter board receiving slot 16 for receiving a conventional daughter board. The daughter board receiving grooves 16 may be partitioned into a plurality of daughter board receiving grooves by partitions, so as to facilitate receiving a plurality of daughter boards 300. The daughter board receiving grooves 16 may be formed on the bottom of the case body 100, which is closer to the user than the case cover, so that the daughter boards 300 can be easily taken. By providing the daughter board storage groove 16, the daughter boards which are frequently used can be easily taken. The depth of each daughter board receiving groove can be set according to the length or width of the daughter board 300, and the opening size of each daughter board receiving groove can be set according to the thickness of the daughter board 300, so that the depth of the bottom of the box can be fully utilized, and more daughter boards 300 can be received.

Figure 3 is a schematic diagram of a daughterboard according to an exemplary embodiment. As shown in fig. 3, the daughterboard includes a substrate 31, a daughterboard communication interface 32, and an electronics interface 33.

The substrate 31 is a carrier for the daughter board communication interface 32 and the electronics interface 33 and may be any type of substrate, such as a printed wiring board.

The daughter board communication interface 32 is located on the substrate 31 and is adapted to a motherboard communication interface on a daughter board slot of the motherboard and/or a communication interface on another daughter board, and the daughter board communication interface 32 includes a low-speed bus pin and a high-speed bus pin, where the low-speed bus pin is used for low-speed communication and the high-speed bus pin is used for high-speed communication. Adaptive here means that the two can be electrically connected to achieve data transmission. The motherboard may be any type of motherboard as long as it can carry communication of the adapter daughter board, and for example, the motherboard may be a motherboard applied to a practical training box, or a motherboard applied to another development platform other than the practical training box. Similarly, the other daughter boards herein may be any type of daughter board as long as it can perform data transmission with the adapter daughter board, for example, the daughter board may be a daughter board applied to a practical training box, and may also be a daughter board applied to other development platforms besides the practical training box.

The daughter board communication interface 32 may be a pin interface, and may be connected by a flat cable or a dupont cable of a universal specification, so as to perform UART serial port communication, IIC bus communication, USB communication, mic data communication, and the like. Here, the mic data communication means microphone data communication.

An electronics interface 33 is located on the substrate 31 and is electrically connected to the daughter board communication interface 32 through wiring on the substrate 31, the electronics interface 33 being compatible with an interface to external electronics. Here, the external electronic device may be any type of electronic device that needs to be connected to the electronic device interface 33 of the daughter board, such as a USB disk, a mouse, a development board for a single chip microcomputer, a keyboard, a USB camera, and the like.

The electronics interface 33 may include any type of interface, such as at least one of a USB interface, a UART interface, a MIC interface, an IIC interface, a power interface, an RJ45 interface, an ethernet interface, a VGA interface, an HDMI interface, an SD card slot, and so forth.

By adopting the above technical solution, since the daughter board communication interface 32 includes the low-speed bus pin for performing low-speed communication and the high-speed bus pin for performing high-speed communication, the daughter board according to the embodiment of the present disclosure has high-speed and low-speed communication capabilities and high-speed and low-speed communication can be performed simultaneously, and the electronic device interface 33 enables the daughter board according to the embodiment of the present disclosure to be connected with any type of external electronic device, that is, by means of the daughter board communication interface 32 and the electronic device interface 33, the external electronic device can be connected to the daughter board slot of the mother board or other daughter boards, for example, the external electronic device is connected to the mother board of the development platform, and therefore, the application range and compatibility of the development platform can be expanded by the daughter board through the capability of high-speed and low-speed communication and the capability of connecting with any external electronic device, therefore, more complex applications can be built, and the expansion capability and development capability of the development platform are enhanced.

In some embodiments, as shown in fig. 3, the adapter sub-board further includes a magnetic foot 34 disposed on the substrate 31, where the magnetic foot 34 is used to fix the adapter sub-board on a sub-board slot of the motherboard or on another sub-board by a magnetic absorption manner, so as to achieve a stable connection between the adapter sub-board and the motherboard or another sub-board.

The magnetic suction pins 34 are designed to be foolproof, so that the adapter sub-board can be prevented from being placed wrongly. For example, the magnetic pin 34 can be designed to be trapezoidal, and similarly, the daughter board slot of the motherboard and the magnetic pin on other daughter boards are also designed to be trapezoidal, so that when the adapter daughter board is connected with the daughter board slot of the motherboard or other daughter boards, the inversion of the daughter boards can be avoided. For another example, if the adapting daughter board can be connected to the first daughter board slot of the motherboard but cannot be connected to the second daughter board slot of the motherboard, the magnetic pin layout of the adapting daughter board can be designed to match the magnetic pin layout of the first daughter board slot but not match the magnetic pin layout of the second daughter board slot, so that the adapting daughter board can only be stably connected to the first daughter board slot but cannot be stably connected to the second daughter board slot.

In addition, although fig. 3 shows 4 magnetic attraction legs 34, the number and the arrangement position of the magnetic attraction legs 34 are not limited in the present disclosure as long as the purpose of stable connection and fool-proofing can be achieved, for example, 4 magnetic attraction legs 34 may be provided and configured into a trapezoid or a parallelogram, etc.

In some embodiments, the electronics interface 33 includes at least one USB interface, in which case the daughterboard may further include a USB-HUB chip (not shown) and a USB master-slave control assembly 35 on the substrate 31. The USB-HUB chip is used for interacting with the USB interface to realize data transmission, and can be simultaneously connected with a plurality of USB devices through the USB interface. The USB master-slave control component 35 is configured to control whether the USB interfaces are in the slave mode or the master mode, wherein in case the USB interfaces are controlled to be in the slave mode, at least one USB interface is used as the slave interface, and in case the USB interfaces are controlled to be in the master mode, at least one USB interface is used as the master interface.

The USB master-slave control assembly 35 may be in the form of a dial switch, a rotary switch, a push button, etc.

In addition, the master-slave mode of operation of the USB interface may be controlled not by the USB master-slave control component 35 described above, but by presetting the USB interface as a master interface or a slave interface. For example, assuming that the adapter daughter board includes two USB interfaces, one of the USB interfaces may be preset as a master device interface for accessing a master device such as a raspberry pi, a single chip development board, and the other USB interface may be preset as a slave device interface for allowing access to a slave device such as a USB disk and a mouse. Thus, the USB master slave control component 35 may be omitted.

By adopting the configuration, the master-slave working mode of the USB interface can be effectively controlled, the master-slave control of USB communication is realized, the wiring complexity on the adapter daughter board is simplified, and the cost is reduced.

In some embodiments, as shown in fig. 3, the daughterboard may further include an operating status indication assembly 36 on the substrate 31 for indicating the operating status of the daughterboard, such as indicating whether the daughterboard is currently in an operating or closed state. The operation status indicating assembly 36 may be in the form of an indicator light, and when the adapter board is in the power-on operation state, the indicator light is on, and when the adapter board is not in the power-on state, the indicator light is not on, so that the operation status of the adapter board can be conveniently indicated.

In some embodiments, as shown in fig. 3, the daughterboard may further include a communication status indication component 37 for the electronic device interface 33 on the substrate 31 for indicating the communication status of the electronic device interface 33. The communication status indicating component 37 may be in the form of an indicator light, and an indicator light for indicating the communication status of each electronic device interface 33 may be configured for each electronic device interface 33, and it is of course also possible to configure the communication status indicating component for only a part of the electronic device interfaces 33. For example, if the USB communication is currently performed, an indicator light for indicating the communication status of the USB interface is turned on to indicate the current status of the USB communication. By employing the communication status indication component 37, a status prompt can be provided for development and monitoring.

In some embodiments, as shown in fig. 3, the daughterboard may further include a reset switch 38 on the base plate 31 for resetting the daughterboard. For example, in the event of a malfunction of the daughter board, the reset switch 38 is pressed to control the reset of the daughter board. Therefore, the reset can be realized under the condition that the adapter sub-board works wrongly, and the normal work of the adapter sub-board is ensured.

FIG. 4 is a schematic diagram illustrating an adapter according to an exemplary embodiment. As shown in fig. 4, the adapter interface includes an adapter communication interface 41 and an electronic device interface 42.

The patch communication interface 41 is compatible with a motherboard communication interface on a motherboard slot of a motherboard and/or with a daughter board communication interface on a daughter board. The switching communication interface 41 includes a low-speed bus pin for low-speed communication and a high-speed bus pin for high-speed communication. Adaptive here means that the two can be electrically connected to achieve data transmission. The motherboard may be any type of motherboard as long as it can carry communication of the adapter, for example, the motherboard may be a motherboard applied to a practical training box, or a motherboard applied to another development platform other than the practical training box. Similarly, the other daughter boards herein may be any type of daughter board as long as it can perform data transmission with the adapter daughter board, for example, the daughter board may be a daughter board applied to a practical training box, and may also be a daughter board applied to other development platforms besides the practical training box.

The adapting communication interface 41 may be a pin interface, and may be connected by a flat cable or a dupont cable of a general specification, so as to perform UART serial port communication, IIC bus communication, USB communication, mic data communication, and the like. Here, the mic data communication means microphone data communication.

The electronic device interface 42 is electrically connected to the switching communication interface 41 through a connecting line, and the electronic device interface 42 is adapted to an interface of an external electronic device. Here, the external electronic device may be any type of electronic device that needs to be connected to the electronic device interface 42 of the adaptor according to the embodiment of the present disclosure, such as a USB disk, a mouse, a single chip development board, a keyboard, a USB camera, and the like.

The electronics interface 42 may include any type of interface, such as at least one of a USB interface, a UART interface, a MIC interface, an IIC interface, a power interface, an RJ45 interface, an ethernet interface, a VGA interface, an HDMI interface, an SD card slot, and so forth.

The power interface may include at least one of a dc power interface and a power Type-C interface, that is, in an actual product, limited by the size of the adapter, only one of the power interfaces may exist. The input voltage of the power interface is set according to the external electronic device to which the power interface needs to be connected, and may be 5V, for example.

The RJ45 interface may be a crystal header interface and may be used for network data communications.

By adopting the above technical solution, since the adapting communication interface 41 includes the low-speed bus pin for performing low-speed communication and the high-speed bus pin for performing high-speed communication, the adapting interface according to the embodiment of the present disclosure has high-speed and low-speed communication capabilities and high-speed and low-speed communication can be performed simultaneously, and the electronic device interface 42 enables the adapting interface according to the embodiment of the present disclosure to be connected with any type of external electronic device, that is, by means of the adapting communication interface 41 and the electronic device interface 42, the external electronic device can be connected to the daughter board slot of the motherboard or other daughter boards, for example, the external electronic device is connected to the motherboard of the development platform, and therefore, the application range and compatibility of the development platform can be expanded by the adapting interface due to the capability of high-speed and low-speed communication and the capability of connecting with any electronic device, therefore, more complex applications can be built, and the expansion capability and development capability of the development platform are enhanced.

In some embodiments, the electronic device interface 42 may include at least one USB interface, in which case the interface may also include a USB-HUB chip (not shown) and a USB master slave control assembly 43. The USB-HUB chip is used for interacting with the USB interface to realize data transmission, and can be simultaneously connected with a plurality of USB devices through the USB interface. The USB master-slave control component 43 is used to control whether the USB interfaces are in the slave mode or the master mode, wherein in case the USB interfaces are controlled to the slave mode, at least one USB interface is used as the slave interface, and in case the USB interfaces are controlled to the master mode, at least one USB interface is used as the master interface.

The USB master-slave control component 43 may be at least one of a dial switch, a knob switch, and a key.

Furthermore, instead of controlling the master-slave mode of operation of the USB interface via the USB master-slave control module 43 described above, the master-slave mode may be controlled by presetting the USB interface as a master interface or a slave interface. For example, assuming that the electronic device interface 42 includes a USB 2.0Type-a interface, a USB Type-C interface, a USB 2.0Type-B interface, and a USB 2.0Micro-B interface, the USB 2.0Type-a interface and the USB Type-C interface may be preset as slave device interfaces to allow access to slave devices such as a USB disk and a mouse, and the USB 2.0Type-B interface and the USB 2.0Micro-B interface are preset as master device interfaces to access to master devices such as a raspberry group and a single chip development board. Thus, the USB master slave control assembly 43 may be omitted.

By adopting the configuration, the master-slave working mode of the USB interface can be effectively controlled, the master-slave control of USB communication is realized, the wiring complexity on the switching interface is simplified, and the cost is reduced.

In some embodiments, as shown in FIG. 4, the adapter port further includes an operational status indication assembly 44 for indicating the operational status of the adapter port. For example to indicate whether the adapter port is currently in an operative or closed state. The operating condition indicating assembly 44 may be in the form of an indicator light that is illuminated when the adapter is in an energized operating condition and not illuminated when the adapter is not in an energized condition, thereby enabling the operating condition of the adapter to be conveniently indicated.

In some embodiments, the adapter may further include a communication status indication component (not shown) for the electronic device interface 42 for indicating a communication status of the electronic device interface 42. The communication status indicating component may be in the form of an indicator light, and an indicator light for indicating the communication status of each electronic device interface 42 may be configured for each electronic device interface 42, and it is of course also possible to configure the communication status indicating component for only a part of the electronic device interfaces 42. For example, if USB communication is currently being performed, an indicator lamp for indicating the communication state of the USB interface is turned on for prompting the current state of the USB communication. By employing the communication status indication component, a status prompt can be provided for development and monitoring.

In some embodiments, the adapter may further include a reset switch (not shown) for resetting the adapter. For example, in the case of an operational error of the transfer port, the reset switch is pressed to control the reset of the transfer port. Therefore, the reset can be realized under the condition that the switching port works wrongly, and the normal work of the switching port is ensured.

Figure 5 is a schematic diagram of a power daughter board shown in accordance with an exemplary embodiment. As shown in fig. 5, the power supply daughter board includes a substrate 51, a daughter board communication interface 52, a power supply 53, and a controller 54.

The substrate 51 is a carrier for the daughter board communication interface 52, the controller 54, and the power supply 53, and may be any type of substrate, such as a printed wiring board.

The daughter board communication interface 52 is located on the substrate 51 and is adapted to a motherboard communication interface on a daughter board slot of the motherboard and/or a communication interface on another daughter board, and the daughter board communication interface 52 includes a low-speed bus pin and a high-speed bus pin, where the low-speed bus pin is used for low-speed communication and the high-speed bus pin is used for high-speed communication. Adaptive here means that the two can be electrically connected to achieve data transmission. The motherboard may be any type of motherboard as long as it can carry communication of the adapter daughter board, and for example, the motherboard may be a motherboard applied to a practical training box, or a motherboard applied to another development platform other than the practical training box. Similarly, the other daughter boards herein may be any type of daughter board as long as it can perform data transmission with the adapter daughter board, for example, the daughter board may be a daughter board applied to a practical training box, and may also be a daughter board applied to other development platforms besides the practical training box.

The daughter board communication interface 52 may be a pin interface, and may be connected by a flat cable or a dupont cable of a universal specification, so as to perform UART serial port communication, IIC bus communication, USB communication, mic data communication, and the like. Here, the mic data communication means microphone data communication.

The power source 53 is located on the substrate 51 and may comprise any type of power source, such as at least one of a rechargeable battery, a solar panel, and the like. The rechargeable battery can be a lithium battery, a lead-zinc battery, a nickel-cadmium battery, etc. For the solar panel, the solar panel can convert solar energy into electric energy at any time and any place, so that the cruising ability of the power supply daughter board is improved. The solar panel is rotatable and liftable, so that the solar panel can find the optimal light source by lifting the solar panel or rotating the solar panel and the like to fully convert light energy.

The controller 54 is located on the substrate 51 and is used for controlling the power supply 53 to supply power to the outside through the daughter board communication interface 52. For example, other daughter boards that require power may be powered through the daughter board communication interface 52; the motherboard may also be powered through the daughter board communication interface 52; the daughter board communication interface 52 may also be connected to the previously described daughter board or adapter, and the external electronic device requiring power may be connected to the electronic device interface of the daughter board or adapter, so that the power daughter board according to the embodiments of the present disclosure can be utilized to supply power to the external electronic device.

The controller 54 may be any type of controller such as a field programmable gate array, a single chip, or the like.

In addition to controlling the external power supply of the power daughter board, the controller 54 may also be used to control the charging, overcharge and overdischarge protection, voltage stabilization, etc. of the power daughter board. For example, in the case where the power supply 53 is a rechargeable battery, the controller 54 may control the rechargeable battery to draw power from the motherboard through the daughter board communication interface 52 for charging, so that the power daughter board can be charged by the motherboard in the case where the power of the power daughter board is insufficient.

By adopting the technical scheme, the daughter board communication interface 52 comprises the low-speed bus pin for low-speed communication and the high-speed bus pin for high-speed communication, so that the power daughter board according to the embodiment of the disclosure has high-speed and low-speed communication capabilities, high-speed and low-speed communication can be simultaneously performed, and power is supplied to the outside through the daughter board communication interface 52, so that other daughter boards can be used by being separated from the motherboard.

Figure 6 is yet another schematic diagram of a power daughter board shown in accordance with an exemplary embodiment. As shown in fig. 6, the power supply daughter board may further include a remaining power display assembly 55, which is located on the substrate 51. The controller 54 may be further configured to query the remaining power of the power supply 53; the remaining power display module 55 is used to display the remaining power, so that the user can know the remaining power of the power daughter board in real time.

The remaining power display unit 55 may be at least one of a digital display tube, a remaining power indicator light, a signal grid, and the like. When the power daughter board is in the top that the daughter board vertically piled up, the form such as digital display tube, signal check more is favorable to the user to know the residual capacity condition, and when the power daughter board was in the vertically intermediate position that piles up of daughter board, the form of residual capacity pilot lamp more was favorable to the user to know the residual capacity condition.

In some embodiments, as shown in fig. 6, the power daughter board may further include an operation control component 56 on the substrate 51 for controlling the power daughter board to be turned on and off. The operation control assembly 56 may be in the form of a dial switch, a rotary switch, a push button, or the like. When the work control assembly 56 controls the power supply sub-board to be turned off, the power supply sub-board can be ignored, and when the work control assembly 56 controls the power supply sub-board to be turned on, the power supply sub-board is in a working state and can be charged and discharged.

In some embodiments, as shown in fig. 6, the power daughter board may further include a reset switch 57 on the substrate 51 for resetting the power daughter board. For example, when the power supply daughter board malfunctions, the reset switch 57 is pressed to control the reset of the power supply daughter board. The reset switch 57 may be in the form of a dial switch, a rotary switch, a push button, or the like. Therefore, when the power supply daughter board has an error, the power supply daughter board can be reset, and the normal operation of the power supply daughter board is ensured.

In some embodiments, as shown in fig. 6, the power daughter board may further include a magnetic pin 58 disposed on the substrate 51, and the magnetic pin 58 is used to fix the power daughter board to a daughter board slot of the motherboard or to other daughter boards by means of magnetic attraction. This enhances the stability of the connection. The magnetic pins 58 can be designed to be fool-proof to avoid placing errors of the daughter boards during connection. The foolproof design has been described in detail above and will not be described in detail herein.

In some embodiments, as shown in fig. 6, the power supply daughter board may further include a charge and discharge indication assembly 59 on the base board 51 for indicating whether the power supply 53 daughter board is in a charged state or a discharged state. For example, if the charge indicator lamp in fig. 6 is turned on, it indicates that the power sub-board is currently being charged, and if the discharge indicator lamp in fig. 6 is turned on, it indicates that the power sub-board is currently being discharged to the outside. Therefore, the user can know the state of the power supply daughter board in time, and misoperation is avoided.

Fig. 7 is yet another schematic diagram of a power daughter board shown in accordance with an exemplary embodiment, suitable for use where the power source 53 includes a solar panel. As shown in fig. 7, the power daughter board may further include a light intensity indicating assembly 60 on the substrate 51 for indicating whether the power daughter board is conditionally turned on. If the light intensity indicating component 60 indicates that the current light intensity is relatively weak, it indicates that the power daughter board is currently turned on, the electric energy obtained by solar energy conversion is not too much, and if the light intensity indicating component 60 indicates that the current light intensity is very strong, it indicates that the power daughter board is turned on, the solar energy can be effectively utilized to convert the electric energy. The light intensity indicating assembly 60 may be in the form of an indicator light or a signal grid.

In some embodiments, as shown in fig. 7, for the power daughter board using the solar panel, it may further include an operation status indication component 61 for indicating whether the power daughter board is currently in an operation status, so that a user can clearly know the operation status of the power daughter board. The operating condition indicating assembly 61 may be in the form of an indicator light.

In some embodiments, a power daughter board using solar panels may be used to charge a power daughter board using rechargeable batteries. As shown in fig. 8, the power daughter board including the rechargeable battery can be charged by the power daughter board including the solar panel, by stacking the power daughter board using the solar panel and the power daughter board using the rechargeable battery so that the daughter board communication interfaces of the two are electrically connected to each other. Thus, solar energy can be fully utilized, energy can be saved, and the power supply daughter board using the rechargeable storage battery can be simply charged.

FIG. 9 is a schematic diagram of a development platform shown in accordance with an exemplary embodiment. As shown in fig. 9, the development platform includes a motherboard 91 and a daughter board 92, the motherboard 91 includes a motherboard communication interface 910, the daughter board 92 includes a daughter board communication interface 920, the motherboard communication interface 910 is adapted to the daughter board communication interface 920 and includes a low-speed bus pin and a high-speed bus pin, respectively, the low-speed bus pin is used for low-speed communication, and the high-speed bus pin is used for high-speed communication. Adaptive here means that the two can be electrically connected to achieve data transmission. The motherboard may be any type of motherboard as long as it can carry communication of the daughter boards, and for example, the motherboard may be a motherboard applied to a practical training box, or a motherboard applied to another development platform other than the practical training box. Similarly, the other daughter boards herein may be any type of daughter board as long as it can perform data transmission with the adapter daughter board, for example, the daughter board may be a daughter board applied to a practical training box, and may also be a daughter board applied to other development platforms besides the practical training box.

The modular design in the development platform is essentially the objective embodiment of fragmenting the computing, storing, sensing, executing and other capabilities in the development platform system. For different application scenarios, the above-mentioned modules have great differences in capabilities of calculation, storage, sensing, execution and the like, and the data communication characteristics between the modules are also great differences. Some information transmission is low rate but real-time performance is high, some is high rate and has certain real-time performance requirement, some is low rate and does not require too high real-time performance. By providing both the motherboard communication interface 910 and the daughter board communication interface 920 with low-speed bus pins and high-speed bus pins, the requirements of the above-mentioned various application scenarios can be satisfied.

The high speed bus pins may be USB pins as well as other types of high speed communication pins that enable video transmission. The low speed bus pins may be I2C pins, UART pins, SPI pins, and other types of low speed bus pins.

Since the high-speed communication is realized through the high-speed bus pins and the low-speed communication is realized through the low-speed bus pins, that is, the high-speed communication and the low-speed communication are realized by adopting different communication bus pins, the high-speed communication and the low-speed communication can be simultaneously carried out.

By adopting the technical scheme, the motherboard communication interface and the daughter board communication interface respectively comprise the low-speed bus pin capable of carrying out low-speed communication and the high-speed bus pin capable of carrying out high-speed communication, so that the development platform has high-speed and low-speed communication capability and high-speed and low-speed communication can be carried out simultaneously, the development platform can support more chips, the application range can be expanded (such as video transmission), more complex applications can be built (such as intelligent television development and other products), and the expansion capability and the development capability of the development platform are enhanced.

In some embodiments, the motherboard communication interface 910 and the daughter board communication interface 920 may include other pins, such as a debug pin, an MIC pin, a master slave detection pin, a power pin, a ground pin, and so forth, in addition to the high speed bus pin and the low speed bus pin. This enables the motherboard communication interface 910 and the daughter board communication interface 920 to meet various practical requirements.

FIG. 10 is a diagram illustrating a motherboard communication interface 910 and a daughterboard communication interface 920 of a development platform, according to an example embodiment. As shown in fig. 10, the low-speed bus pins include an I2C pin, a UART1 pin, and a UART2 pin, and the high-speed bus pins include a USB pin; in addition, the motherboard communication interface 910 and the daughter board communication interface 920 include MIC array pins, analog MIC pins, master-slave detection pins, VCC pins, and GND pins. It should be understood by those skilled in the art that these pins and their numbers are merely examples and do not constitute a limitation of the present disclosure. That is, the low-speed bus pin and the high-speed bus pin are not limited to the pins listed above, and for example, the high-speed bus pin may be an HDMI pin, a DP pin, or a USB protocol pin of the subsequent evolution, or the like; also, the other pins than the low-speed bus pins and the high-speed bus pins are not limited to the pins listed above. These may be varied according to the actual application.

Fig. 11 to 15 are schematic layout diagrams illustrating high and low speed pins of a motherboard communication interface 910 and a daughter board communication interface 920 of a development platform according to an exemplary embodiment. As shown in fig. 11, the low speed bus pins and the high speed bus pins are located on different sides of the communication interface and are arranged opposite each other. As shown in fig. 12, the low speed bus pins and the high speed bus pins are located on different sides of the communication interface and are not arranged opposite. As shown in fig. 13, the low speed bus pins and the high speed bus pins are located on the same side of the communication interface and are arranged adjacent to each other. As shown in fig. 14, the low speed bus pins and the high speed bus pins are located on the same side of the communication interface and are not arranged adjacently. As shown in fig. 15, the low-speed bus pins and the high-speed bus pins are all plural and are distributed in a staggered manner.

By reasonably arranging the positions of the high-speed bus pins and the low-speed bus pins, the reasonable wiring of the high-speed bus and the low-speed bus which are respectively connected with the high-speed bus pins and the low-speed bus pins can be optimized, the wiring complexity is reduced, the cost is reduced, and the mutual interference of high-speed and low-speed communication is avoided.

In some embodiments, the distance between the low-speed bus pin and the high-speed bus pin is such that the low-speed communication and the high-speed communication do not interfere with each other, for example, the low-speed bus pin and the high-speed bus pin are respectively arranged at diagonal positions of the communication interface to increase the distance between the low-speed bus pin and the high-speed bus pin. Therefore, the mutual interference of high-speed and low-speed communication can be avoided, and the communication quality is improved.

It should be noted that the motherboard communication interface and the daughter board communication interface described herein can be applied to various daughter boards (e.g., power supply daughter boards, adapter ports, communication daughter boards, computation and storage daughter boards, sensor daughter boards, execution daughter boards, etc.) and mother boards described in the present disclosure, so that there are common and mutually adapted communication interfaces between the daughter boards of the development platform and between the mother board and the daughter board to realize electrical connection therebetween.

Figure 16 is a schematic diagram of a daughter board shown in accordance with an exemplary embodiment. As shown in fig. 16, the daughter board includes a substrate 161, a daughter board communication interface 162, and a function circuit 163.

The substrate 161 is a carrier for the daughter board communication interface 162 and the functional circuitry 163, and may be any type of substrate, such as a printed wiring board.

The daughter board communication interface 162 is located on the substrate 161 and is compatible with a motherboard communication interface on a daughter board slot of a motherboard and/or with communication interfaces on other daughter boards.

The daughter board communication interface 162 includes a low-speed bus pin for low-speed communication and a high-speed bus pin for high-speed communication.

The daughter board communication interface 162 may be implemented with the communication interfaces described above in connection with fig. 9-15, and will not be described again.

The functional circuit 163 is located on the substrate 161 to implement the functions corresponding to the daughter board. For example, if the function corresponding to the sub-board is a calculation function, the function circuit 163 is a circuit related to calculation, if the function corresponding to the sub-board is a function of a power supply, the function circuit 163 is a circuit capable of charging and discharging, if the function corresponding to the sub-board is a bluetooth function, the function circuit 163 is a circuit capable of bluetooth communication, and so on.

By adopting the above technical scheme, since the daughter board communication interface 162 includes the low-speed bus pin capable of performing low-speed communication and the high-speed bus pin capable of performing high-speed communication, the daughter board according to the embodiment of the present disclosure has high-speed and low-speed communication capabilities and high-speed and low-speed communication can be performed simultaneously, so that the development platform can support more chips, can perform extension of an application range (for example, video transmission), build more complex applications (for example, develop products such as smart televisions), and enhance the extension capability and development capability of the development platform.

In some embodiments, the daughter board communication interface 162 has pins located on the upper surface of the substrate 161 and pins located on the lower surface of the substrate 161, and the pins on the upper surface and the pins on the lower surface are in electrical communication. For example, for a daughter board located at an intermediate position where a daughter board stack is connected, since it functions to communicate the daughter board above it with the daughter board below it, the daughter board communication interface of the daughter board at the intermediate position needs to have pins located on the upper surface and the lower surface of its substrate in electrical communication with each other to achieve electrical connection. Fig. 17 is a schematic diagram illustrating the connection of a daughter board stack according to an exemplary embodiment, and it can be seen that the daughter board communication interface 162 of the second daughter board has pins on the upper surface of the substrate and pins on the lower surface of the substrate and is in electrical communication with each other, so that the daughter board above the daughter board and the daughter board below the daughter board can be electrically connected together through the second daughter board to form more complex applications and practical training items.

Typically, the executive daughter board is used to perform the action, and in order for the user to be able to view the performed action, the executive daughter board generally needs to be located at the topmost end of the daughter board stack connection, so the executive daughter board may have daughter board communication interface pins going down rather than going up, as shown in fig. 18. The daughter board communication interface of the communication daughter board has an up pin and a down pin because it functions as communication data transmission between the daughter boards, and similarly, the daughter board communication interface of the computation and storage daughter board has an up pin and a down pin because it needs to receive detection data from some daughter boards and control the execution of some daughter boards. A daughter board schematic with an up pin and a down pin for a daughter board communications interface is shown in fig. 19a and 19b, where fig. 19a shows the up pin and fig. 19b shows the down pin.

In some embodiments, the daughter board may further include an electromagnetic shield assembly for protecting the daughter board from electromagnetic interference. Because the use scene of development platform, the daughter board needs to be taken often, and high low-speed communication can produce electromagnetic interference in parallel, consequently through the electromagnetic protection subassembly, can effectively avoid effectively preventing static because of the electromagnetic interference that often takes daughter board and high low-speed communication interference lead to.

The electromagnetic protection component has various realization modes.

One implementation of electromagnetic protection is to use a transparent housing to prevent electromagnetic interference. The components and parts on the daughter board are all covered in this transparent shell, so this transparent shell can avoid the electromagnetic protection that the direct contact daughter board leads to when taking on the one hand, and on the other hand can protect the components and parts on the daughter board effectively to receive the damage of external force. In addition, the transparent structure enables a user to conveniently observe the action performed by the daughter board.

The transparent shell is provided with an opening required by the daughter board. Thus, if there are components (e.g., a dial switch) on the daughter board that require user operation, the user can easily operate the components through the opening.

For the sub-microphone board, the transparent shell is a closed transparent shell, and a sound transmission hole is reserved at the position of the microphone. Therefore, the electromagnetic protection function can be achieved, and the functions of sound reception and dust prevention can be achieved.

Another implementation of electromagnetic protection is to use an electromagnetic protection circuit to ensure stable and safe operation of the daughter board. FIG. 20 is a schematic diagram of an electromagnetic protection circuit for electromagnetically protecting a daughter board, shown in accordance with an exemplary embodiment. The electromagnetic protection circuit is disposed at a position on the daughter board where electromagnetic protection is required. It will be understood by those skilled in the art that the electromagnetic shielding circuitry of fig. 20 is merely illustrative and that virtually any circuit capable of electromagnetic shielding may be used to electromagnetically shield the daughter board.

It should be understood by those skilled in the art that the electromagnetic shielding described herein can be applied to any of the daughter boards described in the present disclosure, including communications daughter boards, patch daughter boards, power daughter boards, computing and memory daughter boards, executive daughter boards, sensor daughter boards, power daughter boards, and the like.

In some embodiments, the functions corresponding to the sub-boards are differentiated by at least one of the size of the sub-boards, the shape of the sub-boards, and the color of the substrate, so as to enhance the recognition of the functions of the sub-boards.

For example, the colors of the substrates 161 of the daughter boards with different functions are different. For example, for a compute and memory daughter board, the color of its substrate may be a black backplane, gold lines, for a communications daughter board, its substrate may be a blue backplane, white lines, for a sensing daughter board, its substrate may be a green backplane, white lines, for an execution daughter board, its substrate may be a yellow backplane, white lines, and so forth.

Or, the daughter boards with different functions have different sizes. For example, for a compute and store daughter board, the size is a first size, for an execute daughter board, the size is a second size, and so on.

Or the daughter boards with different functions have different shapes. For example, for a compute and store daughter board, it has a first shape, for an execute daughter board, it has a second shape, and so on.

Like this, with the help of different colours, the daughter board size of difference, the daughter board shape of difference etc. just can distinguish the function of daughter board directly perceivedly, the degree of discernment of reinforcing daughter board takes more conveniently, is favorable to discovering moreover to pile up and connect the mistake. Taking the above listed daughter board colors as an example, assuming that only one calculating and storing daughter board is needed in the design example, there should be only one black daughter board if the connection is correct, and if a plurality of black daughter boards are found, the connection error can be clearly checked.

In some embodiments, the daughter board may also include magnetic feet 164 disposed on the substrate 161 (as shown in fig. 19 a). The magnetic foot 164 is used for fixing the daughter boards with the daughter board slots of the mother board or fixing the daughter boards with each other in a magnetic adsorption manner, so that the connection stability of the daughter boards is enhanced.

The magnetic foot 164 can be designed for fool-proofing, on one hand, the daughter board can be prevented from being placed in the wrong daughter board slot, and on the other hand, the wrong direction of the daughter board can be prevented from being placed. For example, if the first daughter board slot of the mother board is preset as the master slot, the master device can be placed, but the slave device cannot be placed, then the magnetic pin layout of the calculation and storage daughter board that can be implemented as the master device will be different from the magnetic pin layout of the daughter board that can only be implemented as the slave device, for example, the magnetic pin is different in position on the daughter board, or the magnetic pins are different in shape, for example, all the magnetic pins of the calculation and storage daughter board form a trapezoid, but all the magnetic pins of the daughter board that can only be implemented as the slave device form a parallelogram, so that if the daughter board that can only be implemented as the slave device is placed on the first daughter board, the daughter board cannot be stably placed on the first daughter board slot due to the foolproof design, and thus the user can quickly find the placement error. Fig. 21 and 22 show a foolproof design of the daughter board.

In some embodiments, where the daughter board is a compute and store daughter board, since such daughter boards sometimes require debugging, the compute and store daughter board also includes a debug interface 165 (shown in fig. 21) on the baseboard 161 for implementing debugging of the daughter board. Under the condition that the daughter board needs to be debugged, the debugging content of the daughter board can be downloaded through the downloading interface on the mother board, then the daughter board communication interface of the daughter board is electrically connected with the mother board communication interface of the mother board, and the debugging interface 165 of the daughter board is electrically connected with the debugging interface on the mother board, so that the daughter board can be debugged through the debugging interface 165 by utilizing the debugging content of the daughter board.

For a daughter board having both a daughter board communication interface 162 and a debug interface 165, the daughter board communication interface 162 may be disposed on opposite sides of the substrate 161 from the debug interface 165, e.g., one on the left and the other on the right. Therefore, the stress can be balanced, and pins of the daughter board communication interface 162 and the debugging interface 165 are protected.

In addition, a master-slave switching component can be further included on the compute and memory daughter board for switching between the use of the compute and memory daughter board as a master and slave. The master-slave switching is described in detail in other parts of the present disclosure, and is not described herein again.

In some embodiments, the daughter boards may have different sizes and shapes according to different shapes of components and different usage scenarios, but all the daughter boards with different shapes and sizes may be adapted to the motherboard and may be stacked with other daughter boards. Fig. 23-26 are schematic views of daughterboards of different size and shape shown according to an exemplary embodiment. By making the daughter board expandable in size and shape, the daughter board can be applied to wider scenes, and the expansion capability and development capability of the development platform are enhanced.

FIG. 27 is a schematic diagram of a motherboard shown in accordance with an exemplary embodiment. As shown in fig. 27, the motherboard includes a low-speed bus 273, a high-speed bus 272 and a plurality of daughter board slots 271, each daughter board slot 271 has a motherboard communication interface 2711 thereon, the motherboard communication interface 2711 is adapted to a daughter board communication interface of a daughter board and includes low-speed bus pins for low-speed communication via the low-speed bus 273 and high-speed bus pins for high-speed communication via the high-speed bus 272.

The motherboard communication interface 2711 may be implemented using the communication interfaces described above in connection with fig. 9-15, and will not be described in detail here.

The region of the motherboard where the daughter board slot 271 is located may be referred to as a slot region.

By adopting the technical scheme, the motherboard communication interface on the daughter board slot is matched with the daughter board communication interface of the daughter board and comprises the low-speed bus pin capable of carrying out low-speed communication and the high-speed bus pin capable of carrying out high-speed communication, so that the motherboard according to the embodiment of the disclosure has high-speed and low-speed communication capability and high-speed and low-speed communication can be carried out simultaneously, the development platform can support more chips, the application range can be expanded (for example, video transmission), more complex applications can be built (for example, products such as intelligent televisions are developed), and the expansion capability and the development capability of the development platform are enhanced.

In some embodiments, all of the low speed bus pins on the motherboard communication interface 2711 are connected in series by a low speed bus, and all of the high speed bus pins on the motherboard communication interface 2711 are connected in series by a high speed bus. That is, all the daughter board slots 271 are fully connected by the low-speed bus, and all the daughter board slots 271 are fully connected by the high-speed bus.

The low-speed bus and the high-speed bus enable the development platform to achieve wired communication, and when the daughter board with the wireless communication function is connected to the daughter board slot of the mother board, the development platform can achieve wireless communication, such as zigbee, wifi, bluetooth, 4G/5G and the like. And by means of wireless communication, a plurality of motherboards can be combined for use, and more complex application is formed.

Through the technical scheme, the daughter board is placed on any one of the daughter board slot positions 271, low-speed bus communication and high-speed bus communication can be achieved, bus communication can be achieved without moving the position of the daughter board slot position, the daughter board can be placed in each daughter board slot position flexibly, and convenience in operation is improved. FIG. 28 is a schematic system block diagram of a motherboard in accordance with an exemplary embodiment, wherein the low speed bus and the high speed bus are each fully connected. It should be noted that, in fig. 28, the number and type of pins of each interface and the number and type of external interfaces of the motherboard are merely examples, and the disclosure is not limited thereto.

FIG. 29 is yet another schematic diagram of a motherboard shown in accordance with an exemplary embodiment. As shown in fig. 29, at least one of the daughter board slots 271 includes: a download interface 2712 for downloading debug content for debugging the daughter board; a debug interface 2713 for connecting with a debug interface of the sub board to debug the sub board using the debug content.

The download interface 2712 is an interface capable of connecting with an external apparatus to download debugging content from the external apparatus. For example, the download interface 2712 may be at least one of an ethernet interface, a TYPE-B interface, a MICRO-USB interface, or the like.

The number of pins of the debug interface 2713 and the type thereof can be configured according to an actual debug environment, and for example, it may be a debug interface shown in fig. 28.

By adopting the technical scheme, the debugging content can be downloaded and the daughter board can be debugged by utilizing the debugging content.

In some embodiments, as shown in FIG. 29, the motherboard may also include a USB-HUB chip and at least one high speed communication interface 2714. The high-speed communication interface 2714 is used to connect an external device that needs to perform high-speed communication, and the external device refers to an electronic device other than a motherboard, such as an upper computer, a USB device, and a keyboard. The USB-HUB chip is used to transfer information between the high-speed communication interface 271 and the motherboard communication interface 2711. With this configuration, it is possible to connect with an external USB device for USB communication.

In some embodiments, some of the plurality of daughter board slots 271 may be configured as master daughter board slots for connection with a daughter board functioning as a master device in the case of high speed communications. For example, the daughter board slot in the upper left corner of FIG. 29 may be set as the master daughter board slot. The main control daughter board slot is a USB-HOST interface to indicate the main control role. The USB-HOST interface is connected with other non-master control daughter board slots through branch lines. The non-master daughter board slot is also called a slave DEVICE slot, and the interface of the non-master daughter board slot is a USB-DEVICE interface.

Through setting up master control daughter board trench, when carrying out high-speed communication, the daughter board that plays the master control effect need be placed in master control daughter board trench and just can realize high-speed communication's master-slave control, and this kind of configuration can reduce the wiring in addition, reduce cost.

In some embodiments, the motherboard may further include an electromagnetic protection circuit for performing electromagnetic protection on the motherboard to effectively prevent static electricity. Regarding electromagnetic shielding, detailed description has been made in other parts, and detailed description is omitted here.

In some embodiments, the motherboard may further include a magnetic foot 2715 disposed on each daughter board slot 271, where the magnetic foot is used to fix the daughter board to the daughter board slot 271 in a magnetic absorption manner, so as to enhance the connection stability.

The magnetic pins 2715 can be designed to be fool-proof to avoid errors in the placement position and the placement direction of the daughter board. The main board slot and the sub board which can not be used as the main equipment can be flexibly placed in any one of the sub board slots due to no master-slave relationship during low-speed communication, and the sub board which can be used as the main equipment can be placed in the main control sub board slot due to the master-slave relationship during high-speed communication, while the sub board which can not be used as the main equipment needs to be placed in the non-main control sub board slot. Foolproof designs have been described in detail in other portions of this disclosure and are not described in detail herein.

In some embodiments, as shown in fig. 29, the motherboard may include an operation control switch 2716 for controlling the activation and deactivation of the motherboard. Therefore, the motherboard can be started when the application is required to be built, and the motherboard can be closed when the application is not required to be built, so that the energy consumption can be saved.

In some embodiments, as shown in fig. 29, the motherboard can also include an alarm component 2717 for false alarms. Thus, an alarm can be given when the motherboard has an error. The alarm component 2717 may be in the form of an indicator light or a buzzer.

FIG. 30 is a schematic diagram of a stand-alone motherboard shown in accordance with an exemplary embodiment. The separate motherboard is capable of performing the functions of the motherboard described in connection with fig. 27 to 29.

As shown in fig. 30, the separate motherboard includes at least one daughter board slot and an interface region.

The interface area comprises: a high-speed communication interface 301 for connecting an external device that needs high-speed communication; and the download interface 303 is used for downloading the debugging content of the daughter board. The high-speed communication interface 301 and the download interface 303 are described in detail in other parts of the present disclosure, and are not described herein again.

The interfaces in the interface region may be arranged on the upper surface and/or the side surfaces of the separate motherboard. If arranged on the side, the individual mother plates can be downsized.

The daughter board slot position comprises: a motherboard communication interface 302, wherein the motherboard communication interface 302 is electrically connected with the high-speed communication interface 301 through a high-speed bus, the motherboard communication interface 302 is adapted to a daughter board communication interface of a daughter board and is used for including a low-speed bus pin and a high-speed bus pin, the low-speed bus pin is electrically connected with a low-speed bus for low-speed communication, and the high-speed bus pin is electrically connected with a high-speed bus for high-speed communication; and the mother board debugging interface 304 is adapted to a daughter board debugging interface of a daughter board to be debugged and used for debugging the daughter board to be debugged by using the debugging content of the daughter board. By means of the download interface 303 and the debug interface 304, the download and debug functions can be implemented by a separate motherboard.

The independent motherboard can be used independently, so that the independent motherboard has more flexibility and more application scenes. For example, an independent motherboard can be placed on the smart car as a main control board; the independent mother board can be placed on the machine dog, and different daughter boards are placed on the independent mother board, so that different functions are added to the machine dog; an independent motherboard may be used to simulate an NFC swipe card; a separate motherboard may be placed outdoors to simulate a data collector or the like.

By adopting the above technical scheme, because the motherboard communication interface 302 on the daughter board slot is adapted to the daughter board communication interface of the daughter board and includes the low-speed bus pin capable of performing low-speed communication and the high-speed bus pin capable of performing high-speed communication, the standalone according to the embodiment of the present disclosure has high-speed and low-speed communication capabilities and can perform high-speed and low-speed communication simultaneously, which enables the development platform to support more chips, can perform extension of application range (for example, video transmission), build more complex applications (for example, develop products such as smart televisions), and enhance the extension capability and development capability of the development platform.

In some embodiments, the separate motherboard may include a separate power supply for supplying power. The independent power supply can be a rechargeable battery, a solar panel and a power supply daughter board described in the disclosure. The independent motherboard can be used independently without being powered by a direct-current power supply through the independent power supply.

In some embodiments, a power interface 305 for connecting a power source may also be included on the interface region, as shown in fig. 30. By means of the power interface 305, the separate motherboard can be connected to a dc power supply to supply power to the separate motherboard or to charge the separate power supply on the separate motherboard.

FIG. 31 is yet another schematic diagram of a separate motherboard shown in accordance with an exemplary embodiment. Also included on the interface region are connection ports 306 for enabling connection between individual motherboards, as shown in fig. 31. Connector 306 may be located on an upper surface of the individual motherboard or may be located on at least one side of the individual motherboard. If located on the side, the connection between the individual motherboards is facilitated and the size of the individual motherboards can be reduced.

By adopting the connection port 306, a plurality of independent motherboards can be combined for use, and the independent motherboards and the motherboards described in conjunction with fig. 27 to 29 can also be combined for use, so that the motherboards with different functions can be spliced into a motherboard form, and more complex applications can be conveniently built. When these motherboards are connected together, the bus of the motherboards can be communicated, and bus communication is realized, including high-speed bus communication and low-speed bus communication.

In some embodiments, the independent motherboard may further include electromagnetic protection circuitry for electromagnetically protecting the independent motherboard. The electromagnetic shielding has already been described in detail in other parts and will not be described in detail here.

In some embodiments, as shown in fig. 30, the independent motherboard may further include a magnetic foot 307 disposed on the daughter board slot, and the magnetic foot is used to fix the daughter board to the daughter board slot by magnetic attraction. The magnetic feet 307 may be fool-proof. The magnetic foot has been described in detail in other parts, and is not described in detail here.

In some embodiments, as shown in fig. 30, the interface area may further include an operation control switch 308 for controlling the activation and deactivation of the independent motherboard. Therefore, the independent board can be started when the application is required to be built, and the independent motherboard is closed when the application is not required to be built, so that the energy consumption can be saved.

In some embodiments, as shown in FIG. 30, the standalone motherboard may also include an alarm component 309 for false alarms. Thus, an alarm can be given when the independent motherboard has an error. The alarm component 308 may be in the form of an indicator light or a buzzer.

Figure 32 is a schematic diagram of a daughter board shown in accordance with an exemplary embodiment. The daughter board can be a communication daughter board for switching communication modes, and can also be a calculation and storage daughter board for switching master-slave modes.

As shown in fig. 32, the daughter board includes a substrate 321, a daughter board communication interface 322, a functional circuit 323, and a mode switching component 324.

The substrate 321 is a carrier for the daughter board communication interface 322, the functional circuitry 323, and the mode switching component 324, which may be any type of substrate, such as a printed wiring board.

The daughter board communication interface 322 is located on the substrate 321 and is compatible with a motherboard communication interface on a daughter board slot of a motherboard and/or with communication interfaces on other daughter boards.

The daughter board communication interface 322 includes a low-speed bus pin for low-speed communication and a high-speed bus pin for high-speed communication.

The daughter board communication interface 322 may be implemented with the communication interfaces described above in connection with fig. 9-15, and will not be described again.

The functional circuit 323 is located on the substrate 321 and is used to implement a function corresponding to the daughter board. The functional circuit 323 has been described in detail in other parts, and is not described here in detail.

The mode switching element 324 is disposed on the substrate 321 for switching the operation mode of the functional circuit 323.

By adopting the above technical scheme, since the daughter board communication interface 322 includes the low-speed bus pin capable of performing low-speed communication and the high-speed bus pin capable of performing high-speed communication, the daughter board according to the embodiment of the present disclosure has high-speed and low-speed communication capabilities and high-speed and low-speed communication can be performed simultaneously, so that the development platform can support more chips, can perform extension of an application range (for example, video transmission), build more complex applications (for example, develop products such as smart televisions), and enhance the extension capability and development capability of the development platform.

In some embodiments, where the daughter board is a compute and store daughter board, the mode switching component 324 is used to switch between the compute and store daughter board being used as a master and a slave. For example, in the case where the compute and memory daughter board currently needs to function as a master, the mode switch component 324 may switch the compute and memory daughter board to the master mode, and in the case where the compute and memory daughter board currently needs to function as a slave, the mode switch component 324 may switch the compute and memory daughter board to the slave mode. Thus, the computing and storage sub-board can be ensured to work in a correct master-slave mode.

FIG. 33 is a block diagram illustrating a schematic functional structure of a compute and memory daughter board in accordance with an exemplary embodiment. As shown in fig. 33, the mode switch component 324 includes a mode switch and a master slave detection pin located on the daughter board communication interface 322. And the master-slave detection pin is used for outputting a detection signal indicating whether the calculation and storage daughter board needs to be used as a master device or a slave device to the mode switch. And the mode switch is used for switching to be connected with a slave device interface of the USB-HUB chip of the calculation and storage daughter board when the detection signal indicates that the calculation and storage daughter board needs to be used as the master device, and switching to be connected with the calculation and storage chip GD32 of the calculation and storage daughter board when the detection signal indicates that the calculation and storage daughter board needs to be used as the slave device. The mode switch can be in the form of a dial switch, a knob switch, a key and the like. In fig. 33, the upward interface refers to a portion of the same interface located on the upper surface of the substrate, and the downward interface refers to a portion of the same interface located on the lower surface of the substrate; in addition, an interface including pins of I2C, UART1, and the like is a communication interface, and an interface including pins of a network port, VCC, and the like is a debug interface.

For example, if the master/slave detection pin receives a high level, which indicates that the compute and store daughter board needs to be used as a master device, in this case, the master/slave detection pin outputs a high level to the mode switch, and the mode switch switches to the slave device interface (i.e., USB-H1 in the figure) of the USB-HUB chip built in the compute and store daughter board, which indicates that the incoming signals are slave device signals, and the compute and store daughter board operates as a USB master device. If the master-slave detection pin receives a low level, it indicates that the calculation and storage daughter board needs to be used as a slave device, in this case, the master-slave detection pin outputs a low level to the mode switch, the mode switch is directly connected to the calculation and storage chip of the calculation and storage daughter board (i.e., switched to the USB-D in the figure), and at this time, the calculation and storage daughter board works as a USB slave device.

The calculation and storage daughter board works in a master-slave switching mode, wiring can be simplified, and practicability is enhanced.

In some embodiments, where the daughter board is a communications daughter board, the mode switching component 324 is used to switch between operating the communications daughter board in a bus communications mode and a non-bus communications mode. The switching of the bus communication mode can solve the communication problems that when the communication sub-board is used as the main control device, data transmission needs to be carried out with the main board, and an interface is a UART interface.

The mode switching component 324 is a mode switch. The mode switch can be in the form of a dial switch, a knob switch, a key and the like. Under the condition that the mode switch is switched to the bus communication mode switch bit, the communication daughter board is connected with the mother board of the development platform to perform bus data transmission; in the case where the mode switch is switched to the non-bus communication mode switch bit, the communication daughter board is not in communication with the mother board and is capable of providing bus communication for other daughter boards stacked vertically above the communication daughter board.

Fig. 34 is a schematic functional block diagram of a communication daughter board shown according to an exemplary embodiment. The meaning of the up interface and the down interface in fig. 34 is similar to that in fig. 33. As shown in fig. 34, the communication mode is manually switched by a 1-bit DIP switch (i.e., a dial switch).

In the bus communication mode, the switch 1 is in the on state, and the switch 2 is in the off state, at this time, communication data is transmitted by the UART1 serial port, and the communication sub board can be connected to the main board through the UART interface to perform bus data transmission. In the non-bus communication mode, the change-over switch 1 is in an off state, and the change-over switch 2 is in an on state, at this time, the motherboard of the development platform only supplies power to the communication daughter board, and the communication daughter board does not supply I2C communication to the motherboard of the development platform for other daughter boards on the longitudinal stack of the communication daughter board, but can supply I2C communication to the communication daughter board for other daughter boards. Therefore, when the communication sub-board works as the main control device, the bus communication mode is switched to be capable of communicating with the mother board through the UART serial port, and when the communication sub-board only works as the wireless communication, the bus communication mode is switched to be the non-bus communication mode.

In some embodiments, the daughter board further includes an electromagnetic shielding assembly for preventing the daughter board from electromagnetic interference, which effectively prevents static electricity. The electromagnetic protection component can be a transparent shell and/or an electromagnetic protection circuit, wherein an opening required by the daughter board is reserved on the transparent shell. The electromagnetic shielding has been described in detail in other parts of the present disclosure and will not be described in detail here.

In some embodiments, the daughter board further includes a magnetic foot disposed on the substrate 321, and the magnetic foot is used for fixing the daughter board to a daughter board slot of a mother board of the development platform or fixing the daughter board to the mother board by means of magnetic attraction. The magnetic attraction foot is designed to be foolproof. The magnetic foot has been described in detail in other parts of the present disclosure, and is not described in detail herein.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A daughter board, comprising:

a substrate;

the daughter board communication interface is positioned on the substrate and is matched with a mother board communication interface on a daughter board slot position of the mother board and/or a communication interface on other daughter boards, the daughter board communication interface comprises a low-speed bus pin and a high-speed bus pin, the low-speed bus pin is used for carrying out low-speed communication, and the high-speed bus pin is used for carrying out high-speed communication;

and the functional circuit is positioned on the substrate and used for realizing the function corresponding to the daughter board.

2. The daughter board of claim 1, wherein said daughter board communication interface has pins located on an upper surface of said substrate and pins located on a lower surface of said substrate, and wherein said pins on said upper surface and said pins on said lower surface are in electrical communication.

3. The daughter board of claim 1, further comprising an electromagnetic shield assembly for protecting said daughter board from electromagnetic interference.

4. The daughter board according to claim 3, wherein said electromagnetic shielding component is a transparent housing and/or an electromagnetic shielding circuit, wherein said transparent housing is left with an opening for said daughter board.

5. The daughter board of claim 4, wherein said daughter board is a microphone daughter board, then said transparent housing is a closed transparent housing, and a sound transmission hole is left at said microphone.

6. The daughter board of claim 1, wherein the functions corresponding to said daughter board are differentiated by at least one of daughter board size, daughter board shape, substrate color.

7. The daughter board of claim 1, further comprising a magnetic foot disposed on the substrate, wherein the magnetic foot is used for fixing the daughter board to the daughter board slot of the mother board and/or the other daughter boards by magnetic absorption.

8. The daughter board of claim 7, wherein said magnetic foot is a foolproof magnetic foot.

9. The daughter board of any one of claims 1 to 8, wherein the daughter board is a compute and memory daughter board, the daughter board further comprising a debug interface on the baseboard for enabling debugging of the daughter board, wherein the daughter board communication interface and the debug interface are disposed on opposite sides of the baseboard.

10. The daughter board of claim 9, further comprising a master-slave switching component on said compute and storage daughter board for switching between said compute and storage daughter board being used as a master and slave.