CN113918095B - Hybrid cross storage method and device for data and electronic equipment - Google Patents
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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Abstract
The application is applicable to the technical field of data storage, and provides a hybrid cross storage method and device for data and electronic equipment, wherein the method comprises the following steps: acquiring data to be stored; determining a head address of an address area corresponding to the type of data to be stored and the number n of cache units occupied by the data to be stored in the cache area; writing the first address, the number n of the cache units and the data to be stored into a cache area; extracting a first address and the number n of the cache units from the cache area, and extracting data to be stored from the cache area according to the number n of the cache units; and writing the data to be stored into an address area indicated by the head address. The embodiment of the application realizes the mixed cross storage of multiple types of data through one buffer area, and remarkably reduces the occupied amount of the memory.
Description
Technical Field
The application belongs to the technical field of data storage, and particularly relates to a hybrid cross storage method and device for data and electronic equipment.
Background
The power module in the electric automobile and the charging pile thereof often needs to locally store a plurality of continuous data, and the data needing to be stored continuously is more than one type, such as storage fault, running time, working time, voltage and current, and the like, and the data length can comprise 8 bits, 16 bits, 32 bits, 64 bits, and the like.
In order to enable continuous storage of these different types of data, the prior art generally opens up different address areas for different types of data for separate storage processing. However, since each address area needs to be provided with an independent corresponding buffer area, when the types of data stored continuously are more, the number of the buffer areas is also more, a large amount of memory is occupied, and the complexity and code redundancy of the whole storage process are high.
Disclosure of Invention
In view of the above, the embodiments of the present application provide a hybrid cross storage method and apparatus for data, and an electronic device, so as to solve the problems in the prior art that when multiple types of data are continuously stored, the buffer area is more, and a large amount of memory is occupied.
A first aspect of an embodiment of the present application provides a hybrid cross storage method for data, including:
acquiring data to be stored;
determining a head address of an address area corresponding to the type of data to be stored and the number n of cache units occupied by the data to be stored in the cache area; wherein, each type of data corresponds to an address area for storing the type of data, and n is a positive integer;
writing the first address, the number n of the cache units and the data to be stored into a cache area;
extracting a first address and the number n of the cache units from the cache area, and extracting data to be stored from the cache area according to the number n of the cache units;
and writing the data to be stored into an address area indicated by the head address.
Optionally, each k bits in the buffer form a buffer unit, and k is the number of bits in the buffer; writing the first address, the number n of the cache units and the data to be stored into the cache area, wherein the method comprises the following steps:
according to the length of the head address and the number of bits of the buffer area, determining the number m of buffer units occupied by the head address in the buffer area, and distributing m buffer units from the buffer area to store the head address;
allocating a cache unit to store the number n of the cache units from the cache area;
allocating n cache units to store data to be stored in the cache area;
wherein k and m are positive integers.
Optionally, each address area includes a data area; writing data to be stored into an address area indicated by a head address, comprising:
searching the length of the data area and the writing index value of the address area indicated by the head address; the writing index value is used for indicating the initial storage position of the data to be stored in the data area;
writing the data to be stored into the data area according to the writing index value, and updating the writing index value according to the end storage position of the data to be stored in the data area; and if the updated write index value is greater than or equal to the length of the data area, setting the updated write index value to zero.
Optionally, searching the data area length and the writing index value of the address area indicated by the head address includes:
searching the length of the data area and the writing index value of the address area indicated by the head address from a preset address area information table; the address area information table comprises a first address of each address area, a length of a data area and a writing index value;
correspondingly, updating the writing index value according to the end storage position of the data to be stored in the data area comprises the following steps:
and updating the writing index value in the address area information table according to the storage position of the data to be stored in the tail end of the data area.
Optionally, each address area further includes an index area, and the lengths of the data areas in the same address area are consistent with those of the index areas; writing data to be stored into an address area indicated by a head address, further comprising:
writing the updated written index value into the index area; the initial storage position of the updated writing index value in the index area corresponds to the initial storage position of the data to be stored in the data area.
Optionally, after performing the operation of writing the data to be stored into the data area, the method further includes:
judging whether the data to be stored is successfully written;
if the writing of the data to be stored fails, receiving a processing instruction input by a user, and correspondingly processing the data to be stored according to the processing instruction.
Optionally, the processing instructions include: re-writing instructions and skipping writing instructions; and correspondingly processing the data to be stored according to the processing instruction, including:
if a rewriting instruction is received, the data to be stored is rewritten in the data area;
if the skip writing instruction is received, writing of the data to be stored is skipped.
A second aspect of an embodiment of the present application provides a hybrid cross storage device for data, including:
the acquisition module is used for acquiring data to be stored;
the determining module is used for determining the head address of the address area corresponding to the type of the data to be stored and the number n of the cache units occupied by the data to be stored in the cache area; wherein, each type of data corresponds to an address area for storing the type of data, and n is a positive integer;
the cache writing module is used for writing the head address, the number n of the cache units and the data to be stored into the cache area;
the cache extraction module is used for extracting a first address and the number n of the cache units from the cache area and extracting data to be stored from the cache area according to the number n of the cache units;
and the storage writing module is used for writing the data to be stored into the address area indicated by the head address.
A third aspect of the embodiments of the present application provides an electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the hybrid cross-storage method of data as described above when the computer program is executed by the processor.
A fourth aspect of the embodiments of the present application provides a computer readable storage medium storing a computer program which when executed by a processor performs the steps of a hybrid interleaving method of data as described above.
Compared with the prior art, the embodiment of the application has the beneficial effects that:
according to the embodiment of the application, the first address of the address area corresponding to the data and the number of the buffer units occupied by the data in the buffer area are written into the buffer area together with the data when the data is buffered, so that the address area into which the data is to be put can be determined according to the first address when the data is extracted from the buffer area, and the data can be completely extracted from the buffer area according to the number of the buffer units occupied by the data in the buffer area. The embodiment of the application realizes the mixed cross storage of multiple types of data through one buffer area, and remarkably reduces the occupied amount of the memory.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a hybrid cross-storage method for data according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an address area according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a buffer area according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a flow of writing data into a data area according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a hybrid cross-storage device for data according to an embodiment of the present application;
fig. 6 is a schematic diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
In order to illustrate the technical scheme of the application, the following description is made by specific examples.
In the power module in the electric automobile and the charging pile thereof, local storage may need to be performed on a plurality of continuous data, and the storage content may be: equipment failure, run time, on time, voltage current, etc. Different types of data may also be inconsistent in length, including 8 bits, 16 bits, 32 bits, 64 bits, and so forth. And these data are all intended to be stored continuously, i.e. continuously in case of an abnormal situation of the local storage device, or in case of a fault, the voltage current value, etc. In order to be suitable for continuously storing a plurality of different types of data, the traditional method opens up different address areas for respectively storing and processing the different types of data. Because the traditional method does not carry out unified and normative self-adaptive processing on all types of data, the more the data types are, the more the number of the buffer areas is, the large occupied memory is, the complexity is high, and the code redundancy is caused. Therefore, the scheme provides a mixed cross storage solution for multiple types of data, which can well solve the problem of storage of continuous multiple data with inconsistent types, and enable the storage process to be self-adaptive to various different types of data.
Referring to fig. 1, an embodiment of the present application provides a hybrid cross storage method of data, including the steps of:
step S101, obtaining data to be stored.
In the embodiment of the application, the method can be applied to the power supply module in the electric automobile and the charging pile thereof. The data to be stored may be data related to the power module including, but not limited to, one or more of a fault condition, run time, on time, and voltage current. It should be noted that the method may also be applied to other scenarios where multiple types of data need to be stored to store related data, which is not limited by the embodiment of the present application.
Step S102, determining the head address of an address area corresponding to the type of data to be stored and the number n of cache units occupied by the data to be stored in a cache area; wherein each type of data corresponds to an address area for storing the type of data, and n is a positive integer.
In the embodiment of the application, different address areas are opened up in the IIC memory aiming at different types of data so as to respectively store the different types of data continuously. Each address area has a unique head address so as to identify the address area, and the head address of each address area is not repeated. Referring to fig. 2, region 1, address areas 2, … …, and address area e are used to store different types of data, respectively. The head address of the area 1 is addr1, the head address of the address area 2 is addr2, the head address of the address area e is addre, and addr1, addr2, … … and addre are all different.
Since the length of each type of data is fixed, the length of the data to be stored can be determined according to the type of the data to be stored, and the number n of the cache units occupied by the data to be stored in the cache region can be calculated. For example, for a 16-bit buffer, every 16 bits form a buffer unit, if the length of the data is 64, 4 buffer units are needed to store the data, and n is equal to 4; if the length of the data is 32, n is equal to 2; if the data is less than 16 bits in length, such as 8 bits, then n is equal to 1.
Step S103, writing the head address, the number n of the buffer units and the data to be stored into the buffer area.
In the embodiment of the application, the first address, the number n of the cache units and the data to be stored are written into the cache area at the same time, so that the complete data can be conveniently extracted from the cache area and written into the corresponding address area, and the mixed cross storage of different types of data is realized by using one cache area.
Step S104, extracting the first address and the number n of the buffer units from the buffer area, and extracting the data to be stored from the buffer area according to the number n of the buffer units.
In the traditional method, as each data type is provided with one buffer area, the data types in the same buffer area are the same, and the data length is the same, the whole data can be obtained by extracting the data of the buffer units with fixed number and the data can be put into the corresponding address area. In the embodiment of the application, as different types of data are written into one buffer area, when the data are extracted, firstly, the address area into which the data should be put is determined according to the first address, and then, n buffer unit data are extracted according to the number n of buffer units occupied by the data in the buffer area, so that complete data are obtained.
Step S105, writing the data to be stored into the address area indicated by the head address.
Therefore, in the embodiment of the application, the first address of the address area corresponding to the data and the number of the buffer units occupied by the data in the buffer area are written into the buffer area together with the data when the data is buffered, so that the address area into which the data is to be put can be determined according to the first address when the data is extracted from the buffer area, and the data can be completely extracted from the buffer area according to the number of the buffer units occupied by the data in the buffer area. The embodiment of the application realizes the mixed cross storage of multiple types of data through one buffer area, and remarkably reduces the occupied amount of the memory.
In one possible implementation, each k bits in the buffer form a buffer unit, where k is the number of bits in the buffer; in step S103, the first address, the number n of cache units, and the data to be stored are written into the cache area, which can be described as follows:
determining the number m of buffer units occupied by the head address in the buffer area according to the length of the head address and the number of bits of the buffer area, and distributing m buffer units in the buffer area to store the head address;
allocating a cache unit to store the number n of the cache units from the cache area;
allocating n cache units to store data to be stored in the cache area;
wherein k and m are positive integers.
For example, referring to fig. 3, the number of buffer areas is 16, and the first address length of each address area is 32 bits. The cache writing process of the data to be stored can be as follows:
first dividing the length of the first address by the number of bits of the buffer area by 32 to obtain the number m=2 of buffer units occupied by the first address in the buffer area, and allocating 2 buffer units from the buffer area to store the first address, wherein the first buffer unit stores the lower 16 bits of the first address, and the second buffer unit stores the upper 16 bits of the first address. Then, one cache unit is allocated from the cache area to store the number n of cache units. And finally, allocating n cache units in the cache area to store the data to be stored. It should be noted that: the number of the buffer zone bits can be set according to the requirement, and can be set to 8 bits, 16 bits and the like, and the specific buffer flow can be realized according to the above.
A writing process of writing the extracted data into the corresponding address area will be described below.
In some embodiments, referring to FIG. 2, each address region includes a data region. In step S105, writing the data to be stored in the address area indicated by the first address may include the following steps one to two:
step one, searching the length of a data area and a writing index value of an address area indicated by a head address; the writing index value is used for indicating the initial storage position of the data to be stored in the data area;
writing the data to be stored into the data area according to the writing index value, and updating the writing index value according to the storage position of the data to be stored at the tail end of the data area; and if the updated write index value is greater than or equal to the length of the data area, setting the updated write index value to zero.
In the embodiment of the present application, the updated write index value is used to indicate the initial storage position of the next data to be stored in the data area. If the updated write index value is greater than or equal to the length of the data area, the updated write index value is set to zero, so that the cyclic storage of the data in the data area is realized.
In one possible implementation manner, the length of the data area and the write index value of the address area indicated by the lookup header address in the first step may be described in detail as follows:
searching the length of the data area and the writing index value of the address area indicated by the head address from a preset address area information table; the address area information table comprises a first address of each address area, a length of a data area and a writing index value;
accordingly, updating the write index value according to the storage position of the data to be stored at the end of the data area can be described as follows:
and updating the writing index value in the address area information table according to the storage position of the data to be stored in the tail end of the data area.
For example, the preset address area information table may be shown in table 1, where the address area information table includes the first address of each address area, the length of the data area, the length of the index area, and the written index value.
TABLE 1 Address area information table
| Head address | Data area length | Index zone length | Writing index values |
| addr1 | DataLen1 | IndexLen1 | WIndex1 |
| addr2 | DataLen2 | IndexLen2 | WIndex2 |
| ... | ... | ... | ... |
| addre | DataLene | IndexLene | WIndexe |
In the address area information table, the head address, the data area length, the index area length are known, the number e of rows of the table is also known to the user layer, and the written index value is a variable updated in real time. For example, when a certain length of 32 bits of data is stored in an 8-bit data area, 4 storage units are allocated from the data area to store the data, the number of storage units byte len=4 required for storing one data in the data area is defined, if the table lookup is assumed to obtain a write index value of 4, the 4 th storage unit in the data area is used as a starting storage position to store the data, the end storage position is 4+byte len=8, the starting storage position of the next data is 8, and the write index value in the table is updated to 8. Assuming that the data area length of the data area is 28, when the updated write index value is 28, the write index value is set to 0, so that circular storage is realized.
In addition, after the length of the data area and the written index value of the address area indicated by the first address are queried from the preset address area information table, the number of lines of the query result in the address area information table can be judged, if the number of lines exceeds the total number e of lines of the address area information table, query errors are judged, and the data can be selected to be skipped from being queried or re-queried according to the instruction of the user.
In one possible implementation, referring to fig. 2, each address area further includes an index area, and the data area in the same address area is consistent with the length of the index area. In step S105, writing the data to be stored in the address area indicated by the head address may further include step S:
writing the updated written index value into an index area; the initial storage position of the updated writing index value in the index area corresponds to the initial storage position of the data to be stored in the data area.
When the power module is powered up again after fault recovery, in order to prevent the previously stored data from being overwritten, an index area is provided in the address area to store the write index value in real time to continue to be stored from the position at the time of power-off after power-up. In the same address area, the data area and the index area are identical in size, the ByteLen is also identical, and the initial storage position of the index value of the data to be stored in the index area corresponds to the initial storage position of the data to be stored in the data area, so that the written index value is circularly stored in the index area, the written index value is prevented from being always stored in the same position of the index area, and the service life of the index area is prolonged. Illustratively, after a certain data is written into the data area of the address area 1, the storage location of the data at the end of the data area is determined as an updated index value, and the updated index value is cyclically written into the index area of the address area 1.
It will be appreciated that the index region lengths of the different address regions may be the same or different and the data region lengths of the different address regions may be the same or different. Also, since different types of data may be the same or different in length, the ByteLen of different address areas may be the same or different.
In the process of writing the data to be stored into the data area, the writing failure may also occur due to a program error, an abnormal device, and the like, and a processing manner in the case of the writing failure is described below.
In one possible implementation manner, after performing the operation of writing the data to be stored into the data area in step S105, the method may further include:
judging whether the data to be stored is successfully written;
if the writing of the data to be stored fails, receiving a processing instruction input by a user, and correspondingly processing the data to be stored according to the processing instruction.
Optionally, in one possible implementation, the processing instructions include: the write command is rewritten and the write command is skipped. If a rewriting instruction is received, the data to be stored is rewritten in the data area; if the skip writing instruction is received, writing of the data to be stored is skipped.
In the embodiment of the application, similar to the processing mode of the data to be stored, after the operation of writing the updated writing index value into the index area is executed, whether the updated writing index value is successfully written or not can be judged, and if the updated writing index value is failed to be written, the writing index value can be selected to be written into the index area again or the writing of the writing index value can be skipped according to the processing instruction input by the user.
According to the above, referring to fig. 4, the embodiment of the present application further provides a detailed implementation flow of writing the data of the buffer into the address area, as follows:
(1) Extracting the first address and the number n of the cache units from the cache area.
(2) And according to the lookup table of the head address, extracting the number of the information table rows where the head address is located.
(3) Judging whether the number of the information table lines where the table lookup result is located exceeds the limit, if yes, carrying out overrun processing, namely selecting to skip the group of data or re-table lookup according to a user instruction; if not, executing (4).
(4) And extracting the length DataLen of the data area, the length IndexLen of the index area and the write index value Windex in the information table according to the table look-up result of the first address.
(5) And according to the number n of the cache units, sequentially extracting n cache unit data and writing the data into the data area of the corresponding address area.
(6) Judging whether the data is written successfully or not, and executing the step (7) if the data is written successfully; if the writing is not successful, the processing mode of the user layer needs to be judged, and the data is skipped to be written or rewritten.
(7) The write index value of the address area is increased by ByteLen. And if the updated write index value is greater than or equal to the data area length DataLen, setting zero.
(8) Judging whether all n data are written, if yes, executing the step (9); otherwise, jumping to (5) re-extracting the n cache unit data and writing the n cache unit data into the data area of the corresponding address area.
(9) And writing the updated writing index value into the index area.
(10) Judging whether the writing of the index value into the index area is successful or not, and if so, executing the step (11); if the index value fails, the processing mode of the user layer needs to be judged, and the index value is selected to be written into the index area again or the writing of the index value is skipped.
(11) If the skip writing of the index value or the writing of the index value into the index area is completed, judging whether the data in the buffer area is completely read, if the data in the buffer area is still contained, jumping to (1) the process of reading, storing and index storing of the next group of data; and if the data in the buffer area is completely read, ending the current flow.
The embodiment of the application has the following effects:
1. the method comprises the steps of opening up different address areas for different types of data, and registering information of the first address of the address area, the length of the data area and the length of the index area in a unified table. 2. For continuously stored data, a data area and an index area are created in an address area, and the data and index values are stored in real time. 3. The same buffer is used for different types of data storage, and the buffer can be adaptive to the storage of different types of data. 4. And the first address is stored in the buffer area, so that the position where the data should be stored can be determined, and meanwhile, the length of the data area and the length of the index area of the address area can be searched according to the first address, and the cyclic storage of the data and the writing index is performed. 6. The number of the buffer units occupied by the data stored in the buffer area can be used for extracting complete data according to the number of the buffer units. 7. The multiplexing performance is strong, the self-adaption is strong, and the self-adaption continuous cross-mixed storage of different types of data can be realized.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present application.
Referring to fig. 5, an embodiment of the present application provides a hybrid cross-storage device for data, the device 50 including:
the acquiring module 51 is configured to acquire data to be stored.
The determining module 52 is configured to determine a first address of an address area corresponding to a type of data to be stored, and a number n of cache units occupied by the data to be stored in the cache area; wherein each type of data corresponds to an address area for storing the type of data, and n is a positive integer.
The cache writing module 53 is configured to write the first address, the number n of cache units, and the data to be stored into the cache area.
The buffer extraction module 54 is configured to extract the first address and the number n of buffer units from the buffer area, and extract the data to be stored from the buffer area according to the number n of buffer units.
The storage writing module 55 is configured to write data to be stored into an address area indicated by the head address.
Optionally, in one possible implementation manner, each k bits in the buffer area form a buffer unit, where k is the number of bits in the buffer area; the cache writing module 53 is configured to:
determining the number m of buffer units occupied by the head address in the buffer area according to the length of the head address and the number of bits of the buffer area, and distributing m buffer units in the buffer area to store the head address;
allocating a cache unit to store the number n of the cache units from the cache area;
allocating n cache units to store data to be stored in the cache area;
wherein k and m are positive integers.
Optionally, in a possible implementation, each address area includes a data area; the storage writing module 55 is configured to:
searching the length of the data area and the writing index value of the address area indicated by the head address; the writing index value is used for indicating the initial storage position of the data to be stored in the data area;
writing the data to be stored into the data area according to the writing index value, and updating the writing index value according to the end storage position of the data to be stored in the data area; and if the updated write index value is greater than or equal to the length of the data area, setting the updated write index value to zero.
Optionally, in one possible implementation, the storage writing module 55 is specifically configured to:
searching the length of the data area and the writing index value of the address area indicated by the head address from a preset address area information table; the address area information table comprises a first address of each address area, a length of a data area and a writing index value; and updating the writing index value in the address area information table according to the storage position of the data to be stored at the end of the data area.
Optionally, in a possible implementation manner, each address area further includes an index area, and the data area in the same address area is consistent with the length of the index area; the memory write module 55 is further configured to:
writing the updated written index value into the index area; the initial storage position of the updated writing index value in the index area corresponds to the initial storage position of the data to be stored in the data area.
Optionally, in one possible implementation, after performing the operation of writing the data to be stored into the data area, the storage writing module 55 is further configured to:
judging whether the data to be stored is successfully written;
if the writing of the data to be stored fails, receiving a processing instruction input by a user, and correspondingly processing the data to be stored according to the processing instruction.
Optionally, in one possible implementation, the processing instructions include: re-writing instructions and skipping writing instructions; the memory write module 55 is further configured to:
if a rewriting instruction is received, the data to be stored is rewritten in the data area;
if the skip writing instruction is received, writing of the data to be stored is skipped.
Fig. 6 is a schematic diagram of an electronic device 60 according to an embodiment of the present application. As shown in fig. 6, the electronic device 60 of this embodiment includes: a processor 61, a memory 62 and a computer program 63 stored in the memory 62 and executable on the processor 61, such as a hybrid cross-storage program of data. The steps in the above-described hybrid cross-storage method embodiment of the respective data are implemented when the processor 61 executes the computer program 63, for example, steps S101 to S104 shown in fig. 1. Alternatively, the processor 61, when executing the computer program 63, implements the functions of the modules in the above-described embodiments of the apparatus, such as the functions of the modules 51 to 55 shown in fig. 5.
By way of example, the computer program 63 may be divided into one or more modules/units, which are stored in the memory 62 and executed by the processor 61 to complete the present application. One or more of the modules/units may be a series of computer program instruction segments capable of performing particular functions for describing the execution of the computer program 63 in the electronic device 60. For example, the computer program 63 may be divided into an acquisition module 51, a determination module 52, a cache writing module 53, a cache extraction module 54, a storage writing module 55 (a module in a virtual device), each of which functions specifically as follows:
the acquiring module 51 is configured to acquire data to be stored.
The determining module 52 is configured to determine a first address of an address area corresponding to a type of data to be stored, and a number n of cache units occupied by the data to be stored in the cache area; wherein each type of data corresponds to an address area for storing the type of data, and n is a positive integer.
The cache writing module 53 is configured to write the first address, the number n of cache units, and the data to be stored into the cache area.
The buffer extraction module 54 is configured to extract the first address and the number n of buffer units from the buffer area, and extract the data to be stored from the buffer area according to the number n of buffer units.
The storage writing module 55 is configured to write data to be stored into an address area indicated by the head address.
The electronic device 60 may be a desktop computer, a notebook computer, a palm computer, a cloud server, or the like. The electronic device 60 may include, but is not limited to, a processor 61, a memory 62. It will be appreciated by those skilled in the art that fig. 6 is merely an example of electronic device 60 and is not intended to be limiting of electronic device 60, and may include more or fewer components than shown, or may combine certain components, or different components, e.g., electronic device 60 may also include input-output devices, network access devices, buses, etc.
The processor 61 may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 62 may be an internal storage unit of the electronic device 60, such as a hard disk or a memory of the electronic device 60. The memory 62 may also be an external storage device of the electronic device 60, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) or the like, which are provided on the electronic device 60. Further, the memory 62 may also include both internal storage units and external storage devices of the electronic device 60. The memory 62 is used to store computer programs and other programs and data required by the electronic device 60. The memory 62 may also be used to temporarily store data that has been output or is to be output.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, the specific names of the functional units and modules are only for distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/electronic device and method may be implemented in other manners. For example, the apparatus/electronic device embodiments described above are merely illustrative, e.g., the division of modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated modules/units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the present application may implement all or part of the flow of the method of the above embodiment, or may be implemented by a computer program to instruct related hardware, and the computer program may be stored in a computer readable storage medium, where the computer program, when executed by a processor, may implement the steps of each of the method embodiments described above. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, executable files or in some intermediate form, etc. The computer readable medium may include: any entity or device capable of carrying computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. It should be noted that the content of the computer readable medium can be appropriately increased or decreased according to the requirements of the jurisdiction's jurisdiction and the patent practice, for example, in some jurisdictions, the computer readable medium does not include electrical carrier signals and telecommunication signals according to the jurisdiction and the patent practice.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (7)
1. A hybrid cross-storage method of data, comprising:
acquiring data to be stored;
determining the head address of an address area corresponding to the type of the data to be stored and the number n of cache units occupied by the data to be stored in a cache area; wherein, each type of data corresponds to an address area for storing the type of data, and n is a positive integer;
writing the head address, the number n of the cache units and the data to be stored into the cache area;
extracting the head address and the number n of the cache units from the cache area, and extracting the data to be stored from the cache area according to the number n of the cache units;
writing the data to be stored into an address area indicated by the head address;
forming a buffer unit every k bits in the buffer, wherein k is the number of bits in the buffer; writing the head address, the number n of cache units and the data to be stored into the cache area, wherein the writing comprises the following steps:
determining the number m of cache units occupied by the head address in the cache region according to the length of the head address and the number of bits of the cache region, and distributing m cache units in the cache region to store the head address;
allocating a cache unit to store the number n of the cache units from the cache area;
allocating n cache units to store the data to be stored in the cache area;
wherein k and m are positive integers;
each address area comprises a data area;
writing the data to be stored into an address area indicated by the head address, including:
searching the length of the data area and the writing index value of the address area indicated by the head address; the write index value is used for indicating the initial storage position of the data to be stored in the data area;
writing the data to be stored into a data area according to the writing index value, and updating the writing index value according to the tail storage position of the data to be stored in the data area; if the updated write index value is greater than or equal to the length of the data area, setting the updated write index value to zero;
each address area also comprises an index area, and the lengths of the data areas in the same address area are consistent with those of the index areas;
writing the data to be stored into an address area indicated by the head address, and further comprising:
writing the updated written index value into an index area; the initial storage position of the updated writing index value in the index area corresponds to the initial storage position of the data to be stored in the data area.
2. The hybrid cross-storage method of data as claimed in claim 1, wherein searching for a data area length and a write index value of an address area indicated by the head address comprises:
searching the data area length and the writing index value of the address area indicated by the head address from a preset address area information table; wherein, the address area information table contains the first address of each address area, the length of the data area and the writing index value;
correspondingly, updating the write index value according to the storage position of the data to be stored at the tail end of the data area comprises the following steps:
and updating the writing index value in the address area information table according to the storage position of the data to be stored in the tail end of the data area.
3. The hybrid cross storage method of data according to claim 1, further comprising, after performing the operation of writing the data to be stored into a data area:
judging whether the data to be stored is successfully written;
if the writing of the data to be stored fails, receiving a processing instruction input by a user, and correspondingly processing the data to be stored according to the processing instruction.
4. The hybrid cross-storage method of data as in claim 3 wherein the processing instructions comprise: re-writing instructions and skipping writing instructions; and correspondingly processing the data to be stored according to the processing instruction, wherein the processing method comprises the following steps:
if a rewriting instruction is received, the data to be stored is rewritten in the data area;
and if the skip writing instruction is received, skipping writing of the data to be stored.
5. A hybrid cross-storage device for data, comprising:
the acquisition module is used for acquiring data to be stored;
the determining module is used for determining the head address of the address area corresponding to the type of the data to be stored and the number n of the cache units occupied by the data to be stored in the cache area; wherein, each type of data corresponds to an address area for storing the type of data, and n is a positive integer;
the cache writing module is used for writing the head address, the number n of the cache units and the data to be stored into the cache area;
the cache extraction module is used for extracting the head address and the number n of the cache units from the cache area, and extracting the data to be stored from the cache area according to the number n of the cache units;
the storage writing module is used for writing the data to be stored into an address area indicated by the head address;
forming a buffer unit every k bits in the buffer, wherein k is the number of bits in the buffer; writing the head address, the number n of cache units and the data to be stored into the cache area, wherein the writing comprises the following steps:
determining the number m of cache units occupied by the head address in the cache region according to the length of the head address and the number of bits of the cache region, and distributing m cache units in the cache region to store the head address;
allocating a cache unit to store the number n of the cache units from the cache area;
allocating n cache units to store the data to be stored in the cache area;
wherein k and m are positive integers;
each address area comprises a data area;
writing the data to be stored into an address area indicated by the head address, including:
searching the length of the data area and the writing index value of the address area indicated by the head address; the write index value is used for indicating the initial storage position of the data to be stored in the data area;
writing the data to be stored into a data area according to the writing index value, and updating the writing index value according to the tail storage position of the data to be stored in the data area; if the updated write index value is greater than or equal to the length of the data area, setting the updated write index value to zero;
each address area also comprises an index area, and the lengths of the data areas in the same address area are consistent with those of the index areas;
writing the data to be stored into an address area indicated by the head address, and further comprising:
writing the updated written index value into an index area; the initial storage position of the updated writing index value in the index area corresponds to the initial storage position of the data to be stored in the data area.
6. An electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any of claims 1 to 4 when the computer program is executed.
7. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the steps of the method according to any one of claims 1 to 4.
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