CN113918095A - Data hybrid cross storage method and device and electronic equipment - Google Patents
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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Abstract
The invention is suitable for the technical field of data storage, and provides a data hybrid cross storage method, a data hybrid cross storage device and electronic equipment, wherein the method comprises the following steps: acquiring data to be stored; determining a first address of an address area corresponding to the type of the data to be stored and the number n of cache units occupied by the data to be stored in a cache area; writing the first address, the number n of the cache units and the data to be stored into a cache region; extracting the initial address and the number n of cache units from the cache region, and extracting data to be stored from the cache region according to the number n of cache units; and writing the data to be stored into the address area indicated by the first address. The embodiment of the invention realizes the mixed cross storage of various types of data through one cache region, and obviously reduces the memory occupation amount.
Description
Technical Field
The invention belongs to the technical field of data storage, and particularly relates to a data hybrid cross storage method and device and electronic equipment.
Background
The power module in the electric automobile and the charging pile thereof needs to store a plurality of continuous data locally, and the data needing to be stored continuously is more than one, such as storage failure, operation time, voltage and current, etc., and the data length can include 8 bits, 16 bits, 32 bits, 64 bits, etc.
In order to enable these different types of data to be stored continuously, the prior art usually opens up different address areas for the different types of data to perform separate storage processing. However, each address area needs to be provided with an independent corresponding cache area, and when the types of data to be continuously stored are large, the number of the cache areas is large, a large amount of memory is occupied, and the complexity of the whole storage process is high, and the codes are redundant.
Disclosure of Invention
In view of this, embodiments of the present invention provide a data hybrid interleaving method, an apparatus, and an electronic device, so as to solve the problems in the prior art that when multiple types of data are continuously stored, a large number of cache regions are needed and a large amount of memory is occupied.
A first aspect of an embodiment of the present invention provides a data hybrid interleaving storage method, including:
acquiring data to be stored;
determining a first address of an address area corresponding to the type of the data to be stored and the number n of cache units occupied by the data to be stored in a cache area; each type of data corresponds to an address area for storing the type of data, and n is a positive integer;
writing the first address, the number n of the cache units and the data to be stored into a cache region;
extracting the initial address and the number n of cache units from the cache region, and extracting data to be stored from the cache region according to the number n of cache units;
and writing the data to be stored into the address area indicated by the first address.
Optionally, every k bits in the buffer area form a buffer unit, where k is the number of bits in the buffer area; writing the initial address, the number n of the cache units and the data to be stored into a cache region, comprising:
determining the number m of cache units occupied by the first address in the cache region according to the length of the first address and the bit number of the cache region, and allocating m cache units from the cache region to store the first address;
allocating a cache unit from the cache region to store the number n of the cache units;
distributing n cache units from the cache region to store data to be stored;
wherein k and m are positive integers.
Optionally, each address area includes a data area; writing data to be stored into an address area indicated by a first address, comprising:
searching the data area length and the write index value of the address area indicated by the first address; the writing index value is used for indicating the initial storage position of the data to be stored in the data area;
writing the data to be stored into the data area according to the write index value, and updating the write index value according to the tail storage position of the data to be stored in the data area; and if the updated write index value is larger than or equal to the length of the data area, setting the updated write index value to zero.
Optionally, the searching for the data area length and the write index value of the address area indicated by the head address includes:
searching the data area length and the write index value of the address area indicated by the first address from a preset address area information table; wherein, the address area information table comprises the first address, the length of the data area and the writing index value of each address area;
correspondingly, updating the write index value according to the ending storage position of the data to be stored in the data area comprises the following steps:
and updating the write index value in the address area information table according to the tail storage position of the data to be stored in the data area.
Optionally, each address area further includes an index area, and the length of the data area in the same address area is consistent with that of the index area; writing the data to be stored into the address area indicated by the first address, further comprising:
writing the updated write index value into the index area; and the initial storage position of the updated write index value in the index area corresponds to the initial storage position of the data to be stored in the data area.
Optionally, after performing the operation of writing the data to be stored into the data area, the method further includes:
judging whether the data to be stored is written successfully or not;
and if the data to be stored fails to be written, receiving a processing instruction input by a user, and performing corresponding processing on the data to be stored according to the processing instruction.
Optionally, the processing instruction includes: a rewrite instruction and a skip write instruction; and performing corresponding processing on the data to be stored according to the processing instruction, wherein the processing method comprises the following steps:
if a rewriting instruction is received, rewriting the data to be stored into the data area;
and if the skip writing instruction is received, skipping the writing of the data to be stored.
A second aspect of an embodiment of the present invention provides a hybrid interleaving storage apparatus for data, including:
the acquisition module is used for acquiring data to be stored;
the determining module is used for determining the first address of an address area corresponding to the type of the data to be stored and the number n of cache units occupied by the data to be stored in the cache area; each type of data corresponds to an address area for storing the type of data, and n is a positive integer;
the cache writing module is used for writing the initial address, the number n of the cache units and the data to be stored into a cache region;
the cache extraction module is used for extracting the initial address and the number n of cache units from the cache region and extracting data to be stored from the cache region according to the number n of the cache units;
and the storage writing module is used for writing the data to be stored into the address area indicated by the first address.
A third aspect of the embodiments of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the steps of the hybrid interleaving storage method for data as described above when executing the computer program.
A fourth aspect of embodiments of the present invention provides a computer-readable storage medium, in which a computer program is stored, and the computer program, when executed by a processor, implements the steps of the hybrid interleaved storage method for data as described above.
Compared with the prior art, the embodiment of the invention has the following beneficial effects:
according to the embodiment of the invention, the first address of the address area corresponding to the data, the number of the cache units occupied by the data in the cache area and the data are written into the cache area together when the data are cached, and then when the data are extracted from the cache area subsequently, which address area the data should be put into can be determined according to the first address, and the data can be completely extracted from the cache area according to the number of the cache units occupied by the data in the cache area. The embodiment of the invention realizes the mixed cross storage of various types of data through one cache region, and obviously reduces the memory occupation amount.
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In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic flow chart of a hybrid interleaving storage method for data according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating an address area according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a cache area according to an embodiment of the present invention;
FIG. 4 is a flow chart illustrating writing data into a data area according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a hybrid interleaving memory device for data according to an embodiment of the present invention;
fig. 6 is a schematic diagram of an electronic device provided in an embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
In electric automobile and fill the power module in the electric pile, probably need carry out local storage to many continuous data, the memory content probably is: equipment failure, run time, operating time, voltage current, and the like. Different types of data may also be inconsistent in length, including 8 bits, 16 bits, 32 bits, 64 bits, etc. And these data are intended to be stored continuously, i.e., a continuous failure occurring when the local storage device is in an abnormal condition, or a voltage current value when a failure occurs, etc. In order to adapt to continuous storage of various types of data, the traditional method develops different address areas to respectively store and process the different types of data. Because the traditional method does not perform uniform and standard self-adaptive processing on all types of data, the more the data types are, the more the number of cache regions is, the large memory is occupied, the complexity is high, and the code redundancy is realized. Therefore, the scheme provides a mixed cross storage solution for multiple types of data, which can well solve the storage problem of continuous multiple data with inconsistent types and enables the storage process to be adaptive to various types of data.
Referring to fig. 1, an embodiment of the present invention provides a method for hybrid interleaving storage of data, where the method includes the following steps:
and step S101, acquiring data to be stored.
In the embodiment of the invention, the method can be applied to the electric automobile and the power module in the charging pile thereof. The data to be stored may be data related to the power module including, but not limited to, one or more of fault conditions, run times, operating times, and voltage currents. It should be noted that the method may also be applied to other scenarios that require storing multiple types of data to store related data, and the embodiment of the present invention is not limited thereto.
Step S102, determining the first address of an address area corresponding to the type of the data to be stored and the number n of cache units occupied by the data to be stored in a cache area; each type of data corresponds to an address area for storing the type of data, and n is a positive integer.
In the embodiment of the invention, different address areas are opened up in the IIC memory for different types of data so as to respectively store different types of data continuously. Each address area has a unique first address for identifying the address area, and the first addresses of the address areas are not repeated. Referring to fig. 2, a region 1, an address area 2, … …, and an address area e are used to store different types of data, respectively. The first address of the area 1 is addr1, the first address of the address area 2 is addr2, the first address of the address area e is addre, and addr1, addr2, … … and addre are different.
Because the length of each type of data is fixed, the length of the data to be stored can be determined according to the type of the data to be stored, and the number n of the cache units occupied by the data to be stored in the cache region can be calculated. For example, for a 16-bit cache region, a cache unit is formed every 16 bits, if the length of data is 64, 4 cache units are needed to store the data, and n is equal to 4; if the length of the data is 32, n is equal to 2; if the data is less than 16 bits long, for example, the data is 8 bits, then n is equal to 1.
Step S103, writing the first address, the number n of the cache units and the data to be stored into a cache region.
In the embodiment of the invention, the first address, the number n of the cache units and the data to be stored are simultaneously written into the cache region, so that the complete data can be conveniently extracted from the cache region and the data can be written into the corresponding address region, and the mixed cross storage of different types of data can be realized by using one cache region.
And step S104, extracting the initial address and the number n of the cache units from the cache region, and extracting the data to be stored from the cache region according to the number n of the cache units.
In the conventional method, each data type is provided with a buffer area, the data types in the same buffer area are the same, and the data lengths are also the same, so that a complete data can be obtained by extracting a fixed number of buffer unit data and put into a corresponding address area. In the embodiment of the present invention, since different types of data are all written into one buffer area, when data is extracted, it is first necessary to determine which address area the data should be placed into according to the first address, and then n buffer unit data are extracted according to the number n of buffer units occupied by the data in the buffer area, so as to obtain a complete data.
In step S105, the data to be stored is written into the address area indicated by the first address.
Therefore, in the embodiment of the invention, the first address of the address area corresponding to the data, the number of the cache units occupied by the data in the cache area and the data are written into the cache area together with the data when the data are cached, and then when the data are subsequently extracted from the cache area, which address area the data should be put into can be determined according to the first address, and the data can be completely extracted from the cache area according to the number of the cache units occupied by the data in the cache area. The embodiment of the invention realizes the mixed cross storage of various types of data through one cache region, and obviously reduces the memory occupation amount.
In one possible implementation manner, every k bits in the buffer area form a buffer unit, and k is the bit number of the buffer area; in step S103, the first address, the number n of cache units, and the data to be stored are written into the cache region, which can be detailed as follows:
determining the number m of cache units occupied by the first address in the cache region according to the length of the first address and the bit number of the cache region, and allocating m cache units from the cache region to store the first address;
allocating a cache unit from the cache region to store the number n of the cache units;
distributing n cache units from the cache region to store data to be stored;
wherein k and m are positive integers.
For example, referring to fig. 3, the number of bits of the buffer area is 16, and the length of the first address of each address area is 32 bits. The cache write process of the data to be stored may be as follows:
firstly, dividing the length 32 of the first address by the number 16 of cache block bits to obtain the number m of cache units occupied by the first address in the cache block, wherein 2 cache units are allocated from the cache block to store the first address, the first cache unit stores the lower 16 bits of the first address, and the second cache unit stores the upper 16 bits of the first address. Then, one buffer unit is allocated from the buffer area to store the number n of buffer units. And finally, allocating n cache units from the cache region to store the data to be stored. It should be noted that: the number of bits of the cache region can be set as required, and can be set to 8 bits, 16 bits, and the like, and the specific cache flow is as described above.
A writing process of writing the extracted data into the corresponding address area is explained below.
In some embodiments, each address area comprises a data area, as shown in FIG. 2. In step S105, writing the data to be stored into the address area indicated by the first address may include the following steps one to two:
step one, searching the data area length and the write index value of an address area indicated by a first address; the writing index value is used for indicating the initial storage position of the data to be stored in the data area;
writing the data to be stored into the data area according to the write index value, and updating the write index value according to the tail storage position of the data to be stored in the data area; and if the updated write index value is larger than or equal to the length of the data area, setting the updated write index value to zero.
In the embodiment of the present invention, the updated write index value is used to indicate the starting storage location of the next data to be stored in the data area. If the updated write index value is greater than or equal to the length of the data area, the updated write index value is set to zero, and the circular storage of the data in the data area is realized.
In a possible implementation manner, the finding of the data area length and the write index value of the address area indicated by the first address in the first step may be detailed as follows:
searching the data area length and the write index value of the address area indicated by the first address from a preset address area information table; wherein, the address area information table comprises the first address, the length of the data area and the writing index value of each address area;
correspondingly, the updating of the write index value according to the ending storage location of the data to be stored in the data area may be detailed as follows:
and updating the write index value in the address area information table according to the tail storage position of the data to be stored in the data area.
For example, the preset address area information table may be as shown in table 1, and the address area information table includes the first address, the length of the data area, the length of the index area, the writing index value, and the like of each address area.
TABLE 1 address area information Table
| First address | Data zone length | Length of index zoneDegree of rotation | Writing an index value |
| addr1 | DataLen1 | IndexLen1 | WIndex1 |
| addr2 | DataLen2 | IndexLen2 | WIndex2 |
| ... | ... | ... | ... |
| addre | DataLene | IndexLene | WIndexe |
In the address area information table, the first address, the length of the data area and the length of the index area are known, the row number e of the table is also known by the user layer, and the write index value is a variable updated in real time. For example, when data with a length of 32 bits is stored in an 8-bit data area, 4 memory cells need to be allocated from the data area to store the data, and it is defined that, in the data area, the number of memory cells bytlen required to store one data is 4, and assuming that the write index value obtained by table lookup is 4, the 4 th memory cell in the data area is used as the start memory location to store the data, and the end memory location is 4+ bytlen is 8, the start memory location of the next data is 8, and the write index value in the table is updated to 8. Assuming that the data area length of the data area is 28, when the updated write index value is 28, the write index value is set to 0, and circular storage is realized.
In addition, after the data area length and the write index value of the address area indicated by the head address are inquired from the preset address area information table, the number of lines of the inquiry result in the address area information table can be judged, if the number of lines exceeds the total line number e of the address area information table, the inquiry is judged to be wrong, and the data can be selected to skip the inquiry of the data or to be inquired again according to the instruction of the user.
In a possible implementation manner, referring to fig. 2, each address area further includes an index area, and the length of the data area and the length of the index area in the same address area are the same. In step S105, writing the data to be stored into the address area indicated by the first address, which may further include the third step:
writing the updated write index value into the index area; and the initial storage position of the updated write index value in the index area corresponds to the initial storage position of the data to be stored in the data area.
When the power module is restored after a failure and is powered on again, in order to prevent previously stored data from being overwritten, an index area is provided in the address area to store a write index value in real time to continue storage from a location at the time of power-off after power-on. In the same address area, the data area and the index area have the same size, the bytlen is also the same, and the initial storage position of the index value of the data to be stored in the index area corresponds to the initial storage position of the data to be stored in the data area, so that the circular storage of the write index value in the index area is also realized, the write index value is prevented from being always stored in the same position of the index area, and the service life of the index area is prolonged. For example, when a certain data is written in the data area of the address area 1, the storage location of the data at the end of the data area is determined as an updated index value, and the updated index value is cyclically written in the index area of the address area 1.
It is understood that the length of the index area may be the same or different for different address areas, and the length of the data area may be the same or different for different address areas. Also, since the data lengths of different types may be the same or different, the bytlens of different address areas may be the same or different.
In the process of writing the data to be stored into the data area, a write failure may occur due to a program error, a device abnormality, or the like, and a processing manner in the case of the write failure will be described below.
In a possible implementation manner, after performing the operation of writing the data to be stored into the data area in step S105, the method may further include:
judging whether the data to be stored is written successfully or not;
and if the data to be stored fails to be written, receiving a processing instruction input by a user, and performing corresponding processing on the data to be stored according to the processing instruction.
Optionally, in a possible implementation manner, the processing instruction includes: a rewrite instruction and a skip write instruction. If a rewriting instruction is received, rewriting the data to be stored into the data area; and if the skip writing instruction is received, skipping the writing of the data to be stored.
In the embodiment of the present invention, similar to the processing manner of the data to be stored, after the operation of writing the updated write index value into the index area is performed, it may be further determined whether the updated write index value is successfully written, and if the updated write index value is unsuccessfully written, the write index value may be selected to be written into the index area again or to be skipped over according to the processing instruction input by the user.
According to the above, referring to fig. 4, an embodiment of the present invention further provides a detailed implementation process for writing data in a cache area into an address area, as follows:
(1) and extracting the initial address and the number n of cache units from the cache region.
(2) And looking up the table according to the first address, and extracting the number of rows of the information table where the first address is located.
(3) Judging whether the number of rows of the information table where the table look-up result is positioned exceeds the limit, if the number exceeds the limit, carrying out the limit exceeding treatment, namely, skipping the group of data or looking up the table again according to the user instruction; and if not, executing (4).
(4) And extracting the data area length DataLen, the index area length IndexLen and the write index value Windex in the information table according to the table look-up result of the first address.
(5) And sequentially extracting n cache unit data according to the number n of the cache units, and writing the n cache unit data into the data area corresponding to the address area.
(6) Judging whether the data is written successfully or not, and if so, executing (7); if the data is not written successfully, the processing mode of the user layer needs to be judged, and the data is skipped to be written or rewritten.
(7) The write index value of the address area is increased by bytlen. And if the updated write index value is larger than or equal to the data area length DataLen, setting the write index value to be zero.
(8) Judging whether n data are written in completely, if so, executing (9); otherwise, jumping to (5) to extract n cache unit data again and writing the data into the data area of the corresponding address area.
(9) And writing the updated write index value into the index area.
(10) Judging whether the writing of the index value into the index area is successful, if so, executing (11); if the user layer fails, the processing mode of the user layer needs to be judged, and the index value is selected to be written into the index area again or the writing of the index value is skipped.
(11) If the index value is skipped to be written or the index value is written into the index area, judging whether the data in the cache area is completely read or not, and if the data still exist in the cache area, skipping to (1) the processes of reading, storing and index storing of the next group of data; and if the data in the cache region are completely read, ending the current process.
The embodiment of the invention has the following effects:
1. different address areas are opened up for different types of data, and the information of the first address of the address area, the length of the data area and the length of the index area is registered in a unified table. 2. And aiming at the continuously stored data, a data area and an index area are created in the address area, and the data and the index value are stored in real time. 3. The same buffer area is used for different types of data storage, and the buffer area can adapt to the storage of different types of data. 4. The first address is stored in the cache region, the position where the data should be stored can be determined, and meanwhile, the data region length and the index region length of the address region can be found according to the first address, and the data and the index writing are circularly stored. 6. The number of cache units occupied by the stored data in the cache region can extract complete data according to the number of the cache units. 7. The reusability is strong, the self-adaptation is strong, and the self-adaptation continuous cross hybrid storage of different types of data can be realized.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
Referring to fig. 5, an embodiment of the present invention provides a hybrid interleaving storage device for data, where the device 50 includes:
the obtaining module 51 is configured to obtain data to be stored.
A determining module 52, configured to determine a first address of an address area corresponding to the type of the data to be stored, and a number n of cache units occupied by the data to be stored in the cache area; each type of data corresponds to an address area for storing the type of data, and n is a positive integer.
And a buffer write module 53, configured to write the first address, the number n of buffer units, and the data to be stored into the buffer area.
And the cache extracting module 54 is configured to extract the first address and the number n of cache units from the cache region, and extract the data to be stored from the cache region according to the number n of cache units.
And a storage writing module 55, configured to write the data to be stored in the address area indicated by the first address.
Optionally, in a possible implementation manner, every k bits in the buffer area form a buffer unit, where k is a bit number of the buffer area; the cache write module 53 is configured to:
determining the number m of cache units occupied by the first address in the cache region according to the length of the first address and the bit number of the cache region, and allocating m cache units from the cache region to store the first address;
allocating a cache unit from the cache region to store the number n of the cache units;
distributing n cache units from the cache region to store data to be stored;
wherein k and m are positive integers.
Optionally, in a possible implementation manner, each address area includes a data area; the memory write module 55 is configured to:
searching the data area length and the write index value of the address area indicated by the first address; the writing index value is used for indicating the initial storage position of the data to be stored in the data area;
writing the data to be stored into the data area according to the write index value, and updating the write index value according to the tail storage position of the data to be stored in the data area; and if the updated write index value is larger than or equal to the length of the data area, setting the updated write index value to zero.
Optionally, in a possible implementation manner, the storage writing module 55 is specifically configured to:
searching the data area length and the write index value of the address area indicated by the first address from a preset address area information table; wherein, the address area information table comprises the first address, the length of the data area and the writing index value of each address area; and updating the write index value in the address area information table according to the tail storage position of the data to be stored in the data area.
Optionally, in a possible implementation manner, each address area further includes an index area, and the length of the data area and the length of the index area in the same address area are the same; the storage write module 55 is further configured to:
writing the updated write index value into the index area; and the initial storage position of the updated write index value in the index area corresponds to the initial storage position of the data to be stored in the data area.
Optionally, in a possible implementation manner, after performing the operation of writing the data to be stored into the data area, the storage writing module 55 is further configured to:
judging whether the data to be stored is written successfully or not;
and if the data to be stored fails to be written, receiving a processing instruction input by a user, and performing corresponding processing on the data to be stored according to the processing instruction.
Optionally, in a possible implementation manner, the processing instruction includes: a rewrite instruction and a skip write instruction; the storage write module 55 is further configured to:
if a rewriting instruction is received, rewriting the data to be stored into the data area;
and if the skip writing instruction is received, skipping the writing of the data to be stored.
Fig. 6 is a schematic diagram of an electronic device 60 provided in an embodiment of the present invention. As shown in fig. 6, the electronic apparatus 60 of this embodiment includes: a processor 61, a memory 62, and a computer program 63, such as a hybrid interleaved program of data, stored in the memory 62 and executable on the processor 61. The processor 61 implements the steps in the above-described embodiment of the hybrid interleaved storage method of the respective data, such as the steps S101 to S104 shown in fig. 1, when executing the computer program 63. Alternatively, the processor 61 implements the functions of the modules in the above-described device embodiments, for example, the functions of the modules 51 to 55 shown in fig. 5, when executing the computer program 63.
Illustratively, the computer program 63 may be divided into one or more modules/units, which are stored in the memory 62 and executed by the processor 61 to carry out the invention. One or more modules/units may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution of the computer program 63 in the electronic device 60. For example, the computer program 63 may be divided into an obtaining module 51, a determining module 52, a cache writing module 53, a cache extracting module 54, and a storage writing module 55 (a module in a virtual device), and the specific functions of each module are as follows:
the obtaining module 51 is configured to obtain data to be stored.
A determining module 52, configured to determine a first address of an address area corresponding to the type of the data to be stored, and a number n of cache units occupied by the data to be stored in the cache area; each type of data corresponds to an address area for storing the type of data, and n is a positive integer.
And a buffer write module 53, configured to write the first address, the number n of buffer units, and the data to be stored into the buffer area.
And the cache extracting module 54 is configured to extract the first address and the number n of cache units from the cache region, and extract the data to be stored from the cache region according to the number n of cache units.
And a storage writing module 55, configured to write the data to be stored in the address area indicated by the first address.
The electronic device 60 may be a desktop computer, a notebook, a palm top computer, a cloud server, or other computing devices. The electronic device 60 may include, but is not limited to, a processor 61, a memory 62. Those skilled in the art will appreciate that fig. 6 is merely an example of an electronic device 60 and does not constitute a limitation of the electronic device 60 and may include more or fewer components than shown, or combine certain components, or different components, e.g., the electronic device 60 may also include input-output devices, network access devices, buses, etc.
The Processor 61 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The storage 62 may be an internal storage unit of the electronic device 60, such as a hard disk or a memory of the electronic device 60. The memory 62 may also be an external storage device of the electronic device 60, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), etc., provided on the electronic device 60. Further, the memory 62 may also include both internal storage units and external storage devices of the electronic device 60. The memory 62 is used to store computer programs and other programs and data required by the electronic device 60. The memory 62 may also be used to temporarily store data that has been output or is to be output.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules, so as to perform all or part of the functions described above. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus/electronic device and method may be implemented in other ways. For example, the above-described apparatus/electronic device embodiments are merely illustrative, and for example, a module or a unit may be divided into only one logic function, and may be implemented in other ways, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow in the method according to the embodiments of the present invention may also be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, and when the computer program is executed by a processor, the computer program may implement the steps of the embodiments of the method. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include: any entity or device capable of carrying computer program code, recording medium, U.S. disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution media, and the like. It should be noted that the computer readable medium may contain other components which may be suitably increased or decreased as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, in accordance with legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunications signals.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. A method for hybrid interleaving of data, comprising:
acquiring data to be stored;
determining a first address of an address area corresponding to the type of the data to be stored and the number n of cache units occupied by the data to be stored in a cache area; each type of data corresponds to an address area for storing the type of data, and n is a positive integer;
writing the initial address, the number n of the cache units and the data to be stored into the cache region;
extracting the initial address and the number n of the cache units from the cache region, and extracting the data to be stored from the cache region according to the number n of the cache units;
and writing the data to be stored into the address area indicated by the first address.
2. The hybrid interleaving memory method of claim 1, wherein every k bits in said buffer area form a buffer unit, k being the number of bits of said buffer area; writing the head address, the number n of the cache units and the data to be stored into the cache area, including:
determining the number m of cache units occupied by the first address in the cache region according to the length of the first address and the bit number of the cache region, and allocating m cache units from the cache region to store the first address;
allocating a cache unit from the cache region to store the number n of the cache units;
distributing n cache units from the cache region to store the data to be stored;
wherein k and m are positive integers.
3. A method of hybrid interleaved storage of data as claimed in claim 1 or 2 wherein each address area comprises a data area;
writing the data to be stored into the address area indicated by the head address, including:
searching the data area length and the write index value of the address area indicated by the first address; the writing index value is used for indicating the initial storage position of the data to be stored in the data area;
writing the data to be stored into a data area according to the write index value, and updating the write index value according to the tail storage position of the data to be stored in the data area; and if the updated write index value is larger than or equal to the length of the data area, setting the updated write index value to zero.
4. The hybrid interleaving memory method for data according to claim 3, wherein the searching for the data area length and the write index value of the address area indicated by the first address comprises:
searching the data area length and the write index value of the address area indicated by the first address from a preset address area information table; wherein, the address area information table comprises the first address, the length of the data area and the writing index value of each address area;
correspondingly, updating the write index value according to the ending storage position of the data to be stored in the data area includes:
and updating the write index value in the address area information table according to the tail storage position of the data to be stored in the data area.
5. A hybrid interleaving storage method for data according to claim 3, wherein each address area further includes an index area, and the length of the data area is identical to that of the index area in the same address area;
writing the data to be stored into the address area indicated by the head address, further comprising:
writing the updated write index value into an index area; and the initial storage position of the updated write index value in the index area corresponds to the initial storage position of the data to be stored in the data area.
6. The hybrid interleaving storage method of data according to claim 3, further comprising, after performing the operation of writing the data to be stored into the data area:
judging whether the data to be stored is written successfully or not;
and if the data to be stored fails to be written, receiving a processing instruction input by a user, and carrying out corresponding processing on the data to be stored according to the processing instruction.
7. The method of hybrid interleaved storage of data according to claim 6 wherein said processing instructions comprise: a rewrite instruction and a skip write instruction; and correspondingly processing the data to be stored according to the processing instruction, wherein the processing comprises the following steps:
if a rewriting instruction is received, rewriting the data to be stored into a data area;
and if a skip writing instruction is received, skipping the writing of the data to be stored.
8. A hybrid interleaving memory device for data, comprising:
the acquisition module is used for acquiring data to be stored;
the determining module is used for determining a first address of an address area corresponding to the type of the data to be stored and the number n of cache units occupied by the data to be stored in a cache area; each type of data corresponds to an address area for storing the type of data, and n is a positive integer;
the cache writing module is used for writing the head address, the number n of the cache units and the data to be stored into the cache region;
the cache extraction module is used for extracting the initial address and the number n of the cache units from the cache region and extracting the data to be stored from the cache region according to the number n of the cache units;
and the storage writing module is used for writing the data to be stored into the address area indicated by the first address.
9. An electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the steps of the method according to any of claims 1 to 7 are implemented when the computer program is executed by the processor.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 7.
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