CN113917802A - Overlay error measuring and calculating method - Google Patents
Overlay error measuring and calculating method Download PDFInfo
- Publication number
- CN113917802A CN113917802A CN202111191680.6A CN202111191680A CN113917802A CN 113917802 A CN113917802 A CN 113917802A CN 202111191680 A CN202111191680 A CN 202111191680A CN 113917802 A CN113917802 A CN 113917802A
- Authority
- CN
- China
- Prior art keywords
- offset
- overlay error
- photomask
- test
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 59
- 238000012360 testing method Methods 0.000 claims abstract description 82
- 230000008569 process Effects 0.000 claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 claims abstract description 22
- 238000005259 measurement Methods 0.000 claims abstract description 17
- 238000004364 calculation method Methods 0.000 claims description 11
- 238000012545 processing Methods 0.000 claims description 10
- 230000002159 abnormal effect Effects 0.000 claims description 6
- 238000013461 design Methods 0.000 claims description 5
- 238000000691 measurement method Methods 0.000 claims description 4
- 230000000717 retained effect Effects 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 10
- 238000007405 data analysis Methods 0.000 abstract description 3
- 230000002349 favourable effect Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 29
- 239000002184 metal Substances 0.000 description 17
- 238000004458 analytical method Methods 0.000 description 7
- 235000012431 wafers Nutrition 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000013598 vector Substances 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70653—Metrology techniques
- G03F7/70658—Electrical testing
Abstract
The invention provides a measuring and calculating method of overlay error, which comprises the following steps: designing a first photomask and a second photomask according to a preset deviation amount for manufacturing a test chain; acquiring N test chains corresponding to different preset offsets, wherein N is more than or equal to 3; measuring the electrical parameters of the N test chains to obtain the electrical parameters and the corresponding preset offset as a group of reference data; and performing data analysis on the reference data, and calculating to obtain an alignment error value of the first photomask and the second photomask. The overlay error value is obtained based on electrical measurement, the implementation is easy, and the obtained result is closer to the real overlay error; the process is convenient to monitor in real time, the production process can be adjusted in time, and the yield of products is continuously improved. In addition, the method can be suitable for repeated testing after the semiconductor chip is manufactured, and is favorable for better tracing the process problems.
Description
Technical Field
The invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a measuring and calculating method for overlay errors in a semiconductor photoetching process.
Background
With the updating and iteration of semiconductor technology, the size of a device is smaller and smaller, and in the process, a photomask (mask) for realizing the same layer of pattern etching is developed into two layers at present from the earliest layer. In the manufacturing process of semiconductor chips, a photolithography machine is used to expose all fields (fields) on a silicon wafer one by one, and then the silicon wafer is replaced until the exposure of all the silicon wafers is completed. And after the process treatment is finished on the silicon wafer, exposing the second layer of pattern on the silicon wafer, namely repeatedly exposing. The pattern exposed by the second layer of photomask must be accurately overlapped with the pattern exposed by the first layer of photomask, so the method is called overlay etching. Overlay error (OVL) refers to the accuracy of alignment between the pattern of the current layer and the pattern of the previous layer in the lithographic manufacturing process. Because the integrated circuit chip is manufactured by laminating a plurality of layers of structures, the structure formed by each photoetching process needs to be aligned with each previously formed layer of structure, and the alignment precision among the layers of structures directly influences the effectiveness and the yield of the integrated circuit chip. In the manufacturing process of the semiconductor chip, the process parameters for manufacturing the integrated circuit chip can be adjusted according to the overlay error value so as to improve the effectiveness and the yield of the integrated circuit chip, the deviation of the interlayer overlay alignment has great influence on the performance of the device, even the device may be out of service, the yield is reduced, the waste of time and money is caused, and the cost is increased, so the OVL calculation is more important, and the overlay error value with accurate measurement and calculation is a key step for improving the yield.
In order to realize accurate alignment and overlay, the prior art mainly adopts a mark alignment method, but overlay errors formed by mark alignment cannot be recorded and reflected one by one in a fluctuation process. In addition, the data tracing of the overlay error can only be based on online monitoring data (OVL inline equipment test result), and the method has short timeliness and cannot be tested again after the semiconductor device is finished.
Therefore, there is a need to develop a measurement and calculation method for overlay error, which does not rely on the conventional marking alignment method, has good data traceability, long timeliness and more worried test effect, and can accurately perform analysis and calculation to further promote the deep development and high-efficiency application of semiconductor manufacturing technology.
Disclosure of Invention
The invention provides a measuring and calculating method of overlay error, which aims to solve all or part of problems in the prior art, is suitable for calculating OVL (overlay error) values between light shields through electrical measurement and can realize detection of overlay error values in a photoetching process.
The invention provides a measuring and calculating method of overlay error, which comprises the following steps: s1, designing a first photomask and a second photomask according to a preset offset, wherein the preset offset comprises zero offset, a plurality of positive offset and a plurality of negative offset which are changed relative to the zero offset according to a preset offset step length; making a test chain through the first reticle and the second reticle; s2, acquiring N test chains corresponding to different preset offsets, wherein N is not less than 3 and is an integer; s3, measuring the electrical parameters of the N test chains, and taking the obtained electrical parameters and the corresponding preset offset as a group of reference data; s4, carrying out data processing on each group of reference data except zero offset to obtain N-1 overlay error values; calculating the alignment error values of the first photomask and the second photomask based on the N-1 alignment error values; wherein the test chain comprises at least one first conductive structure and at least one second conductive structure respectively located in two adjacent dielectric layers, and at least one connection structure electrically connecting the first conductive structure and the second conductive structure; the connecting structure is completely connected with the second conductive structure without offset; the first conductive structure is made of the first mask and the connection structure is made of the second mask. At least one of the first conductive structures is electrically connected with at least one of the second conductive structures through at least one connecting structure to form the test chain; and at least three test chains corresponding to different preset offsets.
The zero offset represents the position alignment of a second photomask for manufacturing the test chain relative to a first photomask, and the offset of a connecting structure is 0; the positive offset represents the offset of the position of a graph in a second photomask for manufacturing the test chain, which is offset to one side relative to the position of the graph in the first photomask, and the positive offset is represented by a positive value; the negative offset represents the offset of the position of the pattern in the second photomask for manufacturing the test chain, which is offset to the other side in the opposite direction relative to the position of the pattern in the first photomask, and is characterized by a negative value. The offset of the test chain is the offset of the pattern position in the second reticle relative to the pattern position in the first reticle. The test chain can detect errors in various directions in the plane, such as the horizontal direction, the vertical direction or any other direction, in the wafer plane. For example: offset from left to right, left, right to left, right, etc.
In step S2, the obtaining N test chains includes connecting in parallel the test chains with the same offset made by the first photomask and the second photomask as one test chain; the electrical parameter measured in step S3 is a resistance value. That is, the test chains corresponding to different preset offsets may be formed by connecting a plurality of test chains corresponding to the same preset offset in parallel. The method is beneficial to reducing the influence of the electrical measurement method caused by measurement deviation in the actual measurement process so as to obtain more accurate overlay error values.
And the value ranges of the positive offset and the negative offset are set according to the design rules of different node processes.
The value range of the positive offset and the value range of the negative offset are the same, and the number of the test chains obtained on the basis of the positive offset is equal to the number of the test chains obtained on the basis of the negative offset. The method is beneficial to acquiring symmetrical sample data and can more accurately perform subsequent data processing analysis.
The connecting structure in the test chain obtained based on the positive offset and the connecting structure of the test chain obtained based on the negative offset are axisymmetric with respect to the connecting structure of the test chain obtained based on the zero offset. The design of the test structure is beneficial to enabling the calculation and analysis of the overlay error value to be more convenient and faster.
The preset offset step size is set in a manner that the influence of the offset on the electrical parameters of the test chain is inversely related to the influence of the offset on the electrical parameters of the test chain. Namely, the smaller the preset offset step length is in a region where the offset has a large influence on the electrical parameter of the test chain, the larger the preset offset step length is in a region where the offset has a small influence on the electrical parameter of the test chain. The method is favorable for acquiring a reasonable amount of the reference data, and if the change of the offset is greatly influenced by the electrical parameters, a plurality of groups of the reference data are acquired by a small preset offset step length for analysis, so that more accurate analysis is facilitated; the electric parameter has small influence on the change of the offset, namely the electric parameter is insensitive to the change of the offset, and relatively less reference data is obtained by using a larger preset offset step length, so that the analysis amount is reduced, and the effective analysis efficiency is improved.
The removing of the abnormal point after the electrical parameter is measured in the step S3 includes: taking the average value of the maximum value and the minimum value of the measurement results as the mark,
(ii) a Greater than in the measurement result
And (3) after the value of (a) is taken as an abnormal point to be removed, taking the value as the obtained electrical parameter. The abnormal points are removed in advance, so that the data processing is more accurate, the data processing amount is reduced, and the data analysis efficiency is improved.
In step S3, the corresponding preset offset includes the positive offset or the negative offset. In the subsequent data analysis, only the positive deviation condition or the negative deviation condition relative to the zero deviation is processed, which is beneficial to reducing the subsequent data processing amount and improving the working efficiency.
The calculating the overlay error values of the first photomask and the second photomask based on the N-1 overlay error values includes: presetting a reference value according to the process node; an overlay error value is recorded as amBased on amCalculating the standard deviation, denoted as σmTraversing m, wherein m is more than or equal to 1 and less than or equal to N-1; will obtain the standard deviation of sigma larger than the reference valuemCorresponding to amAnd removing, and taking the median or average value of the retained alignment error values as the alignment error values of the first photomask and the second photomask.
In step S4, a function curve of each discrete group of reference data is obtained by linear fitting or linear interpolation, and N-1 overlay error values are obtained based on the function curve.
In step S4, obtaining N-1 overlay error values includes: s41, determining a zero offset position as an origin by adopting a rectangular coordinate system; s42, selecting the corresponding preset offset as XiIs recorded as a coordinate point (X)i，Rxi) I is more than or equal to 2 and less than or equal to N; from the coordinate point (X)i，Rxi) Making a line parallel to the x-axis to the origin, denoted Lx(ii) a Selecting the corresponding deviation X of the preset offsetiVarying Xi-1And Xi-2The corresponding reference data are respectively marked as coordinate points (X)i-1，Rxi-1) And (X)i-2，Rxi-2) Connecting coordinate points (X)i-1，Rxi-1) And (X)i-2，Rxi-2) Make a straight line and a straight line LxIntersecting, the X-axis coordinate corresponding to the intersection point is Xj(ii) a Calculating the corresponding preset offset as XiThe overlay error Vx of the test chaini，
(ii) a And S43, traversing i to obtain the N-1 overlay error values.
The preset offset is set for two orthogonal offset directions and is correspondingly characterized by vectors (a, b); the step S3 includes: taking the obtained electrical parameters and the corresponding a as a group of reference data, and marking as A; taking the obtained electrical parameters and the corresponding B as a group of reference data, and marking as B; in the step S4, each group a and each group B are respectively subjected to data processing, and alignment error values are calculated and recorded as SaAnd SbIn the form of a vector (S)a，Sb) And characterizing overlay error values of the first photomask and the second photomask. Through the direction ofThe overlay error value represented by the quantity can more visually reflect the deviation in any direction in the plane, is favorable for better combining the actual production situation, obtains the overlay error which is more in line with the actual situation, and can more effectively guide the process optimization and the design improvement.
In step S1, the first mask is used to fabricate at least three first conductive structures at a time, and the first mask is used alternately for even number of times to complete the fabrication of all the first conductive structures; for the first reticle used twice alternately, the steps S2 to S4 are performed twice respectively; respectively recording the overlay error values calculated in the step S4 as SMagic card、SDollThen, the overlay error value of the first photomask used twice is calculated to be
. In the advanced process, because the first conductive structures are closer to each other, the first conductive structures are easily fused by one-step manufacturing of a photomask, under the advanced process condition, the first conductive structures are often alternately used by the same photomask to complete the manufacturing of the conductive structures, the first photomask also has overlay errors in different uses, and the overlay error value of the first photomask in two uses can be further obtained in a better way.
Compared with the prior art, the invention has the main beneficial effects that:
the alignment error measuring and calculating method has concise steps, can calculate and obtain the alignment errors among a plurality of photomasks used for manufacturing the same layer and/or different layers through electrical measurement, is easier to realize, can obtain results closer to real alignment errors, can monitor the process in real time, can quickly reflect process fluctuation, and can guide the adjustment of the semiconductor chip production process in time through the results obtained through measurement and calculation, thereby providing a feasible basic scheme for further continuously improving the product yield. In addition, the measuring and calculating method can be used for retesting after the semiconductor chip is manufactured, and can be used for data comparison with the test result of the OVL inline equipment to prove, so that the reliability of the overlay error test result is improved; and the process problem tracing can be completed better and more flexibly.
Drawings
Fig. 1 is a schematic process diagram of a measurement calculation method according to a first embodiment of the present invention.
Fig. 2 is a schematic diagram of a test structure according to a first embodiment of the invention.
Fig. 3 is a schematic diagram of measurement results in the second embodiment of the present invention.
Detailed Description
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings. In the figures, parts of the same structure or function are denoted by the same reference numerals, and not all parts shown are denoted by the associated reference numerals in all figures for reasons of clarity of presentation. The operations of the embodiments are depicted in the following embodiments in a particular order, which is provided for better understanding of the details of the embodiments and to provide a thorough understanding of the present invention, but the order is not necessarily one-to-one correspondence with the methods of the present invention, and is not intended to limit the scope of the present invention.
Example one
In an embodiment of the present invention, as shown in fig. 1, an exemplary overlay error measurement and calculation method includes: s1, designing a first photomask and a second photomask according to preset offset, wherein the preset offset comprises zero offset, a plurality of positive offset and a plurality of negative offset which are changed relative to the zero offset according to a preset offset step length; manufacturing a test chain through the first photomask and the second photomask; s2, acquiring N test chains corresponding to different preset offsets, wherein N is not less than 3 and is an integer; s3, measuring the electrical parameters of the N test chains, and taking the obtained electrical parameters and the corresponding preset offset as a group of reference data; s4, carrying out data processing on each group of reference data except zero offset to obtain N-1 alignment error values; calculating the alignment error values of the first photomask and the second photomask based on the N-1 alignment error values; the testing chain comprises at least one first conductive structure and at least one second conductive structure which are respectively positioned in two adjacent dielectric layers, and at least one connecting structure which electrically connects the first conductive structure and the second conductive structure; the connecting structure is completely connected with the second conductive structure without offset; the first conductive structure is made of a first mask and the connection structure is made of a second mask. The at least one first conductive structure is electrically connected to the at least one second conductive structure by the at least one connecting structure to form a test chain. In this embodiment, an exemplary test structure is shown in fig. 2, the test chain may be obtained from the same preset offset Misalign Value or may be obtained from different preset offsets Misalign Value, and at least three test chains corresponding to different preset offsets Misalign Value are provided. In this embodiment, in step S2, the obtaining N test chains includes connecting in parallel the test chains with the same offset made by the first photomask and the second photomask as one test chain; an example of the electrical parameter measured in step S3 is a resistance value.
In this example 43 test chains were used. As illustrated in fig. 2, the dielectric layer where the first conductive structure is located is a metal layer, the dielectric layer where the second conductive structure is located is a Ploy (polysilicon) layer, and both the first conductive structure and the second conductive structure are metal lines, which are respectively labeled as M1 and M2; each test chain includes a plurality of metal lines M1 on the metal layer, a plurality of metal lines M2 on the Poly layer, and a plurality of contact holes Via. The contact hole Via is an exemplary connection structure. The metal wire M1 of the metal layer is electrically connected with the metal wire M2 of the Poly layer through the contact hole Via; the metal line M1 of the metal layer is made by the first mask; the contact hole Via is made of a second photomask; the metal line M2 of the Poly layer is made by the third mask; the first mask and the second mask are designed with a predetermined offset Misalign Value, i.e., the contact hole Via has an offset formed by the predetermined offset Misalign Value with respect to the metal line M1 of the metal layer. In this embodiment, the second mask and the third mask have no offset, and the contact hole Via is not offset with respect to the metal line M2 of the Poly layer, that is, the contact hole Via is completely connected to the metal line M2 of the Poly layer. The contact holes Via of different test chains have different specific preset offsets Misalign Value with respect to metal line M1 of the metal layer. For convenience of description, in the present embodiment, "-, +" (positive or negative) is described in a manner of "left" or "right" in the map fig. 2 with the observer as a coordinate, and the preset offset Misalign Value includes zero offset, positive offset, and negative offset. Zero offset means that the second mask for manufacturing the test chain is aligned with respect to the first mask, and the offset of the connecting structure is 0; the positive offset represents the offset of the position of the graph in the second photomask for manufacturing the test chain to the right relative to the position of the graph in the first photomask, and the positive offset is represented by a positive value; a negative offset represents an offset to the left of the offset of the position of the pattern in the second reticle for manufacturing the test chain relative to the position of the pattern in the first reticle, characterized by a negative value. The connection structure in the test chain obtained based on the positive offset and the connection structure in the test chain obtained based on the negative offset in this embodiment are axisymmetric with respect to the connection structure of the test chain obtained based on the zero offset. I.e., left offset contact hole Via and right offset contact hole Via are left-right axisymmetric with respect to zero offset contact hole Via. The number of test chains derived based on a positive offset is equal to the number of test chains derived based on a negative offset. In this embodiment, the value ranges of the positive offset and the negative offset are set according to the design rules of different node processes. The positive offset and the negative offset have the same value range. In the example case, the process node is 55nm, the value range of the positive offset is greater than 0 and less than or equal to 42 nm, and the unit is nm; the value range of the negative offset is more than or equal to-42 and less than 0, and the unit is nanometer. In this embodiment, the preset offset step size is set in negative correlation with the influence of the offset on the electrical parameters of the test chain. In the illustrated case, the step value in the preset offset (-20, 20) interval is set to 4 in nanometers; the step value in the interval of the preset offsets [ -42, -20], [20, 42] is set to 2.
In step S3, after the test chain passes through the MEOL and BEOL process steps, a voltage U is applied to two ends of the test chain to test a current value I flowing through the test structure, so as to obtain a resistance value R ═ U/I of each test chain. The average value of the maximum value and the minimum value of the resistance value R obtained by measurement is taken as the mark,
. In the present embodiment, the resistance value R to be measured is larger than
The value of (A) is removed as an abnormal point, and then the resistance value is marked in a rectangular coordinate system as an obtained electrical parameter, namely a resistance value, and the resistance value of the ordinate axis corresponding to the test chain is marked as Rxi(ii) a The corresponding abscissa is the preset offset Misalign Value corresponding to the test chain, and is marked as Xi. In step S4, obtaining N-1 overlay error values includes: s41, determining the position of zero offset as an origin and marking as (0, 0); s42, selecting a group of reference data and recording the reference data as a coordinate point (X)i，Rxi) I is more than or equal to 2 and less than or equal to N; from the coordinate point (X)i，Rxi) Making a line parallel to the x-axis to the origin, denoted Lx(ii) a Selecting the corresponding preset offset deviation XiTwo offset amounts of variation Xi-1And Xi-2The corresponding reference data, i.e. the reference data of left deviation or right deviation, are respectively marked as coordinate points (X)i-1，Rxi-1) And (X)i-2，Rxi-2) Connecting coordinate points (X)i-1，Rxi-1) And (X)i-2，Rxi-2) Make a straight line and a straight line LxIntersecting, the X-axis coordinate corresponding to the intersection point is Xj(ii) a Calculating the corresponding preset offset as XiAlignment error Vx of the test chaini，
(ii) a And S43, traversing i to obtain N-1 overlay error values.
In some implementations, in step S3, the corresponding preset offset amount includes a positive offset amount or a negative offset amount. I.e. the data processing may only process reference data shifted left or right.
In some embodiments, in step S4, each discrete set of reference data (X) is obtained by a specific linear fitting or linear interpolation methodi，Rxi) Based on the points on the function curve, N-1 overlay error values are obtained. The specific form is not limited toThe method is carried out.
In this embodiment, calculating the overlay error values of the first mask and the second mask based on the N-1 overlay error values includes: presetting a reference value according to the process node; let the overlay error value be amBased on amCalculating the standard deviation, denoted as σmTraversing m, wherein m is more than or equal to 1 and less than or equal to N-1; will obtain the standard deviation of sigma greater than the reference valuemCorresponding to amAnd removing, namely taking the median of the reserved plurality of overlay error values as the overlay error values of the first photomask and the second photomask. In processes below 55nm, σ is typically taken to be 2 nm. And removing the overlay error with the standard deviation larger than 2 nanometers to obtain a plurality of credible overlay errors.
Example two
The difference between the second embodiment and the first embodiment is mainly that the preset offset is set for two orthogonal offset directions, and the offset is represented by vectors (a, b); step S3 includes: taking the obtained resistance value and the corresponding a as a group of reference data, and marking as A; taking the obtained electrical parameters and the corresponding B as a group of reference data, and marking as B; in step S4, each group a and each group B are respectively subjected to data processing, and overlay error values are calculated and recorded as SaAnd SbIn the form of a vector (S)a，Sb) And characterizing overlay error values of the first photomask and the second photomask. An exemplary measurement result is shown in the box diagram of fig. 3, and includes two sets of reference data biased in directions misAlignDirection of X and Y, each set of reference data being composed of a resistance value rc (ohm) and a deviation a indicative of the X direction or a deviation b indicative of the Y direction. In this embodiment, the average of the N-1 overlay error values is taken as the overlay error values of the first mask and the second mask.
For clarity of description, the use of certain conventional and specific terms and phrases is intended to be illustrative and not restrictive, but rather to limit the scope of the invention to the particular letter and translation thereof.
It is further noted that, herein, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
While the invention has been described in detail and with reference to specific examples thereof, it will be apparent to one skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope thereof as defined in the appended claims.
Claims (10)
1. A measuring and calculating method of overlay error is characterized in that: the method comprises the following steps:
s1, designing a first photomask and a second photomask according to a preset offset, wherein the preset offset comprises zero offset, a plurality of positive offset and a plurality of negative offset which are changed relative to the zero offset according to a preset offset step length; manufacturing a test chain through the first photomask and the second photomask;
s2, acquiring N test chains corresponding to different preset offsets, wherein N is not less than 3 and is an integer;
s3, measuring the electrical parameters of the N test chains, and taking the obtained electrical parameters and the corresponding preset offset as a group of reference data;
s4, carrying out data processing on each group of reference data except zero offset to obtain N-1 overlay error values; calculating the alignment error values of the first photomask and the second photomask based on the N-1 alignment error values;
the test chain comprises at least one first conductive structure and at least one second conductive structure which are respectively positioned in two adjacent dielectric layers, and at least one connecting structure which electrically connects the first conductive structure and the second conductive structure; the connecting structure is completely connected with the second conductive structure without offset;
the first conductive structure is made of the first mask and the connection structure is made of the second mask.
2. A method of measuring and calculating overlay error according to claim 1, wherein: in step S2, the obtaining N test chains includes connecting in parallel the test chains with the same offset made by the first photomask and the second photomask as one test chain; the electrical parameter measured in step S3 is a resistance value.
3. A method of measuring and calculating overlay error according to claim 1, wherein: and the value ranges of the positive offset and the negative offset are set according to the design rules of different node processes.
4. A method of measuring and calculating overlay error according to claim 3, wherein: the value ranges are the same, and the number of the test chains obtained based on the positive offset is equal to the number of the test chains obtained based on the negative offset.
5. A method of measuring and calculating overlay error according to claim 1, wherein: the connecting structure in the test chain obtained based on the positive offset and the connecting structure of the test chain obtained based on the negative offset are axisymmetric with respect to the connecting structure of the test chain obtained based on the zero offset.
6. A method of measuring and calculating overlay error according to claim 1, wherein: the preset offset step size is set in a manner that the influence of the offset on the electrical parameters of the test chain is inversely related to the influence of the offset on the electrical parameters of the test chain.
7. According to claimThe overlay error measurement and calculation method according to claim 1, wherein: the removing of the abnormal point after the electrical parameter is measured in the step S3 includes: the average value of the maximum value and the minimum value of the measurement result is taken as
(ii) a Greater than in the measurement result
And (3) after the value of (a) is taken as an abnormal point to be removed, taking the value as the obtained electrical parameter.
8. A method of measuring and calculating overlay error according to claim 1, wherein: in step S3, the corresponding preset offset includes the positive offset or the negative offset.
9. A method of measurement calculation of overlay error according to any one of claims 1-8, wherein: the calculating the overlay error values of the first photomask and the second photomask based on the N-1 overlay error values includes:
presetting a reference value according to the process node; an overlay error value is recorded as amBased on amCalculating the standard deviation, denoted as σmTraversing m, wherein m is more than or equal to 1 and less than or equal to N-1;
will obtain the sigma of the standard deviation larger than the reference valuemCorresponding amAnd removing, and taking the median or average value of the retained alignment error values as the alignment error values of the first photomask and the second photomask.
10. A method of measurement calculation of overlay error according to any one of claims 1-8, wherein: in step S4, obtaining N-1 overlay error values includes:
s41, determining a zero offset position as an origin by adopting a rectangular coordinate system;
s42, selecting the corresponding presetOffset is XiIs recorded as a coordinate point (X)i，Rxi) I is more than or equal to 2 and less than or equal to N; from the coordinate point (X)i，Rxi) Making a line parallel to the x-axis to the origin, denoted Lx(ii) a Selecting the corresponding deviation X of the preset offsetiVarying Xi-1And Xi-2The corresponding reference data are respectively marked as coordinate points (X)i-1，Rxi-1) And (X)i-2，Rxi-2) Connecting coordinate points (X)i-1，Rxi-1) And (X)i-2，Rxi-2) Make a straight line and a straight line LxIntersecting, the X-axis coordinate corresponding to the intersection point is Xj(ii) a Calculating the corresponding preset offset as XiThe overlay error Vx of the test chaini，
；
And S43, traversing i to obtain the N-1 overlay error values.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111191680.6A CN113917802A (en) | 2021-10-13 | 2021-10-13 | Overlay error measuring and calculating method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111191680.6A CN113917802A (en) | 2021-10-13 | 2021-10-13 | Overlay error measuring and calculating method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113917802A true CN113917802A (en) | 2022-01-11 |
Family
ID=79240098
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111191680.6A Pending CN113917802A (en) | 2021-10-13 | 2021-10-13 | Overlay error measuring and calculating method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113917802A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030223630A1 (en) * | 2002-02-15 | 2003-12-04 | Kla-Tencor Corporation | Overlay metrology and control method |
| US20050188342A1 (en) * | 2004-02-19 | 2005-08-25 | Francis Goodwin | Method of determining the overlay accuracy of multiple patterns formed on a semiconductor wafer |
| US20060109464A1 (en) * | 2004-11-22 | 2006-05-25 | Akiyuki Minami | Method for detecting alignment accuracy |
| CN102243443A (en) * | 2010-05-14 | 2011-11-16 | 北京京东方光电科技有限公司 | Detection method for pattern offset between exposure areas and test pattern |
| CN110244527A (en) * | 2019-06-13 | 2019-09-17 | 华中科技大学 | A kind of overlay mark pattern and measuring condition optimization method |
| CN112015056A (en) * | 2020-07-29 | 2020-12-01 | 中国科学院微电子研究所 | Overlay offset value correction method, electronic device and computer-readable storage medium |
| CN113296365A (en) * | 2020-12-29 | 2021-08-24 | 杭州广立微电子股份有限公司 | Method for measuring overlay error and test structure |
-
2021
- 2021-10-13 CN CN202111191680.6A patent/CN113917802A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030223630A1 (en) * | 2002-02-15 | 2003-12-04 | Kla-Tencor Corporation | Overlay metrology and control method |
| US20050188342A1 (en) * | 2004-02-19 | 2005-08-25 | Francis Goodwin | Method of determining the overlay accuracy of multiple patterns formed on a semiconductor wafer |
| US20060109464A1 (en) * | 2004-11-22 | 2006-05-25 | Akiyuki Minami | Method for detecting alignment accuracy |
| CN102243443A (en) * | 2010-05-14 | 2011-11-16 | 北京京东方光电科技有限公司 | Detection method for pattern offset between exposure areas and test pattern |
| US20110279132A1 (en) * | 2010-05-14 | 2011-11-17 | Beijing Boe Optoelectronics Technology Co., Ltd. | Method for detecting pattern offset amount of exposed regions and detecting mark |
| CN110244527A (en) * | 2019-06-13 | 2019-09-17 | 华中科技大学 | A kind of overlay mark pattern and measuring condition optimization method |
| CN112015056A (en) * | 2020-07-29 | 2020-12-01 | 中国科学院微电子研究所 | Overlay offset value correction method, electronic device and computer-readable storage medium |
| CN113296365A (en) * | 2020-12-29 | 2021-08-24 | 杭州广立微电子股份有限公司 | Method for measuring overlay error and test structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9594309B2 (en) | Method and apparatus to characterize photolithography lens quality | |
| US5602492A (en) | Electrical test structure and method for measuring the relative locations of conducting features on an insulating substrate | |
| US5857258A (en) | Electrical test structure and method for measuring the relative locations of conductive features on an insulating substrate | |
| US5617340A (en) | Method and reference standards for measuring overlay in multilayer structures, and for calibrating imaging equipment as used in semiconductor manufacturing | |
| US5699282A (en) | Methods and test structures for measuring overlay in multilayer devices | |
| US6449749B1 (en) | System and method for product yield prediction | |
| US5923041A (en) | Overlay target and measurement procedure to enable self-correction for wafer-induced tool-induced shift by imaging sensor means | |
| US11669957B2 (en) | Semiconductor wafer measurement method and system | |
| US20110051150A1 (en) | Unique mark and method to determine critical dimension uniformity and registration of reticles combined with wafer overlay capability | |
| US5383136A (en) | Electrical test structure and method for measuring the relative locations of conducting features on an insulating substrate | |
| TWI532075B (en) | A method and a system for determining overlap process windows in semiconductors by inspection techniques | |
| US4782288A (en) | Method for evaluating processing parameters in the manufacture of semiconductor devices | |
| US5044750A (en) | Method for checking lithography critical dimensions | |
| CN106154741B (en) | Mask plate, defocus testing method and defocus testing system | |
| CN112882346B (en) | Overlay compensation method and system | |
| CN113093482B (en) | Alignment error testing method, alignment error adjusting method, alignment error testing system and storage medium | |
| TWI412068B (en) | Alignment mark and defect inspection method | |
| CN113917802A (en) | Overlay error measuring and calculating method | |
| US6727989B1 (en) | Enhanced overlay measurement marks for overlay alignment and exposure tool condition control | |
| JPH05267430A (en) | Method of producing metrologic structure specifically suited for direct error measurement introduced in alignment system | |
| TW507308B (en) | Correction of overlay offset between inspection layers in integrated circuits | |
| Cresswell et al. | Recent developments in electrical linewidth and overlay metrology for integrated circuit fabrication processes | |
| US7376920B2 (en) | Method to monitor critical dimension of IC interconnect | |
| US7856138B2 (en) | System, method and computer software product for inspecting charged particle responsive resist | |
| KR20010058979A (en) | Overlay vernier and method detecting overlay using the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |