CN113904681B - High-performance phase-locked loop suitable for wireless MCU and frequency correction method thereof - Google Patents
High-performance phase-locked loop suitable for wireless MCU and frequency correction method thereof Download PDFInfo
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- CN113904681B CN113904681B CN202111148181.9A CN202111148181A CN113904681B CN 113904681 B CN113904681 B CN 113904681B CN 202111148181 A CN202111148181 A CN 202111148181A CN 113904681 B CN113904681 B CN 113904681B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
- H03L7/0895—Details of the current generators
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention relates to a high-performance phase-locked loop suitable for a wireless MCU (microprogrammed control Unit) and a frequency correction method thereof, belonging to the technical field of oscillators. The method is characterized in that: the circuit comprises a phase frequency detector, a charge pump, a loop filter, a voltage-controlled/digital-controlled oscillator, a frequency divider, an LDO (low dropout regulator), an SPVT (pulse voltage regulator) detection circuit and a register; the phase frequency detector, the charge pump, the loop filter, the voltage-controlled/digital-controlled oscillator, the frequency divider and the phase frequency detector are sequentially connected, the LDO is divided into a digital LDO and a low-noise high-power-supply rejection ratio LDO, the low-noise high-power-supply rejection ratio LDO is connected with the voltage-controlled/digital-controlled oscillator, the digital LDO is connected with other parts, the SPVT detection circuit is connected with the register and used for correcting the phase-locked loop before first use, during power-on at each time and during normal use so as to obtain the low-phase-noise high-precision clock frequency. The invention reduces the difficulty of phase-locked loop locking, shortens the locking time of the phase-locked loop and is particularly suitable for a wireless MCU.
Description
Technical Field
The invention relates to a high-performance phase-locked loop suitable for a wireless MCU (microprogrammed control Unit) and a frequency correction method thereof, belonging to the technical field of oscillators.
Background
The phase-locked loop is a main technology for generating high-precision high-frequency clocks in a communication chip, a CPU/MCU chip and a storage chip. In the wireless MCU, a high-frequency phase-locked loop works above GHz, and a core device voltage-controlled oscillator (VCO) of the phase-locked loop works at 2 times of the frequency of the phase-locked loop. And the free running frequency of the VCO varies greatly (e.g., 20% -30% difference in Temperature under a 55nm CMOS process) with variations in process corner (P-process), supply Voltage (V-Voltage), and Temperature (T-Temperature). The prior phase-locked loop technology adopts larger VCO gain (KVCO, unit: MHz/V) to cover the influence of PVT on VCO oscillation frequency, and the scheme has the defects of increasing the locking difficulty and locking time of the phase-locked loop and wasting power consumption; moreover, in order to lock quickly, the bandwidth of the phase-locked loop has to be increased, deteriorating the phase noise of the phase-locked loop.
Disclosure of Invention
The invention aims to provide a phase-locked loop suitable for a wireless MCU (microprogrammed control Unit), which reduces the locking difficulty of the phase-locked loop, shortens the locking time, reduces the phase noise and the power consumption of the phase-locked loop and provides an on-chip low-phase-noise high-precision clock for a wireless MCU chip.
The technical scheme is as follows:
a high-performance phase-locked loop suitable for a wireless MCU comprises a phase frequency detector, a charge pump, a loop filter, a voltage-controlled/digital controlled oscillator, a frequency divider, an LDO (low-voltage linear regulator), an SPVT (sinusoidal pulse velocity vector) detection circuit and a register; the phase frequency detector, the charge pump, the loop filter, the voltage-controlled/digital-controlled oscillator, the frequency divider and the phase frequency detector are sequentially connected, the LDO is divided into a digital LDO and a low-noise high-power-supply rejection ratio LDO, the low-noise high-power-supply rejection ratio LDO is connected with the voltage-controlled/digital-controlled oscillator, the digital LDO is connected with other parts, the SPVT detection circuit is connected with the register and used for correcting the phase-locked loop before first use, during power-on at each time and during normal use so as to obtain the low-phase-noise high-precision clock frequency.
Further, the SPVT detection circuit comprises an open-loop frequency spectrum detection circuit (S), a process corner detection circuit (P), a voltage detection circuit (V) and a temperature detection circuit (T).
Furthermore, the register stores preset ambient temperature and transistor junction temperature before the phase-locked loop is used for the first time, and a calibrated LDO control word and a switched capacitor control word, wherein the calibrated switched capacitor control word is used for adjusting a tuning switched capacitor of the voltage-controlled/digital-controlled oscillator, and the calibrated LDO control word is used for adjusting the output voltage of the LDO.
A high-performance phase-locked loop frequency correction method suitable for a wireless MCU adopts the high-performance phase-locked loop suitable for the wireless MCU, and writes preset ambient temperature, transistor junction temperature, calibrated LDO control words and switched capacitor control words into a register before the high-performance phase-locked loop is used for the first time; after each power-on, the content in the register is introduced, the temperature detection result detected by the SPVT detection circuit is combined, the transconductance of the voltage-controlled/digital-controlled oscillator is adjusted to the required transconductance of the voltage-controlled oscillator under the preset junction temperature by adjusting the bias current, and the free oscillation frequency of the voltage-controlled/digital-controlled oscillator is adjusted to the frequency required to be locked by adjusting the switch capacitor of the voltage-controlled/digital-controlled oscillator; in the normal use process, the phase-locked loop is enabled to quickly lock and output a low-phase noise high-precision clock by starting the low-noise high-power-supply rejection ratio LDO.
The steps of calibration before first use are:
step S101: detecting a process corner of the chip, and taking the regulated and adapted LDO output voltage as a calibrated LDO control word;
step S102: performing open-loop frequency spectrum detection on the voltage-controlled/digital-controlled oscillator, and adjusting the output frequency of a switch capacitor of the voltage-controlled/digital-controlled oscillator to be used as a calibrated switch capacitor control word;
step S103: presetting an ambient temperature and a transistor junction temperature;
step S104: and writing the preset ambient temperature, the transistor junction temperature, the calibrated LDO control word and the switched capacitor control word into a register.
The correction steps after each power-on are as follows:
step S201: leading in a calibrated LDO control word and a switched capacitor control word from a register;
step S202: the SPVT detection circuit detects the temperature;
step S203: adjusting the transconductance of the voltage-controlled/digital-controlled oscillator to adapt to the preset junction temperature by adjusting the bias current;
step S204: the SPVT detection circuit carries out open-loop spectrum detection, and further adjusts the output frequency through the switch capacitor of the voltage-controlled/digital-controlled oscillator.
The steps of correction in normal use are as follows:
step S301: starting a low-noise high-power supply rejection ratio LDO;
step S302: starting a phase-locked loop;
step S303: the phase-locked loop rapidly locks and outputs a low phase noise high precision clock.
Has the advantages that:
1) the invention adopts systematic correction of the influence of PVT change on the VCO, so that the VCO has only a small error with the required locking frequency under free oscillation, thereby greatly reducing the KVCO.
The difficulty of locking the phase-locked loop is reduced, the locking time is shortened, the phase noise and the power consumption of the phase-locked loop are reduced, and a solution is provided for realizing a low-phase-noise high-precision clock of the wireless MCU.
Drawings
FIG. 1 is a diagram illustrating a phase-locked loop structure according to the present invention;
FIG. 2 is a flow chart of calibration of the phase locked loop prior to first use;
FIG. 3 is a flowchart illustrating calibration of the PLL at each power-up;
FIG. 4 is a flowchart illustrating calibration of a phase locked loop during normal operation;
wherein: 1 is an SPVT detection circuit, and 2 is a register.
Detailed Description
The invention is described in detail below with reference to the following figures and specific examples:
as shown in fig. 1, a high-performance phase-locked loop suitable for a wireless MCU includes a phase frequency detector, a charge pump, a loop filter, a voltage-controlled/digital-controlled oscillator, a frequency divider, an LDO, an SPVT detection circuit 1, and a register 2; the phase frequency detector, the charge pump, the loop filter, the voltage-controlled/digital-controlled oscillator, the frequency divider and the phase frequency detector are sequentially connected, the LDO is divided into a digital LDO and a low-noise high-power-supply rejection ratio LDO, the low-noise high-power-supply rejection ratio LDO is connected with the voltage-controlled/digital-controlled oscillator, the digital LDO is connected with other parts, the SPVT detection circuit is connected with the register and used for correcting the phase-locked loop before first use, during power-on at each time and during normal use so as to obtain the low-phase-noise high-precision clock frequency.
The detection circuit comprises an open-loop frequency spectrum detection circuit, a process angle detection circuit, a voltage detection circuit and a temperature detection circuit.
The register stores preset ambient temperature and transistor junction temperature before the phase-locked loop is used for the first time, and calibrated LDO control words and switched capacitor control words, wherein the calibrated switched capacitor control words are used for adjusting the tuning switched capacitor of the voltage-controlled/digital-controlled oscillator, and the calibrated LDO control words are used for adjusting the output voltage of the LDO.
A high-performance phase-locked loop frequency correction method suitable for a wireless MCU adopts the high-performance phase-locked loop suitable for the wireless MCU, and writes preset ambient temperature, transistor junction temperature, calibrated LDO control words and switched capacitor control words into a register before the high-performance phase-locked loop is used for the first time; after each power-on, the content in the register is introduced, the temperature detection result detected by the SPVT detection circuit is combined, the transconductance of the voltage-controlled/digital-controlled oscillator is adjusted to the required transconductance of the voltage-controlled oscillator under the preset junction temperature by adjusting the bias current, and the free oscillation frequency of the voltage-controlled/digital-controlled oscillator is adjusted to the frequency required to be locked by adjusting the switch capacitor of the voltage-controlled/digital-controlled oscillator; in the normal use process, the phase-locked loop is enabled to quickly lock and output a low-phase noise high-precision clock by starting the low-noise high-power-supply rejection ratio LDO.
The steps of calibration before first use are:
step S101: detecting a process corner of the chip, and taking the regulated and adapted LDO output voltage as a calibrated LDO control word;
step S102: performing open-loop frequency spectrum detection on the voltage-controlled/digital-controlled oscillator, and adjusting the output frequency of a switch capacitor of the voltage-controlled/digital-controlled oscillator to be used as a calibrated switch capacitor control word;
step S103: presetting an ambient temperature and a transistor junction temperature;
step S104: and writing preset ambient temperature and transistor junction temperature, and calibrated LDO control words and switched capacitor control words into a register.
The correction steps after each power-on are as follows:
step S201: leading in a calibrated LDO control word and a switched capacitor control word from a register;
step S202: the SPVT detection circuit detects the temperature;
step S203: adjusting the transconductance of the voltage-controlled/digital-controlled oscillator to adapt to the preset junction temperature by adjusting the bias current;
step S204: the SPVT detection circuit carries out open-loop spectrum detection, and further adjusts the output frequency through the switch capacitor of the voltage-controlled/digital-controlled oscillator.
The steps of correction in normal use are as follows:
step S301: starting the LDO with low noise and high power supply rejection ratio;
step S302: starting a phase-locked loop;
step S303: the phase-locked loop rapidly locks and outputs a low phase noise high precision clock.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and scope of the present invention are intended to be covered thereby.
Claims (6)
1. A high performance phase-locked loop suitable for wireless MCU, its characterized in that: the circuit comprises a phase frequency detector, a charge pump, a loop filter, a voltage-controlled/digital-controlled oscillator, a frequency divider, an LDO (low dropout regulator), an SPVT (pulse voltage regulator) detection circuit (1) and a register (2); the phase frequency detector, the charge pump, the loop filter, the voltage-controlled/digital-controlled oscillator, the frequency divider and the phase frequency detector are sequentially connected, the LDO is divided into a digital LDO and a low-noise high-power-supply rejection ratio LDO, the low-noise high-power-supply rejection ratio LDO is connected with the voltage-controlled/digital-controlled oscillator, the digital LDO is connected with other parts, and the SPVT detection circuit is connected with the register and used for correcting the phase-locked loop before first use, during power-on every time and during normal use so as to obtain low-phase-noise high-precision clock frequency; the SPVT detection circuit comprises an open-loop frequency spectrum detection circuit, a process corner detection circuit, a voltage detection circuit and a temperature detection circuit.
2. A high performance phase locked loop adapted for use in a wireless MCU as defined in claim 1, wherein: the register stores preset ambient temperature and transistor junction temperature before the phase-locked loop is used for the first time, and calibrated LDO control words and switched capacitor control words, wherein the calibrated switched capacitor control words are used for adjusting the tuning switched capacitor of the voltage-controlled/digital-controlled oscillator, and the calibrated LDO control words are used for adjusting the output voltage of the LDO.
3. A high-performance phase-locked loop frequency correction method suitable for a wireless MCU is characterized in that: using a high performance phase locked loop adapted for use in a wireless MCU as claimed in any one of claims 1 to 2, writing preset ambient and transistor junction temperatures, calibrated LDO control words and switched capacitor control words into a register before first use; after each power-on, the content in the register is introduced, the temperature detection result detected by the SPVT detection circuit is combined, the transconductance of the voltage-controlled/digital-controlled oscillator is adjusted to the required transconductance of the voltage-controlled oscillator under the preset junction temperature by adjusting the bias current, and the free oscillation frequency of the voltage-controlled/digital-controlled oscillator is adjusted to the frequency required to be locked by adjusting the switch capacitor of the voltage-controlled/digital-controlled oscillator; in the normal use process, the phase-locked loop is enabled to quickly lock and output a low-phase-noise high-precision clock by starting the low-noise high-power-supply-rejection-ratio LDO.
4. A correction method as claimed in claim 3, characterized in that: the steps of calibration before first use are:
step S101: detecting a process angle of the chip, and taking the regulated and adapted LDO output voltage as a calibrated LDO control word;
step S102: performing open-loop frequency spectrum detection on the voltage-controlled/digital-controlled oscillator, and adjusting the output frequency of a switch capacitor of the voltage-controlled/digital-controlled oscillator to be used as a calibrated switch capacitor control word;
step S103: presetting an ambient temperature and a transistor junction temperature;
step S104: and writing the preset ambient temperature, the transistor junction temperature, the calibrated LDO control word and the switched capacitor control word into a register.
5. The correction method according to claim 3, characterized in that: the correction steps after each power-on are as follows:
step S201: leading in a calibrated LDO control word and a switch capacitor control word from a register;
step S202: the SPVT detection circuit detects the temperature;
step S203: adjusting the transconductance of the voltage-controlled/digital-controlled oscillator to adapt to the preset junction temperature by adjusting the bias current;
step S204: the SPVT detection circuit carries out open-loop spectrum detection, and further adjusts the output frequency through the switch capacitor of the voltage-controlled/digital-controlled oscillator.
6. The correction method according to claim 3, characterized in that: the steps of correction in normal use are as follows:
step S301: starting the LDO with low noise and high power supply rejection ratio;
step S302: starting a phase-locked loop;
step S303: the phase-locked loop quickly locks and outputs a low phase noise high precision clock.
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| GB2491501B (en) * | 2008-09-05 | 2013-04-10 | Icera Canada ULC | Method and system for calibrating a frequency synthesizer |
| US8358159B1 (en) * | 2011-03-10 | 2013-01-22 | Applied Micro Circuits Corporation | Adaptive phase-locked loop (PLL) multi-band calibration |
| CN103973305B (en) * | 2014-05-23 | 2017-08-08 | 武汉大学 | A kind of low noise phaselocked loop with frequency self-correction function |
| CN107005244B (en) * | 2017-02-08 | 2020-05-05 | 香港应用科技研究院有限公司 | Gain calibration of direct modulation synthesizer using look-up table search by decreasing count of overflow counter |
| US10326454B2 (en) * | 2017-06-02 | 2019-06-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | All-digital phase locked loop using switched capacitor voltage doubler |
| US10594323B2 (en) * | 2018-06-13 | 2020-03-17 | Movellus Circuits, Inc. | Locked loop circuit and method with digitally-controlled oscillator (DCO) gain normalization |
| DE102018216614A1 (en) * | 2018-09-27 | 2020-04-02 | Infineon Technologies Ag | CALIBRATING AN INJECTION-SYNCHRONIZED OSCILLATOR |
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