CN113903313B

CN113903313B - Gate driving circuit

Info

Publication number: CN113903313B
Application number: CN202111114111.1A
Authority: CN
Inventors: 陈宥任; 蔡孟杰; 彭佳添
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2021-01-06
Filing date: 2021-09-23
Publication date: 2023-10-03
Anticipated expiration: 2041-09-23
Also published as: TWI746343B; TW202228118A; CN113903313A

Abstract

A gate driving circuit is provided. The gate driving circuit comprises a shift register circuit coupled in series, wherein the shift register circuit of the N-th stage comprises a pull-up circuit, a pull-down circuit, a voltage stabilizing circuit, an output stage circuit and a first capacitor. The pull-up circuit is used for pulling up the first driving signal. The pull-down circuit pulls down the first driving signal according to the first clock signal and outputs the second driving signal. The voltage stabilizing circuit stabilizes the voltage value of the first driving signal according to the direct current common voltage. The output stage circuit generates an N-th stage gate driving signal according to the first driving signal and the second driving signal. The first capacitor is provided with a first electrode for receiving a first driving signal, and a second electrode of the first capacitor receives an N-th stage grid driving signal.

Description

Gate driving circuit

Technical Field

The present invention relates to a gate driving circuit, and more particularly, to a gate driving circuit for a display panel.

Background

Nowadays, the resolution requirement of the display panel is gradually increasing, and when the resolution is increasing, the Gate load of the Gate driver-on-array (GOA) is increased, so that the size of the transistor of the output stage of the Gate driver circuit must be increased accordingly, so as to improve the output capability of the Gate driver circuit. However, the size of the transistor increases, and the size of the frame and the size of the parasitic capacitance of the display panel also increase, so that the output stage of the gate driving circuit generates a leakage phenomenon, and even the gate driving signal has a ripple (ripple) problem, thereby affecting the display quality.

Disclosure of Invention

In view of the above, the present invention provides a gate driving circuit capable of improving the voltage stabilizing capability of the gate driving circuit.

The gate driving circuit of the invention comprises a plurality of shift register circuits which are connected in series, wherein the shift register circuit of the N-th stage comprises a pull-up circuit, a pull-down circuit, a voltage stabilizing circuit, an output stage circuit and a first capacitor. The pull-up circuit is used for pulling up the first driving signal. The pull-down circuit pulls down the first driving signal according to the first clock signal and outputs the second driving signal. The voltage stabilizing circuit stabilizes the voltage value of the first driving signal according to the direct current common voltage. The output stage circuit generates an N-th stage gate driving signal according to the first driving signal and the second driving signal. The first capacitor is provided with a first electrode for receiving a first driving signal, and a second electrode of the first capacitor receives an N-th stage grid driving signal.

Based on the above, the gate driving circuit of the present invention may be coupled in series with each other through a plurality of shift register circuits, wherein the shift register circuit of the nth stage may stabilize the voltage value of the first driving signal received by the output stage circuit according to the dc common voltage through the voltage stabilizing circuit. Therefore, the grid driving signal generated by the N-stage shift register circuit can be stabilized, and the voltage stabilizing capability of the grid driving circuit is further improved.

In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic diagram of an nth shift register circuit according to an embodiment of the invention.

Fig. 2 is a schematic partial cross-sectional view of an nth stage shift register circuit according to an embodiment of the invention.

Fig. 3 is a schematic diagram of an nth shift register circuit according to another embodiment of the present invention.

Reference numerals illustrate:

100. 400: n-th shift register circuit

110. 450: pull-up circuit

120. 460: pull-down circuit

130. 470: voltage stabilizing circuit

140. 480: output stage circuit

301 to 303: metal layer

310. 320: insulating layer

C1-C3: capacitance device

CK. CK 1-CK 4: clock signal

D2U: second scanning direction signal

Gn: n-th stage gate driving signal

Gn-1: front stage gate drive signal

Gn+1: post-stage gate drive signal

M1 to M29: transistor with a high-voltage power supply

Sn: third drive signal

Sn': fourth drive signal

OUT: output end of N-th shift register circuit

Pn: a second driving signal

Qn: a first driving signal

Qn-2, qn-4: front stage drive signal

U2D: first scanning direction signal

VCOM: common voltage

VGHD, VSS, VSSQ: voltage (V)

XCK: inverse clock signal

Detailed Description

The term "coupled" as used throughout this disclosure (including the claims) may refer to any direct or indirect connection. For example, if a first device couples (or connects) to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections. The terms first, second and the like in the description (including the claims) are used for naming the elements or distinguishing between different embodiments or ranges and are not used for limiting the upper or lower limit of the number of elements or the order of the elements.

Please refer to fig. 1. Fig. 1 is a circuit diagram of an nth shift register circuit according to an embodiment of the invention. In fig. 1, the shift register circuit 100 of the nth stage includes a pull-up circuit 110, a pull-down circuit 120, a voltage stabilizing circuit 130, an output stage circuit 140 and a capacitor C1. The N-th shift register circuits 100 can be serially coupled to each other to form a gate driving circuit for a display panel, wherein the display panel can be a Liquid Crystal Display (LCD) for driving the display panel by using a plurality of gate driving signals Gn and scanning signals provided by the gate driving circuit. In the present embodiment, the pull-up circuit 110 is configured to pull up the first driving signal Qn. The pull-down circuit 120 receives the first clock signal CK, and pulls down the first driving signal Qn according to the first clock signal CK, and may output the second driving signal Pn. The voltage stabilizing circuit 130 receives a dc common voltage VCOM and is used for stabilizing the voltage value of the first driving signal Qn according to the common voltage VCOM. The output stage circuit 140 receives the first driving signal Qn and the second driving signal Pn, and generates an nth stage gate driving signal Gn according to the first driving signal Qn and the second driving signal Pn, wherein N is any positive integer greater than 1. The first capacitor C1 has a first electrode for receiving the first driving signal Qn and a second electrode opposite to the first electrode for receiving the nth stage gate driving signal Gn.

In detail, the pull-up circuit 110 is composed of transistors M1 and M2. The first terminal of the transistor M1 receives the first scan direction signal U2D, and the control terminal (gate) of the transistor M1 receives the pre-gate driving signal Gn-1. The first terminal of the transistor M2 receives the second scan direction signal D2U, the second terminals of the transistors M1 and M2 together receive the first driving signal Qn, and the control terminal of the transistor M2 receives the gate driving signal gn+1 at the subsequent stage. The pull-up circuit 110 can pull up the first driving signal Qn according to the front gate driving signal Gn-1 and the rear gate driving signal gn+1 to select the first scanning direction signal U2D or the second scanning direction signal D2U.

It should be noted that, in the present embodiment, the first scan direction signal U2D is used to indicate the scan direction of the gate driving circuit to be a first direction (e.g. scan from above the display panel (not shown) toward below the display panel), and the second scan direction signal D2U is used to indicate the scan direction of the gate driving circuit to be a second direction (e.g. scan from below the display panel toward above the display panel). In addition, in the present embodiment, the front stage gate driving signal Gn-1 and the rear stage gate driving signal gn+1 can be the gate driving signals generated by the shift register circuits of the N-1 stage and the n+1 stage, respectively, wherein the number of N can be changed according to the actual requirement, and the present invention is not limited thereto.

In the present embodiment, the pull-down circuit 120 includes transistors M3 and M4 and a third capacitor C3. The third capacitor C3 has a first electrode for receiving the first clock signal CK, so that the third capacitor C3 can generate the second driving signal Pn on a second electrode of the third capacitor C3 opposite to the first electrode according to the first clock signal CK. The first terminal of the transistor M3 and the control terminal of the transistor M4 commonly receive the second driving signal Pn, the control terminal of the transistor M3 and the first terminal of the transistor M4 commonly receive the first driving signal Qn, and the second terminal of the transistor M3 and the second terminal of the transistor M4 commonly receive the first voltage VSS. The pull-down circuit 120 is enabled to pull down the first driving signal Qn according to the first clock signal CK and output the second driving signal Pn.

In the present embodiment, the voltage stabilizing circuit 130 is formed by the second capacitor C2. The second capacitor C2 has a first electrode for receiving the first driving signal Qn, and a second electrode opposite to the first electrode for receiving a dc common voltage VCOM, so that the second capacitor C2 can stabilize the voltage value of the first driving signal Qn according to the common voltage VCOM.

In the present embodiment, the output stage 140 includes transistors M5, M6, and M7. The control terminal of the transistor M5 receives the second driving signal Pn. The first terminal of the transistor M6 receives the first clock signal CK, and the control terminal of the transistor M6 receives the first driving signal Qn. The first terminal of the transistor M7 and the first terminal of the transistor M5 are coupled to the output terminal OUT, the control terminal of the transistor M7 receives the inverted clock signal XCK, and the second terminals of the transistors M5 and M7 commonly receive the first voltage VSS. The inverted clock signal XCK is an inverted signal of the clock signal CK. The output stage circuit 140 can generate the nth stage gate driving signal Gn at the output terminal OUT according to the first driving signal Qn and the second driving signal Pn, and serve as the output signal of the nth stage shift register circuit 100.

It should be noted that, in the gate driving circuit of the present invention, the voltage stabilizing circuit 130 may be added to the shift register circuit 100 of the nth stage to stabilize the voltage value of the first driving signal Qn received by the output stage circuit 140 according to the dc common voltage VCOM or other dc voltages. Thus, the gate driving signal Gn generated by the nth shift register circuit 100 can be stabilized without specifically increasing the size of the transistor M6 or the first capacitor C1, thereby improving the voltage stabilizing capability of the gate driving circuit.

For the implementation of the first capacitor C1 and the second capacitor C2 in the example of fig. 1, please refer to fig. 2. Fig. 2 is a schematic partial cross-sectional view of an nth stage shift register circuit according to an embodiment of the invention. In fig. 2, the nth shift register circuit may have metal layers 301 and 302, a transparent conductive layer 303, and insulating layers 310 and 320. The metal layers 301, 302 and the transparent conductive layer 303 may be arranged in sequence overlapping. In some embodiments, the perpendicular projection of transparent conductor layer 303 is no greater than metal layer 302. In this embodiment, the insulating layer 310 may be disposed between the metal layers 301 and 302, and the insulating layer 320 may be disposed between the metal layer 302 and the transparent conductive layer 303. Wherein the first driving signal Qn is coupled to the metal layer 302, the nth gate driving signal Gn is coupled to the metal layer 301, and the common voltage VCOM is coupled to the transparent conductive line layer 303 by way of a VIA. In this way, the first capacitor C1 may be formed between the metal layers 301 and 302 and the insulating layer 310, and the second capacitor C2 may be formed between the metal layer 302, the transparent conductive line layer 303 and the insulating layer 320.

It should be noted that, in the embodiment, the second capacitor C2 is generated by using the metal layer 302, the transparent conductive layer 303 and the insulating layer 320, so that the volume of the first capacitor C1 can be reduced and the voltage stabilizing capability of the gate driving circuit can be improved. Compared to the architecture of two capacitors (7T 2C) without the seven transistors having the capacitor C2, in the present embodiment, the capacitance of the first capacitor C1 can be reduced to 5.89 picofarads by adding the second capacitor C2 to make the shift register circuit of the nth stage be the architecture of three capacitors (7T 3C) of the seven transistors, so as to reduce the volume of the first capacitor C1 (the capacitance of the second capacitor C2 is 1.605 picofarads). In addition, the voltage stabilization of the 7T3C architecture can provide relatively large voltage stabilization capability at different temperatures (e.g., 25 degrees celsius and 85 degrees celsius). Incidentally, ripple can also be effectively reduced. Therefore, the voltage value of the first driving signal Qn can be stabilized through the second capacitor C2 on the premise of not affecting the size of the gate driving circuit, so that the voltage stabilizing capability of the gate driving circuit is improved, and unexpected technical effects are achieved.

Fig. 3 is a schematic diagram of an nth shift register circuit according to another embodiment of the present invention. In fig. 3, the nth shift register circuit 400 includes a pull-up circuit 450, a pull-down circuit 460, a voltage stabilizing circuit 470, an output stage circuit 480, and a first capacitor C1. In the present embodiment, the pull-up circuit 450 is composed of transistors M8 and M9. The first terminal of the transistor M8 receives the second clock signal CK2, the control terminal of the transistor M8 receives the previous driving signal (e.g., the previous four driving signals Qn-4 of the first driving signal Qn in the present embodiment, but the present invention is not limited thereto), and the second terminal of the transistor M8 outputs the third driving signal Sn. The first terminal of the transistor M9 receives the second voltage VGHD, the control terminal of the transistor M9 is coupled to the second terminal of the transistor M8, and the second terminal of the transistor M9 receives the first driving signal Qn. The pull-up circuit 450 can pull up the first driving signal Qn according to the previous driving signal Qn-4 based on the second clock signal CK2 and the second voltage VGHD.

In this embodiment, the pull-down circuit 460 includes transistors M10-M16. The transistor M10 may be coupled in a diode configuration, wherein an anode of the diode and the first terminal of the transistor M14 are commonly coupled to the control terminal of the transistor M14, and a cathode of the diode and the first terminals of the transistors M11 and M13 are commonly coupled to the first terminal of the transistor M14. The control terminals of the transistors M11 and M12 commonly receive the previous driving signal (e.g., the previous two-stage driving signal Qn-2 of the first driving signal Qn in the present embodiment, but the invention is not limited thereto). The control terminals of the transistors M13 and M15 and the first terminal of the transistor M16 commonly receive the first driving signal Qn. The first terminals of the transistors M12 and M15, the second terminal of the transistor M14, and the control terminal of the transistor M16 commonly receive the second driving signal Pn. The second terminals of the transistors M11, M12, M13, M15 and M16 commonly receive the third voltage VSSQ. The pull-down circuit 460 is enabled to pull down the first driving signal Qn according to the first clock signal CK1, the pre-stage driving signal Qn-2, the first driving signal Qn and the second driving signal Pn, and output the second driving signal Pn.

In the present embodiment, the voltage stabilizing circuit 470 is formed by the second capacitor C2. The second capacitor C2 has a first electrode receiving the first driving signal Qn, and a second electrode opposite to the first electrode receiving a dc common voltage VCOM, so that the second capacitor C2 can stabilize the voltage value of the first driving signal Qn according to the common voltage VCOM.

In this embodiment, the output stage 480 includes transistors M17-M29. Wherein transistors M19-M25 may have the same connection relationship with transistors M10-M16 in pull-down circuit 460. The first terminal of the transistor M19 receives the third clock signal CK3. The control terminals of the transistors M17 and M18 commonly receive the second driving signal Pn output by the pull-down circuit 460. The first ends of the transistors M18 and M27 commonly receive the third driving signal Sn. The control terminals of the transistors M26 and M27 are commonly coupled to the second terminal of the transistor M23. The first terminals of the transistors M25 and M28 and the control terminal of the transistor M29 commonly receive the first driving signal Qn, and the control terminal of the transistor M28 receives the fourth driving signal Sn' (which may be the post-M-stage driving signal of the third driving signal Sn in this embodiment, and M may be equal to 9, for example). The first terminal of the transistor M29 receives the fourth clock signal CK4. The first terminals of the transistors M17, M26 and M29 are commonly coupled to the output terminal OUT, and the second terminals of the transistors M17, M26 and M28 commonly receive the first voltage VSS. The second terminals of the transistors M18, M20-M22, M24, M25 and M27 commonly receive the third voltage VSSQ. The output stage circuit 480 generates the nth stage gate driving signal Gn at the output terminal OUT according to the third clock signal CK3, the previous stage driving signal Qn-2, the first driving signal Qn, the second driving signal Pn and the third driving signal Sn, and serves as an output signal of the nth stage shift register circuit 400.

In the above embodiments, the transistors M1 to M29 may be, for example, thin film transistors (Thin Film Transistor, TFTs) having N-type conductivity. The common voltage VCOM may be a dc potential or a ground potential. The first voltage VSS and the third voltage VSSQ may be ground potentials. The second voltage VGHD may be a gate high potential of direct current. In the above embodiments, the present invention is exemplified by the 7T2C and 22T1C structures and the second capacitor is configured as 7T3C and 22T2C structures, but the present invention is not limited thereto, and in other embodiments, other different structures (e.g. 3T1C structure, 4T2C structure, 5T1C structure, 6T2C structure) or any possible shift register circuit structure may be used for implementation.

In summary, the gate driving circuit of the present invention may be coupled to each other in series through a plurality of shift register circuits, wherein each stage of shift register circuit may stabilize the voltage value of the first driving signal received by the output stage circuit according to the dc common voltage through the voltage stabilizing circuit. Therefore, the grid driving signal generated by the shift register circuit can be stabilized on the premise of not increasing the frame size of the display panel, and the voltage stabilizing capability of the grid driving circuit is further improved.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A gate driving circuit includes a plurality of shift register circuits coupled in series, wherein the N-th shift register circuit includes:

a pull-up circuit for pulling up a first driving signal;

a pull-down circuit for pulling down the first driving signal according to a first clock signal;

the voltage stabilizing circuit comprises a second capacitor, and the voltage stabilizing circuit stabilizes the voltage value of the first driving signal according to a common voltage of direct current;

an output stage circuit for generating an N-th stage gate driving signal according to the first driving signal and a second driving signal; and

a first capacitor having a first electrode receiving the first driving signal, a second electrode receiving the N-th gate driving signal,

wherein the first capacitor is formed between a first metal layer and a second metal layer, the second capacitor is formed between the second metal layer and a transparent conductive line,

wherein the pull-up circuit comprises:

a first transistor, a first end of which receives a second clock signal, a control end of which receives a first front driving signal, and a second end of which outputs a third driving signal; and

a second transistor having a first end receiving a first voltage, a control end coupled to a second end of the first transistor, a second end receiving the first driving signal,

the pull-down circuit includes a first voltage controller, the pull-down circuit receives the first clock signal as an input signal and takes an output signal of the first voltage controller as the second driving signal, wherein the voltage controller includes:

a third transistor coupled in a diode configuration having an anode receiving the input signal;

a fourth transistor and a fifth transistor, the control ends of the fourth transistor and the fifth transistor commonly receive a second front-stage driving signal;

a sixth transistor and a seventh transistor, wherein the control ends of the sixth transistor and the seventh transistor receive the first driving signal together;

an eighth transistor having a first terminal coupled to the anode of the diode, a control terminal of the eighth transistor and first terminals of the fourth and sixth transistors being commonly coupled to the cathode of the diode, the fifth and seventh transistors being commonly coupled to the second terminal of the eighth transistor to generate the output signal of the voltage controller at the second terminal of the eighth transistor; and

the control terminal of the ninth transistor is coupled to the second terminal of the eighth transistor, and the second terminals of the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the ninth transistor commonly receive a second voltage.

2. The gate driving circuit of claim 1, wherein the second capacitor has a first electrode receiving the first driving signal and a second electrode receiving the common voltage.

3. The gate driving circuit of claim 1, wherein the first metal layer, the second metal layer and the transparent conductive line layer are sequentially overlapped.

4. The gate drive circuit of claim 1, further comprising:

a first insulating layer disposed between the first metal layer and the second metal layer; and

a second insulating layer arranged between the second metal layer and the transparent conducting wire layer.

5. The gate driving circuit of claim 1, wherein a vertical projection of the transparent conductive line layer is not larger than the second metal layer.

6. The gate driving circuit of claim 1, wherein the output stage receives a third clock signal as the input signal, the output stage comprising:

a second voltage controller having the same circuit structure as the first voltage controller;

a tenth transistor and an eleventh transistor, wherein the control ends of the tenth transistor and the eleventh transistor receive the second driving signal together;

a twelfth transistor and a thirteenth transistor, the twelfth transistor and the thirteenth transistor having a control terminal for receiving the output signal of the second voltage controller, the eleventh transistor and the thirteenth transistor having a first terminal for receiving the third driving signal, the eleventh transistor and the thirteenth transistor having a second terminal for receiving the second voltage;

a fourteenth transistor having a control terminal receiving a fourth driving signal, the tenth transistor, the twelfth transistor and the fourteenth transistor having second terminals receiving a third voltage; and

a fifteenth transistor having a first end receiving a fourth clock signal, the first end of the fourteenth transistor and the control end of the fifteenth transistor receiving the first driving signal together, the tenth transistor and the first end of the twelfth transistor and the second end of the fifteenth transistor receiving the nth stage gate driving signal together.