CN113903313A - Gate drive circuit - Google Patents
Gate drive circuit Download PDFInfo
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- CN113903313A CN113903313A CN202111114111.1A CN202111114111A CN113903313A CN 113903313 A CN113903313 A CN 113903313A CN 202111114111 A CN202111114111 A CN 202111114111A CN 113903313 A CN113903313 A CN 113903313A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Shift Register Type Memory (AREA)
- Liquid Crystal Display Device Control (AREA)
- Logic Circuits (AREA)
Abstract
A gate driving circuit is provided. The gate driving circuit comprises shift register circuits coupled in series, wherein the shift register circuit of the Nth stage comprises a pull-up circuit, a pull-down circuit, a voltage stabilizing circuit, an output stage circuit and a first capacitor. The pull-up circuit is used for pulling up the first driving signal. The pull-down circuit pulls down the first driving signal according to the first clock signal and outputs a second driving signal. The voltage stabilizing circuit stabilizes the voltage value of the first driving signal according to the common voltage of the direct current. The output stage circuit generates an Nth stage gate driving signal according to the first driving signal and the second driving signal. The first capacitor is provided with a first electrode for receiving a first driving signal, and a second electrode for receiving an Nth-level gate driving signal.
Description
Technical Field
The present invention relates to a gate driving circuit, and more particularly, to a gate driving circuit for a display panel.
Background
Nowadays, the resolution of the display panel is gradually increased, and as the resolution is increased, the Gate load of a Gate-on-array (GOA) circuit is increased, so that the size of the transistor of the output stage of the Gate driving circuit must be increased to improve the output capability of the Gate driving circuit. However, the increase of the size of the transistor also increases the size of the frame and the size of the parasitic capacitor of the display panel, and the output stage of the gate driving circuit may generate a leakage phenomenon, and even a ripple (ripple) problem of the gate driving signal may occur, thereby affecting the display quality.
Disclosure of Invention
In view of the above, the present invention provides a gate driving circuit, which can improve the voltage stabilizing capability of the gate driving circuit.
The grid driving circuit comprises a plurality of shift temporary storage circuits which are coupled in series, wherein the shift temporary storage circuit of the Nth level comprises a pull-up circuit, a pull-down circuit, a voltage stabilizing circuit, an output level circuit and a first capacitor. The pull-up circuit is used for pulling up the first driving signal. The pull-down circuit pulls down the first driving signal according to the first clock signal and outputs a second driving signal. The voltage stabilizing circuit stabilizes the voltage value of the first driving signal according to the common voltage of the direct current. The output stage circuit generates an Nth stage gate driving signal according to the first driving signal and the second driving signal. The first capacitor is provided with a first electrode for receiving a first driving signal, and a second electrode for receiving an Nth-level gate driving signal.
Based on the above, the gate driving circuit provided by the invention can be coupled in series through a plurality of shift register circuits, wherein the shift register circuit of the nth stage can stabilize the voltage value of the first driving signal received by the output stage circuit according to the dc common voltage through the voltage stabilizing circuit. Therefore, the grid driving signal generated by the shift register circuit of the Nth stage can be stabilized, and the voltage stabilizing capability of the grid driving circuit is further improved.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic diagram illustrating a shift register circuit of an nth stage according to an embodiment of the present invention.
Fig. 2 is a partial cross-sectional view of a shift register circuit of an nth stage according to an embodiment of the invention.
Fig. 3 is a schematic diagram of a shift register circuit of an nth stage according to another embodiment of the present invention.
Description of reference numerals:
100. 400: nth stage shift temporary storage circuit
110. 450: pull-up circuit
120. 460: pull-down circuit
130. 470: voltage stabilizing circuit
140. 480: output stage circuit
301-303: metal layer
310. 320, and (3) respectively: insulating layer
C1-C3: capacitor with a capacitor element
CK. CK 1-CK 4: clock signal
D2U: second scanning direction signal
Gn: nth stage gate drive signal
Gn-1: preceding stage gate drive signal
Gn + 1: back stage gate drive signal
M1-M29: transistor with a metal gate electrode
Sn: third drive signal
Sn': fourth drive signal
OUT: output end of Nth stage shift temporary storage circuit
Pn: second drive signal
Qn: a first drive signal
Qn-2, Qn-4: preceding stage drive signal
U2D: first scanning direction signal
VCOM: common voltage
VGHD, VSS, VSSQ: voltage of
XCK: inverted clock signal
Detailed Description
The term "coupled" as used throughout this disclosure, including the claims, may refer to any direct or indirect connection means. For example, if a first device couples (or connects) to a second device, it should be construed that the first device may be directly connected to the second device or the first device may be indirectly connected to the second device through other devices or some connection means. The terms "first," "second," and the like, as used throughout this disclosure, including the claims, are used to designate elements (elements) or to distinguish between different embodiments or ranges, and are not used to limit the number of elements, upper or lower, nor the order of the elements.
Please refer to fig. 1. Fig. 1 is a circuit diagram of a shift register circuit of an nth stage according to an embodiment of the present invention. In fig. 1, the shift register circuit 100 of the nth stage includes a pull-up circuit 110, a pull-down circuit 120, a voltage stabilizing circuit 130, an output stage circuit 140, and a capacitor C1. The plurality of nth stage shift register circuits 100 may be coupled in series to form a gate driving circuit for a display panel, wherein the display panel may be a Liquid Crystal Display (LCD), and the display panel is driven by a plurality of gate driving signals Gn and scanning signals provided by the gate driving circuit. In the present embodiment, the pull-up circuit 110 serves to pull up the first driving signal Qn. The pull-down circuit 120 receives the first clock signal CK, pulls down the first driving signal Qn according to the first clock signal CK, and outputs the second driving signal Pn. The voltage stabilizing circuit 130 receives the dc common voltage VCOM and stabilizes the voltage of the first driving signal Qn according to the common voltage VCOM. The output stage circuit 140 receives the first driving signal Qn and the second driving signal Pn, and generates the nth stage gate driving signal Gn according to the first driving signal Qn and the second driving signal Pn, where N is any positive integer greater than 1. The first capacitor C1 has a first electrode receiving the first driving signal Qn and a second electrode opposite to the first electrode receiving the nth-level gate driving signal Gn.
In detail, the pull-up circuit 110 is composed of transistors M1 and M2. A first terminal of the transistor M1 receives the first scan direction signal U2D, and a control terminal (gate) of the transistor M1 receives the previous stage gate driving signal Gn-1. The first terminal of the transistor M2 receives the second scan direction signal D2U, the second terminals of the transistors M1 and M2 commonly receive the first driving signal Qn, and the control terminal of the transistor M2 receives the post-stage gate driving signal Gn + 1. The pull-up circuit 110 can select the first scan direction signal U2D or the second scan direction signal D2U to pull up the first driving signal Qn according to the front stage gate driving signal Gn-1 and the rear stage gate driving signal Gn + 1.
It should be noted that, in the present embodiment, the first scan direction signal U2D indicates that the scan direction of the gate driving circuit is a first direction (e.g., scanning from above the display panel (not shown) to below the display panel), and the second scan direction signal D2U indicates that the scan direction of the gate driving circuit is a second direction (e.g., scanning from below the display panel to above the display panel). In addition, in the embodiment, the front stage gate driving signal Gn-1 and the back stage gate driving signal Gn +1 may be gate driving signals generated by the shift register circuits of the nth-1 stage and the (N + 1) th stage, respectively, where the number of N may be changed according to actual requirements, and the invention is not limited thereto.
In the present embodiment, the pull-down circuit 120 includes transistors M3 and M4 and a third capacitor C3. The third capacitor C3 has a first electrode receiving the first clock signal CK, such that the third capacitor C3 can generate the second driving signal Pn on a second electrode of the third capacitor C3 opposite to the first electrode according to the first clock signal CK. The first terminal of the transistor M3 and the control terminal of the transistor M4 commonly receive the second driving signal Pn, the control terminal of the transistor M3 and the first terminal of the transistor M4 commonly receive the first driving signal Qn, and the second terminals of the transistor M3 and the transistor M4 commonly receive the first voltage VSS. The pull-down circuit 120 may pull down the first driving signal Qn according to the first clock signal CK and output the second driving signal Pn.
In the present embodiment, the voltage stabilizing circuit 130 is formed by a second capacitor C2. The second capacitor C2 has a first electrode receiving the first driving signal Qn and a second electrode opposite to the first electrode for receiving the dc common voltage VCOM, so that the second capacitor C2 can stabilize the voltage of the first driving signal Qn according to the common voltage VCOM.
In the present embodiment, the output stage circuit 140 includes transistors M5, M6, and M7. The control terminal of the transistor M5 receives the second driving signal Pn. The first terminal of the transistor M6 receives the first clock signal CK, and the control terminal of the transistor M6 receives the first driving signal Qn. The first terminal of the transistor M7, the first terminal of the transistor M5, and the second terminal of the transistor M6 are coupled to the output terminal OUT, the control terminal of the transistor M7 receives the inverted clock signal XCK, and the second terminals of the transistors M5 and M7 commonly receive the first voltage VSS. The inverted clock signal XCK is an inverted signal of the clock signal CK. The output stage circuit 140 can generate the nth stage gate driving signal Gn at the output terminal OUT according to the first driving signal Qn and the second driving signal Pn, and serve as the output signal of the nth stage shift register circuit 100.
It is noted that, in the gate driving circuit of the present invention, the voltage stabilizing circuit 130 may be added to the shift register circuit 100 of the nth stage to stabilize the voltage value of the first driving signal Qn received by the output stage circuit 140 according to the dc common voltage VCOM or other dc voltages. Thus, the gate driving signal Gn generated by the nth stage shift register circuit 100 can be stabilized without particularly increasing the size of the transistor M6 or the first capacitor C1, thereby improving the voltage stabilizing capability of the gate driving circuit.
Referring to fig. 2, embodiments of the first capacitor C1 and the second capacitor C2 in the example of fig. 1 are shown. Fig. 2 is a partial cross-sectional view of a shift register circuit of an nth stage according to an embodiment of the invention. In fig. 2, the nth stage of shift register circuit may have metal layers 301 and 302, a transparent conductive layer 303, and insulating layers 310 and 320. The metal layers 301 and 302 and the transparent conductive layer 303 may be sequentially stacked. In some embodiments, the perpendicular projection of transparent wire layer 303 is no larger than metal layer 302. In this embodiment, the insulating layer 310 may be disposed between the metal layers 301 and 302, and the insulating layer 320 may be disposed between the metal layer 302 and the transparent conductive layer 303. Wherein the first driving signal Qn is coupled to the metal layer 302, the nth gate driving signal Gn is coupled to the metal layer 301, and the common voltage VCOM is coupled to the transparent conductive layer 303 by a VIA (VIA) method. In this way, the first capacitor C1 can be formed between the metal layers 301 and 302 and the insulating layer 310, and the second capacitor C2 can be formed between the metal layer 302, the transparent conductive line layer 303 and the insulating layer 320.
It should be noted that, in the embodiment, the metal layer 302, the transparent conductive line layer 303 and the insulating layer 320 are used to generate the second capacitor C2, so that the volume of the first capacitor C1 can be reduced, and the voltage stabilizing capability of the gate driving circuit can be improved. Compared with the architecture of two capacitors (7T2C) of seven transistors without the capacitor C2, in the present embodiment, the capacitance of the first capacitor C1 can be reduced to 5.89 picofarads by adding the second capacitor C2 to make the shift register circuit of the nth stage be the architecture of three capacitors (7T3C) of seven transistors, so as to reduce the volume of the first capacitor C1 (the capacitance of the second capacitor C2 is 1.605 picofarads). Additionally, under conditions of different temperatures (e.g., 25 degrees celsius and 85 degrees celsius), the regulation of the architecture of 7T3C may provide a relatively large regulation capability. Incidentally, the ripple can also be effectively reduced. Therefore, the voltage value of the first driving signal Qn can be stabilized by the second capacitor C2 without affecting the size of the gate driving circuit, so as to improve the voltage stabilizing capability of the gate driving circuit, thereby having unexpected technical effects.
Fig. 3 is a schematic diagram of a shift register circuit of an nth stage according to another embodiment of the present invention. In fig. 3, the shift register circuit 400 of the nth stage includes a pull-up circuit 450, a pull-down circuit 460, a voltage stabilizing circuit 470, an output stage circuit 480, and a first capacitor C1. In the present embodiment, the pull-up circuit 450 is composed of transistors M8 and M9. The first terminal of the transistor M8 receives the second clock signal CK2, the control terminal of the transistor M8 receives a previous driving signal (for example, the previous driving signal Qn-4 of the first driving signal Qn is shown in this embodiment, but the present invention is not limited thereto), and the second terminal of the transistor M8 outputs the third driving signal Sn. The first terminal of the transistor M9 receives the second voltage VGHD, the control terminal of the transistor M9 is coupled to the second terminal of the transistor M8, and the second terminal of the transistor M9 receives the first driving signal Qn. The pull-up circuit 450 can pull up the first driving signal Qn according to the previous driving signal Qn-4 based on the second clock signal CK2 and the second voltage VGHD.
In the present embodiment, the pull-down circuit 460 includes transistors M10-M16. The transistor M10 may be coupled in a diode configuration, an anode of the diode and the first terminal of the transistor M14 are coupled to receive the first clock signal CK1, and a cathode of the diode and the first terminals of the transistors M11 and M13 are coupled to the control terminal of the transistor M14. The control terminals of the transistors M11 and M12 commonly receive a previous driving signal (for example, the previous driving signal Qn-2 of the first driving signal Qn can be used in this embodiment, but the invention is not limited thereto). The control terminals of the transistors M13 and M15 and the first terminal of the transistor M16 commonly receive the first driving signal Qn. The transistor M12 receives the second driving signal Pn in common with the first terminal of the transistor M15, the second terminal of the transistor M14, and the control terminal of the transistor M16. The second terminals of the transistors M11, M12, M13, M15, and M16 commonly receive the third voltage VSSQ. The pull-down circuit 460 can pull down the first driving signal Qn according to the first clock signal CK1, the previous driving signal Qn-2, the first driving signal Qn and the second driving signal Pn, and output the second driving signal Pn.
In the present embodiment, the voltage stabilizing circuit 470 is formed by a second capacitor C2. The second capacitor C2 has a first electrode receiving the first driving signal Qn, and a second electrode opposite to the first electrode receiving a dc common voltage VCOM, so that the second capacitor C2 can stabilize the voltage of the first driving signal Qn according to the common voltage VCOM.
In the present embodiment, the output stage circuit 480 includes transistors M17-M29. Wherein the transistors M19-M25 and the transistors M10-M16 in the pull-down circuit 460 can have the same connection relationship. A first terminal of the transistor M19 receives the third clock signal CK 3. The transistor M17 and the control terminal of M18 commonly receive the second driving signal Pn output by the pull-down circuit 460. The first terminals of the transistors M18 and M27 commonly receive the third driving signal Sn. The control terminals of the transistors M26 and M27 are commonly coupled to the second terminal of the transistor M23. The first terminal of the transistors M25 and M28 and the control terminal of the transistor M29 commonly receive the first driving signal Qn, and the control terminal of the transistor M28 receives the fourth driving signal Sn' (in the embodiment, the latter M-stage driving signal of the third driving signal Sn, M may be equal to 9, for example). A first terminal of the transistor M29 receives the fourth clock signal CK 4. The first terminals of the transistors M17, M26 and M29 are commonly coupled to the output terminal OUT, and the second terminals of the transistors M17, M26 and M28 commonly receive the first voltage VSS. The second terminals of the transistors M18, M20-M22, M24, M25 and M27 commonly receive a third voltage VSSQ. The output stage circuit 480 may generate the nth stage gate driving signal Gn at the output terminal OUT according to the third clock signal CK3, the previous stage driving signal Qn-2, the first driving signal Qn, the second driving signal Pn, and the third driving signal Sn, and may be used as an output signal of the nth stage shift register circuit 400.
In the above embodiments, the transistors M1 to M29 may be, for example, Thin Film Transistors (TFTs) having N-type conductivity. The common voltage VCOM may be a dc potential or a ground potential. The first voltage VSS and the third voltage VSSQ may be ground potentials. The second voltage VGHD may be a gate high potential of a direct current. In the above embodiments, the invention is described by taking the architectures of 7T2C and 22T1C and the architectures of 7T3C and 22T2C as examples, but the invention is not limited thereto, and in other embodiments, different architectures (for example, the architecture of 3T1C, the architecture of 4T2C, the architecture of 5T1C, the architecture of 6T 2C) or any possible architecture of shift register circuit may be used for implementation.
In summary, the gate driving circuit provided by the present invention can be coupled in series through a plurality of shift register circuits, wherein each stage of the shift register circuit can stabilize the voltage value of the first driving signal received by the output stage circuit according to the dc common voltage through the voltage stabilizing circuit. Therefore, the grid driving signal generated by the shift temporary storage circuit can be stabilized on the premise of not increasing the size of the frame of the display panel, and the voltage stabilizing capability of the grid driving circuit is further improved.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (11)
1. A gate driving circuit includes a plurality of shift register circuits coupled in series, wherein the shift register circuit of the Nth stage includes:
a pull-up circuit for pulling up a first driving signal;
a pull-down circuit for pulling down the first driving signal according to a first clock signal;
a voltage stabilizing circuit for stabilizing the voltage value of the first driving signal according to a common voltage of the direct current;
an output stage circuit for generating an Nth stage gate drive signal according to the first drive signal and a second drive signal; and
and the first capacitor is provided with a first electrode for receiving the first driving signal, and a second electrode for receiving the Nth-stage gate driving signal.
2. The gate driving circuit of claim 1, wherein the voltage stabilizing circuit comprises:
a second capacitor having a first electrode for receiving the first driving signal and a second electrode for receiving the common voltage.
3. The gate driving circuit as claimed in claim 2, wherein the first capacitor is formed between a first metal layer and a second metal layer, the second capacitor is formed between the second metal layer and a transparent conductive layer, and the first metal layer, the second metal layer and the transparent conductive layer are sequentially overlapped.
4. The gate drive circuit of claim 3, further comprising:
a first insulating layer disposed between the first metal layer and the second metal layer; and
a second insulating layer disposed between the second metal layer and the transparent conductive layer.
5. The gate driving circuit of claim 3, wherein a vertical projection of the transparent conductive line layer is not larger than the second metal layer.
6. The gate driving circuit as claimed in claim 1, wherein the pull-up circuit comprises:
a first transistor, a first end of which receives a first scanning direction signal, and a control end of which receives a preceding stage gate driving signal; and
a second transistor, a first end of which receives a second scanning direction signal, a second end of which receives the first driving signal together with a second end of the first transistor, and a control end of which receives a back-stage gate driving signal.
7. The gate driving circuit of claim 1, wherein the pull-down circuit comprises:
a first transistor;
a second transistor; and
a third capacitor having a first electrode for receiving the first clock signal and generating the second driving signal on a second electrode of the third capacitor according to the first clock signal,
the first end of the first transistor and the control end of the second transistor receive the second driving signal together, the control end of the first transistor and the first end of the second transistor receive the first driving signal together, and the second ends of the first transistor and the second transistor receive a first voltage together.
8. The gate driving circuit as claimed in claim 1, wherein the output stage circuit comprises:
a first transistor, the control end of which receives the second driving signal;
a second transistor, a first end of which receives the first clock signal, and a control end of which receives the first driving signal; and
a third transistor, a first end of which receives the nth stage gate driving signal together with the first end of the first transistor and the second end of the second transistor, a control end of the third transistor receives a reverse clock signal, and a second end of the third transistor and the first transistor receive a first voltage together.
9. The gate driving circuit as claimed in claim 1, wherein the pull-up circuit comprises:
a first transistor, a first end of which receives a second clock signal, a control end of which receives a first preceding stage driving signal, and a second end of which outputs a third driving signal; and
a second transistor, a first terminal of which receives a first voltage, a control terminal of which is coupled to a second terminal of the first transistor, and a second terminal of which receives the first driving signal.
10. The gate driving circuit of claim 9, wherein the pull-down circuit comprises a first voltage controller, the pull-down circuit receives the first clock signal as an input signal and outputs an output signal of the first voltage controller as the second driving signal, wherein the voltage controller comprises:
a third transistor coupled in a diode configuration and having an anode receiving the input signal;
a fourth transistor and a fifth transistor, wherein the control ends of the fourth transistor and the fifth transistor commonly receive a second previous driving signal;
a sixth transistor and a seventh transistor, wherein the control terminals of the sixth transistor and the seventh transistor commonly receive the first driving signal;
an eighth transistor, a first terminal of which is coupled to the anode of the diode, a control terminal of the eighth transistor and first terminals of the fourth transistor and the sixth transistor are coupled to the cathode of the diode, and first terminals of the fifth transistor and the seventh transistor are coupled to a second terminal of the eighth transistor, so as to generate an output signal of the voltage controller at the second terminal of the eighth transistor; and
a ninth transistor, a first terminal of which receives the first driving signal, a control terminal of which is coupled to a second terminal of the eighth transistor, and second terminals of the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the ninth transistor commonly receive a second voltage.
11. The gate driving circuit of claim 10, wherein the output stage circuit receives a third clock signal as an input signal, the output stage circuit comprising:
a second voltage controller having the same circuit architecture as the first voltage controller;
a tenth transistor and an eleventh transistor, wherein control terminals of the tenth transistor and the eleventh transistor commonly receive the second driving signal;
a twelfth transistor and a thirteenth transistor, wherein the twelfth transistor and the control terminal of the thirteenth transistor commonly receive the output signal of the second voltage controller, the eleventh transistor and the first terminal of the thirteenth transistor commonly receive the third driving signal, and the second terminal of the eleventh transistor and the second terminal of the thirteenth transistor commonly receive the second voltage;
a fourteenth transistor, a control terminal of which receives a fourth driving signal, and second terminals of the tenth transistor, the twelfth transistor and the fourteenth transistor commonly receive a third voltage; and
a fifteenth transistor, a first terminal of which receives a fourth clock signal, a first terminal of the fourteenth transistor and a control terminal of the fifteenth transistor commonly receive the first driving signal, and a first terminal of the tenth transistor and the twelfth transistor and a second terminal of the fifteenth transistor commonly receive the nth-stage gate driving signal.
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| TW110100425 | 2021-01-06 | ||
| TW110100425A TWI746343B (en) | 2021-01-06 | 2021-01-06 | Gate driving circuit |
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| CN113903313A true CN113903313A (en) | 2022-01-07 |
| CN113903313B CN113903313B (en) | 2023-10-03 |
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| CN105719613A (en) * | 2016-04-22 | 2016-06-29 | 上海天马微电子有限公司 | Array substrate, display panel and display device |
| CN108962166A (en) * | 2018-07-23 | 2018-12-07 | 深圳市华星光电技术有限公司 | GOA circuit and liquid crystal display device with the GOA circuit |
| CN109036303A (en) * | 2018-07-24 | 2018-12-18 | 武汉华星光电技术有限公司 | Goa circuit and display device |
| CN108682380A (en) * | 2018-07-26 | 2018-10-19 | 京东方科技集团股份有限公司 | Shift register and its driving method, gate driving circuit and display device |
| CN110619839A (en) * | 2019-03-08 | 2019-12-27 | 友达光电股份有限公司 | Gate drive circuit and control method of shift register |
| CN110706636A (en) * | 2019-03-11 | 2020-01-17 | 友达光电股份有限公司 | Shift register circuit and gate driver |
| CN111179742A (en) * | 2020-02-12 | 2020-05-19 | 武汉华星光电技术有限公司 | Display panel, grid drive circuit and electronic device |
| CN211529585U (en) * | 2020-08-17 | 2020-09-18 | 深圳市华星光电半导体显示技术有限公司 | Grid driving circuit and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113903313B (en) | 2023-10-03 |
| TWI746343B (en) | 2021-11-11 |
| TW202228118A (en) | 2022-07-16 |
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