CN113900984A - Circuit and server for interconnection and switching between single node and multiple nodes - Google Patents
Circuit and server for interconnection and switching between single node and multiple nodes Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a circuit for interconnecting and switching a single node and multiple nodes, which comprises: a processing node; a plurality of requesting nodes; one end of the PCIE Switch chip is connected with the plurality of request nodes, and the other end of the PCIE Switch chip is connected with the processing node; and one end of the CPLD chip is connected with the plurality of request nodes, and the other end of the CPLD chip is connected with the PCIE Switch chip, wherein the CPLD chip is configured to receive request signals sent by the plurality of request nodes and send control instructions to the PCIE Switch chip based on the request signals, and the PCIE Switch chip is configured to select one request node to be interconnected with the processing node based on the control instructions. The invention also discloses a corresponding server.
Description
Technical Field
The invention relates to the technical field of data transmission, in particular to a circuit and a server for interconnection and switching of single nodes and multiple nodes.
Background
In a traditional interconnection system of a server GPU (graphics processing unit) and a CPU (central processing unit), GPUs are all connected in a single-to-single mode, and in a multi-channel CPU system, if a certain CPU is not connected with a GPU, data transmission needs to be carried out through interconnection signals among the CPUs, and data transmission cannot be directly carried out with the GPU.
In the existing scheme, the GPU is connected to the main CPU in a single point, and when the CPU not connected to the GPU needs to use the GPU processing unit in a multi-CPU system, the data to be processed needs to be transmitted to the main CPU connected to the GPU through the interconnection signal between the CPU and the CPU for data processing. Therefore, the data processing response is not timely, and simultaneously, the waste of CPU and GPU resources is caused.
Disclosure of Invention
In order to solve the above problems, an embodiment of the present invention provides a circuit and a server for interconnecting and switching a single node and multiple nodes, where the interconnection between a GPU and multiple CPUs is switched through a PCIE Switch, so as to implement automatic switching of corresponding CPU connections according to image processing requirements, save resources, and improve efficiency.
In view of the above, an aspect of the embodiments of the present invention provides a circuit for interconnecting and switching between a single node and multiple nodes, including: a processing node; a plurality of requesting nodes; one end of the PCIE Switch chip is connected with the plurality of request nodes, and the other end of the PCIE Switch chip is connected with the processing node; and one end of the CPLD chip is connected with the plurality of request nodes, and the other end of the CPLD chip is connected with the PCIE Switch chip, wherein the CPLD chip is configured to receive request signals sent by the plurality of request nodes and send control instructions to the PCIE Switch chip based on the request signals, and the PCIE Switch chip is configured to select one request node to be interconnected with the processing node based on the control instructions.
In some embodiments, the processing chip is further configured to: the processing node is a graphic processor, and the request node is a central processing unit.
In some embodiments, the CPLD chip is further configured to: in response to receiving request signals sent by a plurality of request nodes, judging the priority of the request signals, and sending a control instruction to the PCIE Switch chip based on the priority of the request signals.
In some embodiments, the PCIE Switch chip is further configured to: and returning a completion signal to the CPLD chip in response to the completion of the processing of the control instruction sent by the CPLD chip.
In some embodiments, the CPLD chip is further configured to: and sending an interconnection signal to the corresponding request node in response to receiving the completion signal returned by the CPLD chip.
In some embodiments, the requesting node is further configured to: and establishing connection with the processing node through PCI scanning in response to receiving the interconnection signal sent by the CPLD chip, and performing data transmission and related operations.
In another aspect of the embodiments of the present invention, a server is further provided, which includes a circuit for interconnecting and switching a single node and multiple nodes as follows: a processing node; a plurality of requesting nodes; one end of the PCIE Switch chip is connected with the plurality of request nodes, and the other end of the PCIE Switch chip is connected with the processing node; and one end of the CPLD chip is connected with the plurality of request nodes, and the other end of the CPLD chip is connected with the PCIE Switch chip, wherein the CPLD chip is configured to receive request signals sent by the plurality of request nodes and send control instructions to the PCIE Switch chip based on the request signals, and the PCIE Switch chip is configured to select one request node to be interconnected with the processing node based on the control instructions.
In some embodiments, the processing chip is further configured to: the processing node is a graphic processor, and the request node is a central processing unit.
In some embodiments, the CPLD chip is further configured to: in response to receiving request signals sent by a plurality of request nodes, judging the priority of the request signals, and sending a control instruction to the PCIE Switch chip based on the priority of the request signals.
In some embodiments, the PCIE Switch chip is further configured to: and returning a completion signal to the CPLD chip in response to the completion of the processing of the control instruction sent by the CPLD chip.
In some embodiments, the CPLD chip is further configured to: and sending an interconnection signal to the corresponding request node in response to receiving the completion signal returned by the CPLD chip.
In some embodiments, the requesting node is further configured to: and establishing connection with the processing node through PCI scanning in response to receiving the interconnection signal sent by the CPLD chip, and performing data transmission and related operations.
The invention has the following beneficial technical effects: through the PCIE Switch, the GPU is switched to be interconnected with the CPUs, the corresponding CPU connection is automatically switched according to the image processing requirement, the resources are saved, and the efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic diagram of an embodiment of a single-node to multi-node interconnection and switching circuit provided by the present invention;
fig. 2 is a schematic diagram of an embodiment of a server provided in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In view of the above objects, a first aspect of the embodiments of the present invention proposes an embodiment of a circuit for interconnecting and switching between a single node and a plurality of nodes. FIG. 1 is a schematic diagram illustrating an embodiment of a single-node to multi-node interconnect and switching circuit provided by the present invention. As shown in fig. 1, an embodiment of the present invention includes:
a processing node 100;
a number of requesting nodes 200, 201;
a PCIE Switch chip 300, where one end of the PCIE Switch chip 300 is connected to the plurality of request nodes 200 and 201, and the other end is connected to the processing node 100;
a CPLD chip 400, one end of the CPLD chip 400 is connected with a plurality of request nodes 200, 201, the other end is connected with a PCIE Switch chip 300,
the CPLD chip 400 is configured to receive request signals sent by a plurality of request nodes 200 and 201, and send a control instruction to the PCIE Switch chip 300 based on the request signals, and the PCIE Switch chip 300 is configured to select one request node 200 and 201 to interconnect with the processing node 100 based on the control instruction. Although two requesting nodes are illustrated, other numbers of requesting nodes are also within the scope of the present invention, as desired.
In this embodiment, request signals sent by a plurality of request nodes 200 and 201 are sent to the CPLD chip 400, the default idle state of the request signal is 1, when the request node 200 or 201 has an image processing requirement, the request signal is set to 0, and PCI scanning is performed to establish connection after receiving a signal for completing switching of the PCIE Switch chip 300, and then data transmission and related calculation work are performed; the PCIe Switch chip 300 is responsible for switching interconnection between the uplink CPUs and the GPUs, switching the GPUs to be connected with the relevant CPUs through the received control signals, and returning a completion signal after switching is completed; the CPLD chip 400 is a control unit that receives the request signal from the requesting node 200 or 201 to control the PCIe Switch chip 300 to Switch, and switches according to the request priority when a plurality of requesting nodes 200 and 201 have the request signal.
In this embodiment, the processing node is taken as a GPU unit, and the request nodes are taken as two CPU units, CPU0 and CPU 1. The GPU can be switched with the CPU0 through a PCIe Switch chip, the CPU1 is interconnected, the GPU is interconnected with the CPU0 by default, when the CPU1 sets the request signal 1 to be low level, the CPLD firstly judges whether the request signal 0 of the CPU0 is high level, and if the request signal 0 is high level, the PCIE Switch chip is switched with the GPU to be interconnected with the CPU 1; if the request signal 0 of the CPU0 is at low level, wait until the request signal 0 of the CPU0 goes high level and the CPU1 sends a request signal at low level, and connect the PCIE Switch chip switching GPU with the CPU 1. After the switching is completed, the PCIe Switch chip sends a switching completion signal to the corresponding CPU. The method comprises the following specific steps:
starting up and powering on, and switching the PCIE Switch chip to a GPU by default to be connected with the CPU 0; when the CPU1 has an image processing demand, pull request signal 1 low; the CPLD receives the request signal 1, and judges whether the request signal 0 is at a high level; if the request signal 0 is at a high level, the CPLD switches the PCIE Switch chip GPU to be interconnected with the CPU1, and then a completion signal is transmitted back; if the request signal 0 is at low level, the CPLD waits until the request signal 0 of the CPU0 becomes at high level, switches the PCIE Switch chip GPU to interconnect with the CPU1, and returns a completion signal after completion. After receiving the completion signal, the CPLD chip sends out a PCIE Switch chip switching completion signal 1; the CPU1 performs PCI scanning to establish connections, and then performs data transfer and related computational tasks.
In some embodiments of the invention, processing node 100 is a graphics processor and requesting nodes 200, 201 are central processors.
In this embodiment, the processing node 100 is a GPU unit, and the GPU is an image processor and is responsible for image and graphic related operations; the plurality of request nodes 200 and 201 are CPU units, the request signals sent by the CPU units are sent to the CPLD chip 400, the default idle state of the request signals is 1, when the CPU has an image processing requirement, the request signals are set to 0, and PCI scanning is performed to establish connection after receiving the signal of the PCIE Switch chip 300 switching completion, and then data transmission and related calculation work are performed; the PCIe Switch chip 300 is responsible for switching interconnection between the uplink CPUs and the GPUs, switching the GPUs to be connected with the relevant CPUs through the received control signals, and returning a completion signal after switching is completed; the CPLD chip 400 is a control unit that receives request signals from CPUs to control the PCIe Switch chip 300 to Switch, and switches according to the request priority when a plurality of CPUs have request signals from them.
In the embodiment, a single GPU card can be automatically switched to be connected with a corresponding CPU according to the image processing requirement of the CPU; and GPU hardware resource sharing and quick response are realized.
In some embodiments of the present invention, the CPLD chip 400 is further configured to: in response to receiving request signals sent by several request nodes 200, 201, the priority of the request signals is determined, and a control command is sent to the PCIE Switch chip 300 based on the priority of the request signals.
In this embodiment, when a plurality of request nodes 200 and 201 have request signals sent, a control command is sent to the PCIE Switch chip 300 according to the request priority for switching.
In some embodiments of the present invention, the PCIE Switch chip 300 is further configured to: in response to the completion of the processing of the control instruction sent to the CPLD chip 400, a completion signal is returned to the CPLD chip 400.
In some embodiments of the present invention, the CPLD chip 400 is further configured to: and in response to receiving the completion signal returned by the CPLD chip 400, sending an interconnection signal to the corresponding request node 200, 201.
In some embodiments of the invention, the requesting node 200, 201 is configured to: in response to receiving the interconnection signal sent by the CPLD chip 400, a connection is established with the processing node 100 through PCI scanning, and data transmission and related operations are performed.
In view of the above object, according to a second aspect of the embodiments of the present invention, a server is provided. Fig. 2 is a schematic diagram of an embodiment of a server provided by the present invention. As shown in fig. 2, the server 011 includes a single-node and multi-node interconnecting and switching circuit 012 including: a processing node; a plurality of requesting nodes; one end of the PCIE Switch chip is connected with a plurality of request nodes, and the other end of the PCIE Switch chip is connected with the processing node; one end of the CPLD chip is connected with the plurality of request nodes, the other end of the CPLD chip is connected with the PCIE Switch chip, the CPLD chip is configured and used for receiving request signals sent by the plurality of request nodes and sending control instructions to the PCIE Switch chip based on the request signals, and the PCIE Switch chip is configured and used for selecting one request node to be interconnected with the processing nodes based on the control instructions.
In some embodiments of the invention, the processing node is a graphics processor and the requesting node is a central processor.
In some embodiments of the invention, the CPLD chip is further configured to: in response to receiving request signals sent by a plurality of request nodes, the priority of the request signals is judged, and a control instruction is sent to the PCIE Switch chip based on the priority of the request signals.
In some embodiments of the present invention, the PCIE Switch chip is further configured to: and returning a completion signal to the CPLD chip in response to the completion of the processing of the control instruction sent to the CPLD chip.
In some embodiments of the invention, the CPLD chip is further configured to: and sending an interconnection signal to the corresponding request node in response to receiving a completion signal returned by the CPLD chip.
In some embodiments of the invention, the requesting node is configured to: and in response to receiving the interconnection signal sent by the CPLD chip, establishing connection with the processing node through PCI scanning, and performing data transmission and related operations.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A circuit for single-node to multi-node interconnection and switching, comprising:
a processing node;
a plurality of requesting nodes;
one end of the PCIE Switch chip is connected with the plurality of request nodes, and the other end of the PCIE Switch chip is connected with the processing node;
one end of the CPLD chip is connected with the plurality of request nodes, the other end of the CPLD chip is connected with the PCIE Switch chip,
the CPLD chip is configured to receive request signals sent by the plurality of request nodes, and send a control instruction to the PCIE Switch chip based on the request signals, and the PCIE Switch chip is configured to select one request node to interconnect with the processing node based on the control instruction.
2. The single-node to multi-node interconnect and switchover circuit of claim 1 wherein said processing node is a graphics processor and said requesting node is a central processing unit.
3. The single-node to multi-node interconnect and switching circuit of claim 1, wherein the CPLD chip is further configured to:
in response to receiving request signals sent by a plurality of request nodes, judging the priority of the request signals, and sending a control instruction to the PCIE Switch chip based on the priority of the request signals.
4. The single-node to multi-node interconnect and switching circuit of claim 1, wherein the PCIE Switch chip is further configured to:
and returning a completion signal to the CPLD chip in response to the completion of the processing of the control instruction sent by the CPLD chip.
5. The single-node to multi-node interconnect and switching circuit of claim 4, wherein the CPLD chip is further configured to:
and sending an interconnection signal to the corresponding request node in response to receiving the completion signal returned by the CPLD chip.
6. The single-node to multi-node interconnect and switchover circuit of claim 5 wherein said requesting node is configured to:
and establishing connection with the processing node through PCI scanning in response to receiving the interconnection signal sent by the CPLD chip, and performing data transmission and related operations.
7. A server comprising circuitry for single-node to multi-node interconnection and switching, said circuitry comprising:
a processing node;
a plurality of requesting nodes;
the PCIE Switch chip is used for respectively interconnecting the plurality of request nodes and the processing nodes through the PCIE Switch chip;
one end of the CPLD chip is connected with the plurality of request nodes, the other end of the CPLD chip is connected with the PCIE Switch chip,
the CPLD chip is configured to receive request signals sent by the plurality of request nodes, and send a control instruction to the PCIE Switch chip based on the request signals, and the PCIE Switch chip is configured to select one request node to interconnect with the processing node based on the control instruction.
8. The server according to claim 7, wherein the processing node is a graphics processor and the requesting node is a central processor.
9. The server of claim 7, wherein the CPLD chip is further configured to:
in response to receiving request signals sent by a plurality of request nodes, judging the priority of the request signals, and sending a control instruction to the PCIE Switch chip based on the priority of the request signals.
10. The server of claim 7, wherein the PCIE Switch chip is further configured to: responding to the completion of the processing of the control instruction sent by the CPLD chip, and returning a completion signal to the CPLD chip;
the CPLD chip is further configured to: sending an interconnection signal to the corresponding request node in response to receiving the completion signal returned by the CPLD chip;
the requesting node is configured to: and establishing connection with the processing node through PCI scanning in response to receiving the interconnection signal sent by the CPLD chip, and performing data transmission and related operations.
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| CN202111153094.2A CN113900984B (en) | 2021-09-29 | 2021-09-29 | Circuit and server for interconnection and switching of single node and multiple nodes |
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| CN202111153094.2A CN113900984B (en) | 2021-09-29 | 2021-09-29 | Circuit and server for interconnection and switching of single node and multiple nodes |
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| US20160196194A1 (en) * | 2014-12-17 | 2016-07-07 | Quanta Computer Inc. | Automatic hardware recovery system |
| CN112612741A (en) * | 2020-12-28 | 2021-04-06 | 苏州浪潮智能科技有限公司 | Multi-path server |
| CN112667556A (en) * | 2020-12-23 | 2021-04-16 | 曙光信息产业(北京)有限公司 | GPU server and image processing system |
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2021
- 2021-09-29 CN CN202111153094.2A patent/CN113900984B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20160196194A1 (en) * | 2014-12-17 | 2016-07-07 | Quanta Computer Inc. | Automatic hardware recovery system |
| CN205050131U (en) * | 2015-08-31 | 2016-02-24 | 浪潮电子信息产业股份有限公司 | Support multiple system to handle circuit of start -up and high redundancy wantonly |
| CN112667556A (en) * | 2020-12-23 | 2021-04-16 | 曙光信息产业(北京)有限公司 | GPU server and image processing system |
| CN112612741A (en) * | 2020-12-28 | 2021-04-06 | 苏州浪潮智能科技有限公司 | Multi-path server |
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