CN113900469B - Current-limiting protection circuit - Google Patents
Current-limiting protection circuit Download PDFInfo
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- CN113900469B CN113900469B CN202111184539.3A CN202111184539A CN113900469B CN 113900469 B CN113900469 B CN 113900469B CN 202111184539 A CN202111184539 A CN 202111184539A CN 113900469 B CN113900469 B CN 113900469B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
Abstract
The invention provides a current limiting protection circuit, which relates to the technical field of microelectronic integrated circuits and aims at solving the problem that the current limiting value of the traditional current limiting protection circuit is influenced by technology, temperature and encapsulation.
Description
Technical Field
The invention relates to the technical field of microelectronic integrated circuits, in particular to a current-limiting protection circuit.
Background
In the fan driving chip and the motor driving chip, an output structure of an H-bridge is often adopted to drive an inductive load. Due to the characteristics of inductive load, when various anomalies occur in the chip, including locked rotor, over-temperature protection, abrupt shut-off of the chip or abrupt start of the chip, large current is generated in the output tube of the H bridge formed in the chip. In worse cases, two tubes of one of the legs are simultaneously connected due to the deviation of the driving sequence. This creates a short circuit path between VCC and GND, which produces a very large current on both tubes of this leg. If the maximum current flowing through the output pipe is not limited to a certain extent, the output driving pipe is easy to burn.
In the conventional current limiting protection circuit, a very small sampling resistor is usually connected between the source of the output pipe and the ground. The current through the output tube will flow entirely through this small resistance. When a large current appears on the output tube, a larger voltage value is generated on the sampling resistor. When the voltage value reaches the set voltage value, a control signal is generated to limit the current on the output tube to be further increased or directly close the output tube. Thereby achieving the purpose of protecting the output pipe. However, the introduction of the resistor increases the on-resistance of the H-bridge output tube, which affects the use of the protection structure under the condition of large driving current.
In addition, in some other current limiting protection circuits, when the temperature of the working environment of the chip changes, or the manufacturing process of the chip deviates, or the chip package changes, the protection current of the output tube also often changes. In order to cope with these deviations, it is often necessary to sacrifice the current driving capability of the output tube and set the current limit protection value within a relatively conservative range, and therefore, a current limit protection circuit is needed to solve the above-mentioned problems.
Disclosure of Invention
In view of the problems existing in the prior art, the invention discloses a current-limiting protection circuit, which adopts the technical scheme that the current-limiting protection circuit comprises an H-bridge circuit, wherein the H-bridge circuit further comprises an upper tube driving circuit, a lower tube driving circuit, a PMOS tube MP21, a PMOS tube MP22, an NMOS tube MN25 and an NMOS tube MN26, and the upper tube driving circuit, the lower tube driving circuit, the PMOS tube MP21, the PMOS tube MP22, the NMOS tube MN25 and the NMOS tube MN26 are electrically connected; the detection circuit comprises an NMOS tube MN27 and an NMOS tube MN28, wherein the drain end of the NMOS tube MN27 is connected with the output VOUTP of the H-bridge circuit, the gate end of the NMOS tube MN27 is connected with the gate end of the NMOS tube MN25, the drain end of the NMOS tube MN28 is connected with the output VOUTN of the H-bridge circuit, and the gate end of the NMOS tube MN28 is connected with the gate end of the NMOS tube MN 26; the current limiting setting circuit comprises an NMOS tube MN21 and an NMOS tube MN22, wherein the gate end of the NMOS tube MN21 is connected with the gate end of an NMOS tube MN25, the gate end of the NMOS tube MN22 is connected with the gate end of an NMOS tube MN26, and the drain ends of the NMOS tube MN21 and the NMOS tube MN22 are connected with the drain end of a PMOS tube MP 23; the variable gain amplifier comprises a PMOS tube MP24, a PMOS tube MP25, a PMOS tube MP26, an NMOS tube MN29, an NMOS tube MN30 and an NMOS tube MN31, wherein the source end of the PMOS tube MP24 is connected with the VDD end, the gate end of the PMOS tube MP24 is connected with the gate end of the PMOS tube MP23, the drain end of the PMOS tube MP24 is connected with the source ends of the PMOS tube MP25 and the PMOS tube MP26, the gate end of the PMOS tube MP26 is connected with the source ends of the NMOS tube MN27 and the NMOS tube MN28, the gate end of the PMOS tube MP25 is connected with the source ends of the NMOS tube MN21 and the NMOS tube MN22, the drain end of the PMOS tube MP26 is connected with the drain end of the NMOS tube MN29, the drain end of the PMOS tube MP26 is connected with the gate end of the NMOS tube MP 29, the drain end of the NMOS tube MP25 is connected with the drain end of the NMOS tube MP 30 and the NMOS tube 31, the drain end of the MN25 is connected with the drain end of the NMOS tube 31, the drain end of the NMOS tube 31 is connected with the drain end of the NMOS tube 30, the drain end of the NMOS tube 31 and the NMOS tube 31, the drain end of the NMOS tube 30 is connected with the drain end of the NMOS tube 31; the NMOS tube MN21 is connected with the source end of the NMOS tube MN22 and the GND end, the source end of the PMOS tube MP23 is connected with the VDD end, the gate ends of the PMOS tube MP23 and the PMOS tube MP24 are connected with the gate end of the PMOS tube MP27, the source end of the PMOS tube MP27 is connected with the VDD end, and the drain end of the PMOS tube MP27 is connected with the constant value resistor R1 and the in-phase input end of the operational amplifier circuit.
The detection circuit, the current limiting setting circuit and the variable gain amplifying circuit are matched, so that the problem that a traditional current limiting protection circuit has a certain influence on a protected circuit is solved, and the influence of a current limiting value on the protected circuit along with a process, temperature and encapsulation in the traditional protection circuit is also solved.
As a preferable technical scheme of the invention, the voltage on the VOUTP is V VOUTP ＝
I MN5 *R MN5 The R is MN5 Is the on-resistance of the NMOS transistor MN25, I MN5 For the current flowing through the NMOS transistor MN25, the net1 controls the NMOS transistor MN27 in the detection circuit to driveOpening to enable the voltage on the VOUTP to be input to the positive input end of the variable gain amplifier; net2 controls the NMOS transistor MN28 in the detection circuit to turn off so that the voltage on VOUTN cannot be input to the positive input of the amplifier.
As a preferable technical scheme of the invention, the channel width-to-length ratio of the NMOS transistor MN21 and the NMOS transistor MN22 to the NMOS transistor MN25 and the NMOS transistor MN26 is as follows
Said->The channel width-to-length ratio of the NMOS transistor MN25 and the NMOS transistor MN26 is that the NMOS transistor MN25 and the NMOS transistor MN26 are low-side power driving transistors of an H bridge; said->The channel width-to-length ratio of the NMOS tube MN21 and the NMOS tube MN22 is that the NMOS tube MN21 and the NMOS tube MN22 are sampling tubes for flowing H-bridge current; and n is the size ratio of the H-bridge low-side power tube to the sampling tube.
As a preferable technical scheme of the invention, the current on the PMOS tube MP27 is The R1 is the obtained current I REF The required constant resistance; the V is BG Is a band-gap reference voltage which is not influenced by the change of the power supply voltage and the change of the temperature, and the currents flowing on the PMOS tube MP23 and the PMOS tube MP24 are K1 respectively REF And K2 is I REF Wherein K1 is the channel width-to-length ratio of the PMOS tube MP23 and the PMOS tube MP27, K2 is the channel width-to-length ratio of the PMOS tube MP24 and the PMOS tube MP27,V BG is a bandgap reference voltage that is not affected by supply voltage variations and temperature variations, so R 1 Temperature characteristics of (2) determine I REF And brings great convenience to circuit designers.
As a preferable embodiment of the present invention, the gain of the variable gain amplifier is gm MP25 ，gm MN31 The transconductance of the PMOS transistor MP25 and the NMOS transistor MN31 respectively.
The invention has the beneficial effects that: the invention solves the problem that the traditional current-limiting protection circuit has a certain influence on the protected circuit by adopting the detection circuit, the current-limiting setting circuit and the variable gain amplifying circuit, and also solves the problem that the current-limiting protection value can be influenced on the protected circuit along with the process, the temperature and the encapsulation in the traditional protection circuit, and can be set in a relatively conservative range without sacrificing the current driving capability of an output pipe.
Drawings
FIG. 1 is a schematic diagram of an H-bridge driven inductive load;
FIG. 2 is a schematic diagram of a switching sequence of the upper tube driving circuit;
FIG. 3 is a schematic diagram of a switching sequence of the down tube driving circuit;
FIG. 4 is a schematic diagram of a conventional current limiting protection circuit;
FIG. 5 is a schematic diagram of the present invention;
fig. 6 is a schematic diagram of a current generation circuit.
Detailed Description
Example 1
As shown in fig. 1 to 6, the invention discloses a current limiting protection circuit, which adopts the technical scheme that the current limiting protection circuit comprises an H-bridge circuit, wherein the H-bridge circuit further comprises an upper tube driving circuit, a lower tube driving circuit, a PMOS tube MP21, a PMOS tube MP22, an NMOS tube MN25 and an NMOS tube MN26, and the upper tube driving circuit, the lower tube driving circuit, the PMOS tube MP21, the PMOS tube MP22, the NMOS tube MN25 and the NMOS tube MN26 are electrically connected; the detection circuit comprises an NMOS tube MN27 and an NMOS tube MN28, wherein the drain end of the NMOS tube MN27 is connected with the output VOUTP of the H-bridge circuit, the gate end of the NMOS tube MN27 is connected with the gate end of the NMOS tube MN26, the drain end of the NMOS tube MN28 is connected with the output VOUTP of the H-bridge circuit, and the gate end of the NMOS tube MN28 is connected with the gate end of the NMOS tube MN 25; the current limiting setting circuit comprises an NMOS tube MN21 and an NMOS tube MN22, wherein the gate end of the NMOS tube MN21 is connected with the gate end of an NMOS tube MN25, the gate end of the NMOS tube MN22 is connected with the gate end of an NMOS tube MN26, and the drain ends of the NMOS tube MN21 and the NMOS tube MN22 are connected with the drain end of a PMOS tube MP 23; the variable gain amplifier comprises a PMOS tube MP24, a PMOS tube MP25, a PMOS tube MP26, an NMOS tube MN29, an NMOS tube MN30 and an NMOS tube MN31, wherein the source end of the PMOS tube MP24 is connected with the VDD end, the gate end of the PMOS tube MP24 is connected with the gate end of the PMOS tube MP23, the drain end of the PMOS tube MP24 is connected with the source ends of the PMOS tube MP25 and the PMOS tube MP26, the gate end of the PMOS tube MP26 is connected with the source ends of the NMOS tube MN27 and the NMOS tube MN28, the gate end of the PMOS tube MP25 is connected with the source ends of the NMOS tube MN21 and the NMOS tube MN22, the drain end of the PMOS tube MP26 is connected with the drain end of the NMOS tube MN29, the drain end of the PMOS tube MP26 is connected with the gate end of the NMOS tube MP 29, the drain end of the NMOS tube MP25 is connected with the NMOS tube MP 30 and the NMOS tube MP 31, the drain end of the MN25 is connected with the drain end of the NMOS tube 31, and the drain end of the NMOS tube 31 is connected with the drain end of the NMOS tube 30, and the drain end of the NMOS tube 31 is connected with the drain end of the NMOS tube 31.
As a preferred technical scheme of the invention, the source ends of the NMOS tube MN21 and the NMOS tube MN22 are connected with the GND end, the source end of the PMOS tube MP23 is connected with the VDD end, and the gate ends of the PMOS tube MP23 and the PMOS tube MP24 are connected with the PMOS tube MP 27.
As a preferable technical scheme of the invention, the voltage on the VOUTN is V VOUTP ＝
I MN5 *R MN5 The R is MN5 For the on-resistance of the NMOS transistor MN25, the lower transistor driving circuit generates a sequence of switching high and low, and drives the output transistor NMOS transistor MN25 or the NMOS transistor MN26 to be alternately turned on and off, and when the output net1 of the lower transistor driving circuit is at a high level, the MN25 is controlled to turn on the flowing current; when net2 outputs low level, the control NMOS transistor MN26 is turned off, and the voltage VOUTN is equal to the power supply voltage VCC.
As a preferable technical scheme of the invention, the channel width-to-length ratio of the NMOS tube MN21, the NMOS tube MN22, the NMOS tube MN25 and the NMOS tube MN26 is as follows
As a preferable technical scheme of the invention, the current on the PMOS tube MP27 is Under the control of the output high-low sequence of the lower tube driving circuit, when the NMOS tube MN21 is turned on, the NMOS tube MN22 is turned off, and the current on the PMOS tube MP23 completely flows through the NMOS tube MN21 to generate a turn-on voltage, K1I REF R MN21 When the NMOS tube MN22 is turned on, the NMOS tube MN21 is turned off, and the current on the PMOS tube MP23 flows through the NMOS tube MN22 to generate a turn-on voltage K1I REF R MN22 The channel width-to-length ratio of the NMOS transistor MN21 and the NMOS transistor MN22 is the same, so that the generated turn-on voltage is the same.
As a preferable embodiment of the present invention, the gain of the variable gain amplifier is gm MP25 ，gm MN31 The transconductance of the PMOS transistor MP25 and the NMOS transistor MN31 respectively.
Under the control of the output high-low sequence of the lower tube driving circuit, when the H-bridge output tube NMOS tube MN25 is conducted, the output voltage VOUTP is connected to the gate terminal of the input tube PMOS tube MP26 of the amplifier through the opened NMOS tube MN 27. When the H-bridge output pipe NMOS pipe MN26 is conducted, the output voltage VOUTN is connected to the gate terminal of the input pipe PMOS pipe MP26 of the amplifier through the opened NMOS pipe MN 28.
When the NMOS transistor MN21 and the NMOS transistor MN25 are turned on due to the high-low time sequence output by the lower transistor driving circuit, the NMOS transistor MN22 and the NMOS transistor MN26 are turned off at the moment. At this time, the turn-on voltages of the NMOS transistor MN21 and the NMOS transistor MN25 are respectively used as the gate voltages of the input transistors PMOS transistor MP25 and PMOS transistor MP26 of the amplifier. The current flowing through the NMOS tube MN21 is the current determined by the PMOS tube MP23, and the magnitude is K1 x I REF . When the current flowing through the output NMOS transistor MN25 reaches n 1I REF In this case, the on voltages of the NMOS transistor MN21 and the NMOS transistor MN25 are equal. Where n is the channel width to length ratio of NMOS transistor MN25 and NMOS transistor MN 21. When the NMOS transistor MN22 and the NMOS transistor MN26 are opened due to the high-low time sequence output by the lower transistor driving circuit, then the N21MOS transistor and the NMOS transistor MN25 are closed at the moment. At this time, the turn-on voltages of the NMOS transistor MN22 and the NMOS transistor MN26 are respectively used as the gate voltages of the input transistors PMOS transistor MP25 and PMOS transistor MP26 of the amplifier. The current flowing through the NMOS tube MN22 is the current determined by the PMOS tube MP23, and the magnitude is K1 REF . When the current flowing through the output NMOS transistor MN26 reaches n 1I REF In this case, the on voltages of the NMOS transistor MN22 and the NMOS transistor MN26 are equal. Where n is the channel width to length ratio of NMOS transistor MN26 and NMOS transistor MN 22.
When the current flowing through the NMOS transistor MN25 or MN26 is smaller than n×K1×I REF When the voltage of the gate terminal of the PMOS transistor MP26 is smaller than that of the PMOS transistor MP 25. The variable gain amplifier composed of the PMOS tube MP24, the PMOS tube MP25, the PMOS tube MP26, the NMOS tube MN29, the NMOS tube MN30 and the NMOS tube MN31 works in a high gain mode,the gate voltage of the NMOS transistor MN31 is low, so that the NMOS transistors MN23 and MN24 are in the off state.
When the current flowing through the NMOS transistor MN25 or MN26 of the H-bridge output tube is greater than or equal to n×K1×I REF When the variable gain amplifier works in the low gain mode, the channel width-to-length ratio of the PMOS tube MP25 and the NMOS tube MN31 is adjusted, and the gain of the amplifier can be accurately set. At this time, the gate voltage of the NMOS transistor MN31 is greater than the threshold voltage thereof, and the NMOS transistor MN31 is turned on, so that the NMOS transistors MN23 and MN24 are also turned on. At this time, the NMOS transistor MN23 and the NMOS transistor MN24 generate feedback signals, so as to change the gate voltages of the output tube PMOS transistor MP21 and the PMOS transistor MP22 of the H-bridge, thereby improving the on-resistance thereof and reducing the current flowing through the H-bridge.
The circuit connection related by the invention is a conventional means adopted by the person skilled in the art, can be obtained through limited tests, and belongs to common general knowledge.
The components not described in detail herein are prior art.
Although the specific embodiments of the present invention have been described in detail, the present invention is not limited to the above embodiments, and various changes and modifications without inventive labor may be made within the scope of the present invention without departing from the spirit of the present invention, which is within the scope of the present invention.
Claims (5)
1. The current-limiting protection circuit comprises an H-bridge circuit, wherein the H-bridge circuit further comprises an upper tube driving circuit, a lower tube driving circuit, a PMOS tube MP21, a PMOS tube MP22, an NMOS tube MN25 and an NMOS tube MN26, and the upper tube driving circuit, the lower tube driving circuit, the PMOS tube MP21, the PMOS tube MP22, the NMOS tube MN25 and the NMOS tube MN26 are electrically connected; the method is characterized in that: the detection circuit comprises an NMOS tube MN27 and an NMOS tube MN28, wherein the drain end of the NMOS tube MN27 is connected with the output VOUTP of the H-bridge circuit, the gate end of the NMOS tube MN27 is connected with the gate end of the NMOS tube MN25, the drain end of the NMOS tube MN28 is connected with the output VOUTN of the H-bridge circuit, and the gate end of the NMOS tube MN28 is connected with the gate end of the NMOS tube MN 26; the current limiting setting circuit comprises an NMOS tube MN21 and an NMOS tube MN22, wherein the gate end of the NMOS tube MN21 is connected with the gate end of an NMOS tube MN25, the gate end of the NMOS tube MN22 is connected with the gate end of an NMOS tube MN26, and the drain ends of the NMOS tube MN21 and the NMOS tube MN22 are connected with the drain end of a PMOS tube MP 23; the variable gain amplifier comprises a PMOS tube MP24, a PMOS tube MP25, a PMOS tube MP26, an NMOS tube MN29, an NMOS tube MN30 and an NMOS tube MN31, wherein the source end of the PMOS tube MP24 is connected with the VDD end, the gate end of the PMOS tube MP24 is connected with the gate end of the PMOS tube MP23, the drain end of the PMOS tube MP24 is connected with the source ends of the PMOS tube MP25 and the PMOS tube MP26, the gate end of the PMOS tube MP26 is connected with the source ends of the NMOS tube MN27 and the NMOS tube MN28, the gate end of the PMOS tube MP25 is connected with the source ends of the NMOS tube MN21 and the NMOS tube MN22, the drain end of the PMOS tube MP26 is connected with the drain end of the NMOS tube MN29, the drain end of the PMOS tube MP26 is connected with the gate end of the NMOS tube MP 29, the drain end of the NMOS tube MP25 is connected with the drain end of the NMOS tube MP 30 and the NMOS tube 31, the drain end of the MN25 is connected with the drain end of the NMOS tube 31, the drain end of the NMOS tube 31 is connected with the drain end of the NMOS tube 30, the drain end of the NMOS tube 31 and the NMOS tube 31, the drain end of the NMOS tube 30 is connected with the drain end of the NMOS tube 31; the NMOS tube MN21 is connected with the source end of the NMOS tube MN22 and the GND end, the source end of the PMOS tube MP23 is connected with the VDD end, the gate ends of the PMOS tube MP23 and the PMOS tube MP24 are connected with the gate end of the PMOS tube MP27, the source end of the PMOS tube MP27 is connected with the VDD end, and the drain end of the PMOS tube MP27 is connected with the constant value resistor R1 and the in-phase input end of the operational amplifier circuit.
2. A current limiting protection circuit according to claim 1, wherein: the voltage on VOUTP is V VOUTP ＝I MN5 *R MN5 The R is MN5 Is the on-resistance of the NMOS transistor MN25, I MN5 Is the current flowing through the NMOS transistor MN 25.
3. A current limiting protection circuit according to claim 1, wherein: the channel width-to-length ratio of the NMOS transistors MN21 and MN22 to the NMOS transistors MN25 and MN26 isSaid->The channel width-to-length ratio of the NMOS transistor MN25 and the NMOS transistor MN26 is that the NMOS transistor MN25 and the NMOS transistor MN26 are low-side power driving transistors of an H bridge; said->The channel width-to-length ratio of the NMOS tube MN21 and the NMOS tube MN22 is that the NMOS tube MN21 and the NMOS tube MN22 are sampling tubes for flowing H-bridge current; and n is the size ratio of the H-bridge low-side power tube to the sampling tube.
4. A current limiting protection circuit according to claim 1, wherein: the current on the PMOS tube MP27 isThe R1 is the obtained current I REF The required constant resistance; the V is BG Is a bandgap reference voltage that is not affected by supply voltage variations and temperature variations.
5. A current limiting protection circuit according to claim 1, wherein: the gain of the variable gain amplifier isgm MP25 ，gm MN31 The transconductance of the PMOS transistor MP25 and the NMOS transistor MN31 respectively.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111184539.3A CN113900469B (en) | 2021-10-12 | 2021-10-12 | Current-limiting protection circuit |
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| CN202111184539.3A CN113900469B (en) | 2021-10-12 | 2021-10-12 | Current-limiting protection circuit |
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| CN113900469B true CN113900469B (en) | 2023-09-19 |
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| CN113900469A (en) | 2022-01-07 |
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