CN113889043B - Display driving circuit and display panel - Google Patents
Display driving circuit and display panel Download PDFInfo
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- CN113889043B CN113889043B CN202111168674.9A CN202111168674A CN113889043B CN 113889043 B CN113889043 B CN 113889043B CN 202111168674 A CN202111168674 A CN 202111168674A CN 113889043 B CN113889043 B CN 113889043B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2074—Display of intermediate tones using sub-pixels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3275—Details of drivers for data electrodes
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- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The application relates to a display drive circuit and a display panel, the display drive circuit includes: the first channel amplifier comprises a first gain stage, a first switch unit and a first output stage which are electrically connected in sequence; the second channel amplifier comprises a second gain stage, a second switch unit and a second output stage which are electrically connected in sequence, wherein the output end of the first gain stage is also electrically connected with the input end of the second output stage through a third switch unit, and the input end of the first output stage is also electrically connected with the output end of the second gain stage through a fourth switch unit; when the first output stage and the second output stage have output, the first switch unit, the second switch unit, the fifth switch unit and the seventh switch unit are all in a first switch state, the third switch unit, the fourth switch unit, the seventh switch unit and the eighth switch unit are all in a second switch state, and the first switch state and the second switch state are opposite. The above display drive circuit reduces the output delay characteristics of the respective channel amplifiers.
Description
Technical Field
The application relates to the technical field of display, in particular to a display driving circuit and a display panel.
Background
In general, a display driver IC of a display panel has an independent R/G/B gamma structure, and a sub-pixel rendering method is generally used to further realize high definition.
The method for rendering the sub-pixels comprises pixel rendering technologies such as delta RGB, RGBG, RBGB and the like, and a display panel rendered by the sub-pixels has pixel patterns with various structures, so that when the display panel with the pixels with various structures is driven by the method for rendering the sub-pixels, a plurality of output switches are generally required to be arranged to switch the output of each driving channel, and in order to reduce the on-resistance of each driving channel, the area of the arranged output switches is generally larger, however, the area of the whole driving IC is increased by the arranged output switches, so that the output delay characteristic of each channel amplifier in the driving IC is obviously increased.
Disclosure of Invention
In view of this, the present application provides a display driving circuit and a display panel to solve the technical problem that the output delay characteristics of each channel amplifier in a driving IC are significantly increased due to the increased area of the output switch in the driving IC during the driving of the display panel.
A display driving circuit is applied to a display panel, the display panel comprises a plurality of pixel units, each pixel unit comprises a first color pixel sub-unit and a second color pixel sub-unit, and the display driving circuit comprises:
the first channel amplifier comprises a first gain stage, a first switch unit and a first output stage which are electrically connected in sequence;
the second channel amplifier comprises a second gain stage, a second switch unit and a second output stage which are electrically connected in sequence;
the output end of the first gain stage is electrically connected with the input end of the second output stage through the third switching unit;
the input end of the first output stage is also electrically connected with the output end of the second gain stage through the fourth switching unit;
the first input end of the first gain stage is used for inputting a first pixel digital level signal to drive the first color pixel subunit;
the display drive circuit further includes:
the second input end of the first gain stage is electrically connected with the output end of the first output stage through the fifth switch unit;
the second input end of the first gain stage is electrically connected with the output end of the second output stage through the sixth switch unit, and the first input end of the second gain stage is used for inputting a second pixel digital level signal so as to drive the second color pixel subunit;
the second input end of the second gain stage is electrically connected with the output end of the second output stage through the seventh switch unit;
the second input end of the second gain stage is also electrically connected with the output end of the first output stage through the eighth switch unit;
when the first output stage and the second output stage have outputs, the first switch unit, the second switch unit, the fifth switch unit and the seventh switch unit are all in a first switch state, the third switch unit, the fourth switch unit, the sixth switch unit and the eighth switch unit are all in a second switch state, and the first switch state and the second switch state are opposite.
In one embodiment, the display driving circuit further includes a switch control unit, wherein a first control signal output end of the switch control unit is electrically connected to respective control ends of the first switch unit, the second switch unit, the fifth switch unit and the seventh switch unit to output a first control signal;
the second control signal output end of the switch control unit is electrically connected with the respective control ends of the third switch unit, the fourth switch unit, the sixth switch unit and the eighth switch unit respectively so as to output a second control signal.
In one embodiment, each pixel cell further comprises a third color pixel sub-cell, the display driver circuit further comprising:
the third channel amplifier comprises a third gain stage, a ninth switching unit and a third output stage which are electrically connected in sequence, wherein the first input end of the third gain stage is used for inputting a third pixel digital level signal so as to drive a third color pixel subunit, and the second input end of the third gain stage is also electrically connected with the output end of the third output stage;
the third control signal output end of the switch control unit is electrically connected with the ninth switch unit and used for outputting a third control signal.
In one embodiment, the display driving circuit further comprises:
the fourth channel amplifier comprises a fourth gain stage, a tenth switching unit and a fourth output stage which are electrically connected in sequence, wherein the first input end of the fourth gain stage is used for inputting a third pixel digital level signal to drive the third color pixel subunit, and the second input end of the fourth gain stage is also electrically connected with the output end of the fourth output stage;
the third control signal output end is further electrically connected with the control end of the tenth switching unit and is used for outputting a third control signal.
In one embodiment, the switch control unit adopts a clock control unit, and the first control signal, the second control signal and the third control signal are all periodic control signals, and the respective signal periods are the same.
In one embodiment, the first control signal and the second control signal have respective opposite level states.
In one embodiment, each switching unit adopts a MOS switching tube or a triode.
In one embodiment, the display driving circuit further includes a signal processor, and a first signal generating unit, a second signal generating unit, and a third signal generating unit electrically connected to the signal processor, respectively, the first signal generating unit further electrically connected to the first input terminal of the first gain stage, the second signal generating unit electrically connected to the first input terminal of the second gain stage, and the third signal generating unit electrically connected to the first input terminal of the third gain stage;
the signal processor is used for converting the input initial signal data into three paths of monochromatic signal data and outputting the three paths of monochromatic signal data respectively, wherein the three paths of monochromatic signal data comprise first monochromatic signal data, second monochromatic signal data and third monochromatic signal data;
the first signal generating unit is used for receiving the first monochromatic signal data and carrying out conversion processing on the first monochromatic signal data so as to generate a first pixel digital level signal and output the first pixel digital level signal to a first input end of the first gain stage;
the second signal generation unit is used for receiving second monochromatic signal data and carrying out conversion processing on the second monochromatic signal data so as to generate a second pixel digital level signal and output the second pixel digital level signal to a first input end of the second gain stage;
the third signal generating unit is used for receiving third monochromatic signal data and carrying out conversion processing on the third monochromatic signal data so as to generate a third pixel digital level signal and output the third pixel digital level signal to the first input end of the third gain stage.
In one embodiment, the first signal generating unit includes a first shift register, a first latch, and a first decoder electrically connected to each other, and an output terminal of the first decoder is electrically connected to a first input terminal of the first gain stage;
the second signal generating unit comprises a second shift register, a second latch and a second decoder which are electrically connected, and the output end of the second decoder is electrically connected with the first input end of the second gain stage;
the third signal generating unit comprises a third shift register, a third latch and a third decoder which are electrically connected, and the output end of the third decoder is electrically connected with the first input end of the third gain stage.
A display panel adopts the display driving circuit.
The display driving circuit comprises a first channel amplifier and a second channel amplifier, wherein the first channel amplifier comprises a first gain stage, a first switch unit and a first output stage which are electrically connected in sequence, the second channel amplifier comprises a second gain stage, a second switch unit and a second output stage which are electrically connected in sequence, the output end of the first gain stage is electrically connected with the input end of the second output stage through a third switch unit, the input end of the first output stage is electrically connected with the output end of the second gain stage through a fourth switch unit, when the first output stage and the second output stage output, the first switch unit, the second switch unit, the fifth switch unit and the seventh switch unit are in a first switch state, and the third switch unit, the fourth switch unit, the sixth switch unit and the eighth switch unit are in a second switch state, wherein the first switch state is opposite to the second switch state. When the first switch state is a closed state, the first gain stage, the first switch unit and the first output stage form a path, the fifth switch unit is closed to form a feedback loop, at the moment, the first output stage outputs a voltage driving signal for driving the first color pixel subunit, the second gain stage, the second switch unit and the second output stage form another path, the seventh switch unit is closed to form a corresponding feedback loop, at the moment, the second output stage outputs a voltage driving signal for driving the second color pixel subunit; when the first switch state is an open state, the second switch state is a closed state, the first gain stage, the third switch unit and the second output stage form a channel, the sixth switch unit is closed to form a corresponding feedback loop, the second output stage outputs a voltage driving signal for driving the first color pixel subunit, the second gain stage, the fourth switch unit and the first output stage form another channel, and the eighth switch unit is closed to form a corresponding feedback loop, the first output stage outputs a voltage driving signal for driving the second color pixel subunit, the display driving circuit can switch between the gain stage and the output stage in each channel amplifier by setting the switch between the gain stage and the output stage, and through the switching of each switch unit, the first channel amplifier and the second channel amplifier can cooperate with each other, thereby enabling the first channel amplifier and the second channel amplifier to respectively output the voltage driving signal for driving the first color pixel subunit and the voltage driving signal for driving the second color pixel subunit, further enabling the pixel units with a plurality of color pixel subunits to drive the pixel units, wherein the arrangement of the switch units greatly reduces the overall output power of the display panel from the display amplifier and the display panel.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a block diagram of a circuit structure of a display driver circuit according to an embodiment of the present disclosure;
fig. 2 is a block diagram of a circuit structure of another display driving circuit provided in an embodiment of the present application;
fig. 3 is a block diagram of a circuit structure of another display driver circuit provided in an embodiment of the present application;
fig. 4 is a block diagram of a circuit structure of another display driving circuit provided in an embodiment of the present application;
fig. 5 is a block diagram of a circuit structure of a further display driving circuit provided in an embodiment of the present application;
FIG. 6 is a schematic diagram of an output of a display driving circuit provided in an embodiment of the present application at different times;
fig. 7 is a schematic circuit structure diagram of a display driving circuit according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. The following embodiments and their technical features may be combined with each other without conflict.
A display driving circuit 100 is applied to a display panel, the display panel includes a plurality of pixel units, each pixel unit includes a first color pixel sub-unit and a second color pixel sub-unit, the display driving circuit 100 includes:
a first channel amplifier 110, including a first gain stage 111, a first switch unit Q1 and a first output stage 112, which are electrically connected in sequence;
a second channel amplifier 120, including a second gain stage 121, a second switching unit Q2 and a second output stage 122 electrically connected in sequence;
the output end of the first gain stage 111 is electrically connected to the input end of the second output stage 122 through a third switching unit Q3, and the input end of the first output stage 112 is electrically connected to the output end of the second gain stage 121 through a fourth switching unit Q4;
a first input end of the first gain stage 111 is configured to input a first pixel digital level signal to drive the first color pixel subunit, a second input end of the first gain stage 111 is electrically connected to an output end of the first output stage 112 through the fifth switch unit Q5, and a second input end of the first gain stage 111 is further electrically connected to an output end of the second output stage 122 through the sixth switch unit Q6;
a first input end of the second gain stage 121 is configured to input a second pixel digital level signal to drive the second color pixel subunit, a second input end of the second gain stage 121 is electrically connected to an output end of the second output stage 121 through the seventh switch unit Q7, and a second input end of the second gain stage 121 is also electrically connected to an output end of the first output stage 112 through the eighth switch unit Q8;
when there is an output in the first output stage 112 and the second output stage 122, the first switching unit Q1, the second switching unit Q2, the fifth switching unit Q5 and the seventh switching unit Q7 are all in a first switching state, and the third switching unit Q3, the fourth switching unit Q4, the sixth switching unit Q7 and the eighth switching unit Q8 are all in a second switching state, where the first switching state and the second switching state are opposite.
A first input terminal of the first gain stage 111 is a non-inverting input terminal of the first channel amplifier 110, a second input terminal of the first gain stage 111 is an inverting input terminal of the first channel amplifier 110, a first input terminal of the second gain stage 121 is a non-inverting input terminal of the second channel amplifier 120, and a second input terminal of the second gain stage 121 is an inverting input terminal of the second channel amplifier 120.
In the display driving circuit 100, when the first switch state is a closed state, the first gain stage 111, the first switch unit Q1 and the first output stage 112 form a path, the fifth switch unit Q5 is closed to form a feedback loop, at this time, the first output stage 112 outputs a voltage driving signal for driving the first color pixel subunit, the second gain stage 121, the second switch unit Q2 and the second output stage 122 form another path, the seventh switch unit Q7 is closed to form a corresponding feedback loop, at this time, the second output stage 122 outputs a voltage driving signal for driving the second color pixel subunit.
In the display driving circuit 100, when the first switching state is the off state, the second switching state is the on state, the first gain stage 111, the third switching unit Q3 and the second output stage 122 form a path, the sixth switching unit Q6 is closed to form a corresponding feedback loop, at this time, the second output stage 122 outputs the voltage driving signal for driving the first color pixel subunit, the second gain stage 121, the fourth switching unit Q4 and the first output stage 112 form another path, the eighth switching unit Q8 is closed to form a corresponding feedback loop, at this time, the first output stage 112 outputs the voltage driving signal for driving the second color pixel subunit.
In one embodiment, the first color pixel sub-unit is a red pixel sub-unit, the first pixel digital level signal is a red pixel digital level signal, the second color pixel sub-unit is a blue pixel sub-unit, and the second pixel digital level signal is a blue pixel digital level signal.
In the display driving circuit 100, the switches are disposed between the gain stage and the output stage in each channel amplifier, and the first channel amplifier 110 and the second channel amplifier 120 can cooperate with each other through the switching of each switch unit, so that the first channel amplifier 110 and the second channel amplifier 120 can switch between outputting the voltage driving signal for driving the first color pixel subunit and the voltage driving signal for driving the second color pixel subunit, respectively, and further can drive the pixel units having pixel subunits of multiple colors. The switch unit is arranged between the gain stage and the output stage in each channel amplifier, so that the resistance component between the output end of each channel amplifier and the pixel unit in the display panel is greatly reduced, the output delay characteristic of each channel amplifier in the drive IC is greatly reduced while the normal display of pixel patterns of the display panel is ensured, and the drive power of each channel amplifier is integrally reduced.
In one embodiment, the display driving circuit 100 further includes a switch control unit, wherein a first control signal output end of the switch control unit is electrically connected to respective control ends of the first switch unit Q1, the second switch unit Q2, the fifth switch unit Q5 and the seventh switch unit Q7 respectively to output a first control signal;
a second control signal output end of the switch control unit is electrically connected with respective control ends of the third switch unit Q3, the fourth switch unit Q4, the sixth switch unit Q6 and the eighth switch unit Q8 respectively to output a second control signal.
For example, when the structures of the respective switch units are the same, the first control signal is a high level signal, the first switch unit Q1, the second switch unit Q2, the fifth switch unit Q5 and the seventh switch unit Q7 are in a closed state, at this time, the second control signal is a low level signal, and the third switch unit Q3, the fourth switch unit Q4, the sixth switch unit Q6 and the eighth switch unit Q8 are in an open state.
In one embodiment, each pixel cell further includes a third color pixel sub-cell, as shown in fig. 2, the display driving circuit 100 further includes:
a third channel amplifier 130, including a third gain stage 131, a ninth switching unit Q9 and a third output stage 132 electrically connected in sequence, where a first input end of the third output stage 132 is used to input a third pixel digital level signal to drive a third color pixel subunit, and a second input end of the third output stage 132 is further electrically connected to an output end of the third output stage 132;
the third control signal output end of the switch control unit is electrically connected to the ninth switch unit Q9 for outputting the third control signal.
In one embodiment, as shown in fig. 3, the display driving circuit 100 further includes:
a fourth channel amplifier 140, including a fourth gain stage 141, a tenth switching unit Q10, and a fourth output stage 142 electrically connected in sequence, where a first input end of the fourth output stage 142 is used to input a third pixel digital level signal to drive the third color pixel subunit, and a second input end of the fourth output stage 142 is further electrically connected to an output end of the fourth output stage 142;
the third control signal output end of the switch control unit is further electrically connected to the control end of the tenth switch unit Q10, and is configured to output a third control signal.
Since the first input terminal of the fourth output stage 142 is used for inputting the third pixel digital level signal, the voltage output signal of the fourth output stage 142 is the same as the voltage output signal of the third output stage 132, that is, the voltage output signals of the fourth channel amplifier 140 and the third channel amplifier 130 are both used for driving the third color pixel sub-unit.
A first input end of the third gain stage 131 is a non-inverting input end of the third channel amplifier 130, a second input end of the third gain stage 131 is an inverting input end of the third channel amplifier 130, a first input end of the fourth gain stage 141 is a non-inverting input end of the fourth channel amplifier 140, and a second input end of the fourth gain stage 141 is an inverting input end of the fourth channel amplifier 140.
In one embodiment, the first color pixel subunit is a red pixel subunit, the first pixel digital level signal is a red pixel digital level signal, the second color pixel subunit is a blue pixel subunit, the second pixel digital level signal is a blue pixel digital level signal, the third color pixel subunit is a green pixel subunit, and the third pixel digital level signal is a green pixel digital level signal.
Referring to fig. 3, if R represents a red pixel subunit, G represents a green pixel subunit, B represents a blue pixel subunit, the output of the first channel amplifier 110 is denoted as OUT1, the output of the second channel amplifier 120 is denoted as OUT3, the output of the third channel amplifier 130 is denoted as OUT2, the output of the fourth channel amplifier 140 is denoted as OUT4, and at this time, the outputs are arranged in the order of OUT1, OUT2, OUT3, and OUT4, and OUT1, OUT2, OUT3, and OUT4 are respectively used to drive each corresponding pixel subunit in a display panel, and at this time, the display panel including each pixel unit is generally called an RGBG panel.
In one embodiment, the switch control unit adopts a clock control unit, and the first control signal, the second control signal and the third control signal are all periodic control signals, and the respective signal periods are the same.
In one embodiment, the first control signal and the second control signal have respective opposite level states.
In one embodiment, each switching unit adopts a MOS switching tube or a triode.
In one embodiment, as shown in fig. 4, the display driving circuit 100 further includes a signal processor 150, and a first signal generating unit 160, a second signal generating unit 170, and a third signal generating unit 180 electrically connected to the signal processor 150, respectively, wherein the first signal generating unit 160 is further electrically connected to the first input terminal of the first gain stage 111, the second signal generating unit 170 is electrically connected to the first input terminal of the second gain stage 121, and the third signal generating unit 180 is electrically connected to the first input terminal of the third output stage 132;
the signal processor 150 is configured to convert the input initial signal data into three paths of monochromatic signal data, and output the three paths of monochromatic signal data respectively, where the three paths of monochromatic signal data include first monochromatic signal data, second monochromatic signal data, and third monochromatic signal data;
the first signal generating unit 160 is configured to receive the first monochrome signal data and perform conversion processing on the first monochrome signal data to generate a first pixel digital level signal and output the first pixel digital level signal to the first input terminal 110 of the first gain stage;
the second signal generating unit 170 is configured to receive the second monochrome signal data and perform conversion processing on the second monochrome signal data to generate a second pixel digital level signal and output the second pixel digital level signal to the first input terminal 120 of the second gain stage;
the third signal generating unit 180 is configured to receive the third monochromatic signal data and perform conversion processing on the third monochromatic signal data to generate a third pixel digital level signal and output the third pixel digital level signal to the third channel amplifier 130.
In one embodiment, referring to fig. 4, the first signal generating unit 160 includes a first shift register 161, a first latch 162 and a first decoder 163 electrically connected, and an output terminal of the first decoder 163 is electrically connected to a first input terminal of the first gain stage 111;
the second signal generating unit 170 includes a second shift register 171, a second latch 172 and a second decoder 173 electrically connected to each other, and an output terminal of the second decoder 173 is electrically connected to a first input terminal of the second gain stage 121;
the third signal generating unit 180 includes a third shift register 181, a third latch 182, and a third decoder 183 electrically connected to each other, wherein an output terminal of the third decoder 183 is electrically connected to a first input terminal of the third gain stage 131.
In another embodiment, on the basis of fig. 4, as shown in fig. 5, the display driving circuit 100 further includes the fourth channel amplifier 140 and a corresponding fourth signal generating unit 190, and the fourth signal generating unit 190 includes: a fourth shift register 191, a fourth latch 192 and a fourth decoder 193 electrically connected.
The output terminal of the fourth decoder 193 in the fourth signal generating unit 190 is further connected to the first input terminal of the fourth gain stage 141, and at this time, the fourth signal generating unit 190 is further configured to generate a third pixel digital level signal and output the third pixel digital level signal to the first input terminal of the fourth gain stage 141, and the voltage output signals of the fourth channel amplifier 140 and the third channel amplifier 130 are the same.
In this embodiment, the first monochrome signal data is red signal data, the first pixel digital level signal is a red pixel digital level signal, the first color pixel subunit is a red pixel subunit, the second monochrome signal data is blue signal data, the second pixel digital level signal is a blue pixel digital level signal, the second color pixel subunit is a blue pixel subunit, the third monochrome signal data is green signal data, and the third pixel digital level signal is a green pixel digital level signal, referring to fig. 5, if R represents a red pixel subunit, G represents a green pixel subunit, B represents a blue pixel subunit, the output of the first channel amplifier 110 is denoted as OUT1, the output of the second channel amplifier 120 is denoted as OUT3, the output of the third channel amplifier 130 is denoted as OUT2, the output of the fourth channel amplifier 140 is denoted as OUT4, at this time, OUT1, OUT2, OUT3, and OUT4 are respectively used to drive each pixel subunit in the display panel rgb, and at this time, the corresponding display panel is generally called a G panel.
In this embodiment, the display driving circuit 100 includes a switch control unit, the switch control unit employs a clock control unit, the first control signal, the second control signal and the third control signal are all periodic control signals (i.e. clock period signals), and their signal periods are the same, and their respective level states are opposite, as shown in fig. 6, in a period T1, OUT1 is used to drive a red pixel subunit, OUT2 is used to drive a green pixel subunit, OUT3 is used to drive a blue pixel subunit, and OUT4 is used to drive a green pixel subunit; in period T2, OUT1 is used to drive the blue pixel sub-unit, OUT2 is used to drive the green pixel sub-unit, OUT3 is used to drive the red pixel sub-unit, and OUT4 is used to drive the green pixel sub-unit; in the period T3, OUT1, OUT2, OUT3, and OUT4 are all the same as the period T1; in periods T4, OUT1, OUT2, OUT3 and OUT4 are all the same as the period T2, in other words, the period T1 and the period T2 are a complete cycle period, where SW1 represents a first control signal of the switch control unit, SW2 represents a second control signal of the switch control unit, SW3 represents a third control signal of the switch control unit, R0 in OUT1 represents a voltage driving signal driving the red pixel subunit, B0 in OUT1 represents a voltage driving signal driving the blue pixel subunit, G0 in OUT2 represents a voltage driving signal driving the green pixel subunit, B0 in OUT3 and OUT4 represents a voltage driving signal driving the green pixel subunit, and R0 in OUT3 represents a voltage driving signal driving the red pixel subunit.
For illustration, fig. 6 only illustrates four time periods T1 to T4, and the actual time period is not limited thereto.
In one embodiment, the display driving circuit 100 includes a first channel amplifier 110, a second channel amplifier 120, a third channel amplifier 130, and a fourth channel amplifier 140, wherein the circuit structures of the third channel amplifier 130 and the fourth channel amplifier 140 are the same, and the circuit structure of the first channel amplifier 110 after the switch Q3 is removed is the same as the circuit structure of the third channel amplifier 130 (refer to fig. 7), and therefore, for simplicity, only the circuit structures of the first channel amplifier 110 and the second channel amplifier 120 are illustrated in fig. 7.
As shown in fig. 7, AVDD represents an analog circuit positive voltage source, VSSA represents an analog ground, VBP1 represents a forward bias voltage, VBN1 represents a reverse bias voltage, PO1 represents an output signal of the corresponding first gain stage 111 when the bias voltage is VBN1, NO1 represents an output signal of the corresponding first gain stage 111 when the bias voltage is VBP1, C represents a display panel capacitance, Q1 represents a first switching unit, Q2 represents a second switching unit, Q3 represents a third switching unit, Q4 represents a fourth switching unit, Q5 represents a fifth switching unit, and since the bias voltages are divided into two types, VBP1 and VBN1, Q2, Q3, Q4, and Q5 are each provided with two (shown in fig. 7), OUT1 represents a voltage driving signal output from the first channel amplifier 110, and OUT2 represents a voltage driving signal output from the second channel amplifier 120.
Wherein, T1, T2, T6, T8, T9, T10, T11, T12, T18, T21, T22, T23, T27, T29, T30, T31, T32, T33, T39 and T41 all represent N-type IGBT tubes (Insulated Gate Bipolar transistors), and T3, T4, T5, T7, T13, T14, T15, T16, T17, T19, T20, T24, T25, T26, T28, T34, T35, T36, T37, T38 and T40 all represent P-type IGBTs.
Wherein FB1 represents the gate terminal of T6, FB1 is electrically connected to Q1 and Q3, respectively, FB1 represents the gate terminal of T27, FB2 is electrically connected to Q2 and Q4, respectively (for convenience of illustration, the connections between FB1 and Q3, and the connections between FB2 and Q4 are shown separately).
A display panel adopts the display driving circuit 100.
In one embodiment, the display panel is an OLED display panel.
That is, the above description is only an embodiment of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by using the contents of the specification and the drawings, such as mutual combination of technical features between various embodiments, or direct or indirect application to other related technical fields, are included in the scope of the present application.
In addition, structural elements having the same or similar characteristics may be identified by the same or different reference numerals. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In this application, the word "for example" is used to mean "serving as an example, instance, or illustration". Any embodiment described herein as "for example" is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make or use the present application. In the foregoing description, various details have been set forth for the purpose of explanation.
It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes are not shown in detail to avoid obscuring the description of the present application with unnecessary detail. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
Claims (10)
1. A display driving circuit, applied to a display panel including a plurality of pixel units, each pixel unit including a first color pixel sub-unit and a second color pixel sub-unit, the display driving circuit comprising:
the first channel amplifier comprises a first gain stage, a first switch unit and a first output stage which are electrically connected in sequence;
the second channel amplifier comprises a second gain stage, a second switch unit and a second output stage which are electrically connected in sequence;
the output end of the first gain stage is electrically connected with the input end of the second output stage through the third switching unit;
the input end of the first output stage is also electrically connected with the output end of the second gain stage through the fourth switching unit;
wherein a first input terminal of the first gain stage is used for inputting a first pixel digital level signal to drive the first color pixel subunit;
the display driving circuit further includes:
a fifth switching unit, through which a second input terminal of the first gain stage is electrically connected to an output terminal of the first output stage;
the second input end of the first gain stage is also electrically connected with the output end of the second output stage through the sixth switch unit, and the first input end of the second gain stage is used for inputting a second pixel digital level signal so as to drive the second color pixel subunit;
a second input terminal of the second gain stage is electrically connected with an output terminal of the second output stage through the seventh switch unit;
the second input end of the second gain stage is also electrically connected with the output end of the first output stage through the eighth switch unit;
when the first output stage and the second output stage have outputs, the first switch unit, the second switch unit, the fifth switch unit and the seventh switch unit are all in a first switch state, the third switch unit, the fourth switch unit, the sixth switch unit and the eighth switch unit are all in a second switch state, and the first switch state and the second switch state are opposite.
2. The display driving circuit according to claim 1, further comprising a switch control unit, wherein a first control signal output terminal of the switch control unit is electrically connected to respective control terminals of the first switch unit, the second switch unit, the fifth switch unit and the seventh switch unit to output a first control signal;
and a second control signal output end of the switch control unit is electrically connected with respective control ends of the third switch unit, the fourth switch unit, the sixth switch unit and the eighth switch unit respectively so as to output a second control signal.
3. The display driver circuit of claim 2, wherein each pixel cell further comprises a third color pixel sub-cell, the display driver circuit further comprising:
the third channel amplifier comprises a third gain stage, a ninth switching unit and a third output stage which are electrically connected in sequence, wherein a first input end of the third gain stage is used for inputting a third pixel digital level signal so as to drive the third color pixel subunit, and a second input end of the third gain stage is also electrically connected with an output end of the third output stage;
and the third control signal output end of the switch control unit is electrically connected with the ninth switch unit and is used for outputting a third control signal.
4. The display driver circuit according to claim 3, wherein the display driver circuit further comprises:
a fourth channel amplifier, including a fourth gain stage, a tenth switching unit and a fourth output stage, which are electrically connected in sequence, wherein a first input terminal of the fourth gain stage is used for inputting the third pixel digital level signal to drive the third color pixel subunit, and a second input terminal of the fourth gain stage is further electrically connected with an output terminal of the fourth output stage;
the third control signal output end is further electrically connected to the control end of the tenth switching unit, and is configured to output the third control signal.
5. The display driving circuit according to claim 3, wherein the switch control unit is a clock control unit, and the first control signal, the second control signal, and the third control signal are all periodic control signals having the same signal period.
6. The display driving circuit according to claim 5, wherein the first control signal and the second control signal have opposite level states.
7. The display driving circuit according to claim 1, wherein each of the switching units employs a MOS switch transistor or a triode.
8. The display driving circuit according to claim 3, wherein the display driving circuit further comprises a signal processor, and a first signal generating unit, a second signal generating unit and a third signal generating unit electrically connected to the signal processor, respectively, the first signal generating unit further electrically connected to the first input terminal of the first gain stage, the second signal generating unit electrically connected to the first input terminal of the second gain stage, and the third signal generating unit electrically connected to the first input terminal of the third gain stage;
the signal processor is used for converting input initial signal data into three paths of monochromatic signal data and outputting the three paths of monochromatic signal data respectively, wherein the three paths of monochromatic signal data comprise first monochromatic signal data, second monochromatic signal data and third monochromatic signal data;
the first signal generation unit is used for receiving the first monochromatic signal data and carrying out conversion processing on the first monochromatic signal data so as to generate the first pixel digital level signal and output the first pixel digital level signal to the first input end of the first gain stage;
the second signal generation unit is used for receiving the second monochromatic signal data and carrying out conversion processing on the second monochromatic signal data so as to generate a second pixel digital level signal and output the second pixel digital level signal to a first input end of the second gain stage;
the third signal generation unit is configured to receive the third monochromatic signal data and perform conversion processing on the third monochromatic signal data to generate the third pixel digital level signal and output the third pixel digital level signal to the third channel amplifier.
9. The display driving circuit according to claim 8, wherein the first signal generating unit comprises a first shift register, a first latch, and a first decoder electrically connected to each other, and an output terminal of the first decoder is electrically connected to a first input terminal of the first gain stage;
the second signal generating unit comprises a second shift register, a second latch and a second decoder which are electrically connected, and the output end of the second decoder is electrically connected with the first input end of the second gain stage;
the third signal generating unit comprises a third shift register, a third latch and a third decoder which are electrically connected, and the output end of the third decoder is electrically connected with the first input end of the third gain stage.
10. A display panel characterized in that the display panel employs the display drive circuit according to any one of claims 1 to 9.
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| KR100498489B1 (en) * | 2003-02-22 | 2005-07-01 | 삼성전자주식회사 | Liquid crystal display source driving circuit with structure providing reduced size |
| JP4731195B2 (en) * | 2005-04-07 | 2011-07-20 | ルネサスエレクトロニクス株式会社 | Liquid crystal display device, liquid crystal driver, and driving method of liquid crystal display panel |
| JP4466735B2 (en) * | 2007-12-28 | 2010-05-26 | ソニー株式会社 | SIGNAL LINE DRIVE CIRCUIT, DISPLAY DEVICE, AND ELECTRONIC DEVICE |
| US20100033411A1 (en) * | 2008-08-05 | 2010-02-11 | Ching-Chung Lee | Source driver with plural-feedback-loop output buffer |
| US20100149171A1 (en) * | 2008-12-16 | 2010-06-17 | Da-Rong Huang | Source driver for driving a panel and related method for controlling a display |
| JP2013172398A (en) * | 2012-02-22 | 2013-09-02 | Renesas Electronics Corp | Operational amplifier circuit, display panel driver and display device |
| KR101451589B1 (en) * | 2012-12-11 | 2014-10-16 | 엘지디스플레이 주식회사 | Driving apparatus for image display device and method for driving the same |
| US10755662B2 (en) * | 2017-04-28 | 2020-08-25 | Samsung Electronics Co., Ltd. | Display driving circuit and operating method thereof |
| CN111028783B (en) * | 2018-10-04 | 2022-04-15 | 乐金显示有限公司 | Pixel sensing device, organic light emitting display device and pixel compensation method thereof |
| CN110728951A (en) * | 2019-10-23 | 2020-01-24 | 广东晟合技术有限公司 | Driving structure and method of OLED panel with multiplexing switch and panel |
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