CN113886149A - Programmable device and cloud system - Google Patents

Abstract

A programmable device and a cloud system are disclosed. The programmable device includes: a plurality of devices under test, including a first device under test; the control module is used for receiving a test data packet, analyzing the test data packet, obtaining an identifier of the first equipment to be tested and a test command executed by the first equipment to be tested, determining a first connecting channel from a plurality of connecting channels according to the identifier of the first equipment to be tested, and sending the test command to the first connecting channel; and the plurality of connecting channels comprise the first connecting channel, and the first connecting channel sends the test command to the first device to be tested for execution. In view of the fact that the connection channel is designed in the programmable device in a hardware programming mode, the embodiment of the disclosure can construct multiple connection channels in the same programmable device, and different connection channels are connected with different devices to be tested for testing, thereby realizing that the same programmable device is used for testing multiple devices to be tested.

Description

Programmable device and cloud system

Technical Field

The present disclosure relates to the field of processor testing, and more particularly, to a programmable device and a cloud system.

Background

Testing is an important step in the research and development process. For example, in the design process of an embedded processor, a developer needs to frequently perform a function and performance test on the embedded processor, and after the hardware structure and the hardware logic of the embedded processor are basically fixed, a customer with a purchase intention can evaluate whether the performance of the embedded processor reaches a set index through the test.

FIG. 1 illustrates a test scenario for an embedded processor. As shown in the figure, the client software 111 is deployed on the terminal 11, and the server program 131 is deployed on the server 13. The client software 111 and server program 131 communicate over the network 12, and the server 13 communicates with a Field Programmable Gate Array (FPGA) device 15 via an interface 14. The FPGA belongs to a semi-custom circuit in an application-specific integrated circuit and comprises a plurality of hardware programmable components. When the FPGA is used for testing the embedded processor, the hardware programmable assembly of the FPGA can be used for building the embedded processor and the processor logic of the embedded processor. The test process comprises the following steps: the client software 111 sends test commands to the embedded processor 151 via the server program 131 and receives test results. Referring to the figure, a customer can evaluate various aspects of the code density, the performance, the debugging capability and the like of the embedded processor through testing, and a developer can debug the embedded processor continuously through testing.

However, the inventor finds that, in the test scenario, at the same time, the research and development staff and the client can only use the FPGA device for testing one to one, which results in high dynamic requirements on the FPGA device, and a large amount of FPGA devices need to be purchased to meet the test requirements.

Disclosure of Invention

In view of the above, the present disclosure is directed to a programmable device and a cloud system to solve the problems of the prior art.

According to a first aspect of embodiments of the present disclosure, there is provided a programmable device, comprising:

a plurality of devices under test, including a first device under test;

the control module is used for receiving a test data packet, analyzing the test data packet, obtaining an identifier of the first equipment to be tested and a test command executed by the first equipment to be tested, determining a first connecting channel from a plurality of connecting channels according to the identifier of the first equipment to be tested, and sending the test command to the first connecting channel;

and the plurality of connecting channels comprise the first connecting channel, and the first connecting channel sends the test command to the first device to be tested for execution.

Optionally, the control module is further configured to receive test result data from the first connection channel and send the test result data.

Optionally, the control module further includes a memory controller, the memory controller is configured to read, from a memory, correspondence data between a connection channel and a device under test, and the control module retrieves the correspondence data using an identifier of the first device under test to determine the first connection channel.

Optionally, the first device to be tested is an embedded processor, and the test command is written into an instruction register or a flash memory via a JTAG interface so as to be read and executed by the embedded processor.

Optionally, the first device to be tested is an embedded system, and the test command is written into a flash memory of the embedded system via a JTAG interface so as to be read and executed by an embedded processor in the embedded system.

Optionally, the control module receives the test data packet through an interface type of one of the following:

PCIe interface, USB interface, UART interface.

Optionally, the test data packet includes an identification of a plurality of first devices to be tested and a plurality of test commands to be executed by the first devices to be tested.

Optionally, the multiple devices under test are virtual devices constructed by hardware programming through programmable components provided by the programmable devices, or,

the equipment to be tested is a plurality of entity equipment and is connected with the entity equipment through the programmable equipment.

Optionally, the plurality of connection channels are implemented as one or more of an AXI bus, an APB bus, a universal asynchronous receiver transmitter, and a serial peripheral interface.

Optionally, the programmable device is an FPGA device.

In a second aspect, an embodiment of the present disclosure provides a cloud system based on a programmable device, including: the programmable device and the cloud server of any one of the above, where the cloud server is deployed with a server program, and the server program is configured to receive the test command from a client program, and organize and send the test data packet according to the test command.

Optionally, the server program is further configured to verify whether a user who sends the test command has an authority to operate the first device to be tested.

Optionally, the server program is further configured to organize a plurality of test commands in the same test data packet.

In the embodiment of the present disclosure, since the connection channel is designed in the programmable device in a hardware programming manner, multiple connection channels may be constructed in the same programmable device, and different connection channels are connected to different devices to be tested for testing, so that the same programmable device is used for testing multiple devices to be tested, and therefore, research personnel and customers can reuse the same programmable device for testing multiple devices to be tested.

Drawings

The foregoing and other objects, features, and advantages of the disclosure will be apparent from the following description of embodiments of the disclosure, which refers to the accompanying drawings in which:

FIG. 1 illustrates a test scenario for an existing embedded processor;

FIG. 2 illustrates a hierarchy of a data center to which one embodiment of the present disclosure is applied;

FIG. 3 is a block diagram of a data center to which one embodiment of the present disclosure is applied;

FIG. 4 is a block diagram of the internal structure of a server in a data center according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of the structure of an FPGA;

FIG. 6a is a schematic diagram of a cloud server for implementing one embodiment of the present disclosure;

FIG. 6b is a schematic diagram of a cloud server for implementing one embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a cloud server for implementing one embodiment of the present disclosure;

FIG. 8 is a flow chart of establishing and using a test environment based on an embodiment of the present disclosure.

Detailed Description

The present disclosure is described below based on examples, but the present disclosure is not limited to only these examples. In the following detailed description of the present disclosure, some specific details are set forth in detail. It will be apparent to those skilled in the art that the present disclosure may be practiced without these specific details. Well-known methods, procedures, and procedures have not been described in detail so as not to obscure the present disclosure. The figures are not necessarily drawn to scale.

Data center

Fig. 2 shows a hierarchical structure diagram of a data center as one scenario to which an embodiment of the present disclosure is applied.

A data center is a globally collaborative network of devices that is used to communicate, accelerate, present, compute, store data information over an internet network infrastructure. In future development, the data center will become an asset for enterprise competition. With the popularization of data center applications, artificial intelligence and the like are increasingly applied to data centers. The neural network is an important technology of artificial intelligence, and is widely applied to big data analysis and operation of a data center.

In a conventional large data center, the network structure is generally a three-layer structure shown in fig. 2, i.e., a hierarchical interconnection network model (hierarchical inter-networking model). This model contains the following three layers:

access Layer (Access Layer) 103: sometimes referred to as the edge layer, includes access switch 130 and servers 140 to which the access switch is connected. Each server 140 is a processing and storage entity of a data center in which the processing and storage of large amounts of data is performed by the servers 140. Access switch 130 is a switch used to access these servers to the data center. One access switch 130 accesses multiple servers 140. The access switches 130 are typically located on Top of the Rack, so they are also called set-Top (Top of Rack) switches, which physically connect the servers.

Aggregation Layer (Aggregation Layer) 102: sometimes referred to as the distribution layer, includes aggregation switches 120. Each aggregation switch 120 connects multiple access switches while providing other services such as firewalls, intrusion detection, network analysis, and the like.

Core Layer (Core Layer) 101: including core switches 110. Core switches 110 provide high-speed forwarding of packets to and from the data center and connectivity for multiple aggregation layers. The entire data center network is divided into an L3 layer routing network and an L2 layer routing network, and the core switch 110 provides a flexible L3 layer routing network for the entire data center network.

Typically, the aggregation switch 120 is the demarcation point between L2 and L3 layer routing networks, with L2 below and L3 above the aggregation switch 120. Each group Of aggregation switches manages a Point Of Delivery (POD), within each Of which is a separate VLAN network. Server migration within a POD does not have to modify the IP address and default gateway because one POD corresponds to one L2 broadcast domain.

A Spanning Tree Protocol (STP) is typically used between aggregation switch 120 and access switch 130. STP makes only one aggregation layer switch 120 available for a VLAN network and the other aggregation layer switches 120 are used in the event of a failure (dashed lines in the upper figure). That is, at the aggregation level, no horizontal scaling is done, since only one is still working even if multiple aggregation switches 120 are added.

FIG. 3 illustrates the physical connections of the components in the hierarchical data center of FIG. 2. As shown in fig. 3, one core switch 110 connects multiple aggregation switches 120, one aggregation switch 120 connects multiple access switches 130, and one access switch 130 accesses multiple servers 140.

Cloud server

Since the cloud server 140 is a real device of the data center, fig. 4 shows a structural block diagram of the inside of the cloud server 140. The cloud server 140 includes a memory 210, a Central Processing Unit (CPU)220, and various acceleration units connected by a bus. These acceleration units include an acceleration unit 230 dedicated to the neural network, a Data Transfer Unit (DTU)260, a graphics processing unit (GPU, not shown), an application specific integrated circuit (ASIC, not shown), and a field programmable gate array 240.

In the traditional processor architecture design, a control unit and a storage unit occupy a large part of space in the architecture, and the space occupied by a computing unit is insufficient, so that the traditional processor architecture design is very effective in logic control and is not efficient in large-scale parallel computing. Therefore, various special acceleration units have been developed to perform more efficient processing for increasing the operation speed for calculations of different functions and different fields. The respective accelerating units will be described below.

The acceleration unit 230: the method is a processing unit which adopts a data-driven parallel computing architecture and is used for processing a large number of operations (such as convolution, pooling and the like) of each neural network node. Because data in a large number of operations (such as convolution, pooling and the like) of each neural network node and intermediate results are closely related in the whole calculation process and are frequently used, the existing CPU framework is adopted, and because the memory capacity in a CPU core is small, a large amount of external storage is frequently accessed, and the processing efficiency is low. By adopting the accelerating unit, each core is provided with an on-chip internal memory with the storage capacity suitable for the neural network calculation, so that the frequent access to a memory outside the core is avoided, the processing efficiency can be greatly improved, and the calculation performance is improved.

And the Data Transmission Unit (DTU) is a wireless terminal device which is specially used for converting the serial port data into the IP data or converting the IP data into the serial port data and transmitting the serial port data through a wireless communication network. The main function of the DTU is to wirelessly transmit data from the remote device back to the back office. At the front end, the DTU interfaces with the customer's equipment. After the DTU is powered on and operated, the DTU is firstly registered to a mobile GPRS network and then goes to a background center arranged in the DTU to establish socket connection. The background center is used as a server side of socket connection, and the DTU is a client side of socket connection. Therefore, the DTU and the background software are matched for use, and after the connection is established, the front-end equipment and the background center can perform wireless data transmission through the DTU.

Graphics Processing Unit (GPU): is a microprocessor specially used for image and graph related operation. The GPU develops the defect of too little space of a computing unit in the CPU, and adopts a large number of computing units specially used for graphics computation, so that the display card reduces the dependence on the CPU and bears some of the computation-intensive graphics image processing work originally borne by the CPU.

Application Specific Integrated Circuit (ASIC): refers to integrated circuits designed and manufactured to meet the needs of a particular user and the needs of a particular electronic system. Since such integrated circuits are customized to the user's requirements, their structure is often tailored to the specific user's requirements.

Field Programmable Gate Array (FPGA) 240: is a product developed on the basis of programmable devices such as PAL, GAL and the like. The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited.

Basic structure of FPGA

As shown in fig. 5, the FPGA is mainly completed by 6 parts, which are: the system comprises a programmable input output unit (IOB), a basic programmable logic unit (CLB), a Digital Clock Management (DCM), an embedded block type RAM (SRAM), a programmable internal connection line (PI), an embedded bottom layer functional unit and an embedded special hardware module.

Programmable input output cell (IOB): the interface part of the chip and an external circuit is used for finishing the driving and matching requirements of input/output signals under different electrical characteristics. I/O within an FPGA is categorized by groups, each of which can independently support different I/O standards. Through the flexible configuration of software, different electrical standards and I/O physical characteristics can be adapted, the magnitude of the driving current can be adjusted, and the pull-up resistor and the pull-down resistor can be changed.

Basic programmable logic Cell (CLB): is the basic logic unit within an FPGA. The actual number and characteristics of CLBs will vary from device to device, but each CLB contains a configurable switch matrix consisting of 4 or 6 inputs, some type selection circuits (multiplexers etc.) and flip-flops. The switch matrix is highly flexible and can be configured to handle combinatorial logic, shift registers or RAM.

Digital Clock Management (DCM): the method is a firmware resource which is integrated in a higher-level FPGA product and is specially used for clock synthesis, clock skew elimination and clock phase adjustment, and the DCM is utilized to complete clock frequency multiplication, frequency division and phase shift conveniently, thereby bringing convenience to the system clock design of the FPGA and bringing the reliability problem

Embedded block ram (bram): most FPGAs have embedded block RAMs, which greatly expands the application range and flexibility of the FPGA. The block RAM may be configured as a single port RAM, a dual port RAM, a Content Address Memory (CAM), and a FIFO, among other common storage structures.

Programmable Interconnect (PI): an FPGA relies on programming it to effectively combine individual CLBs and IOBs to implement system-level logic functions. In practice, the designer does not need to directly select routing resources, and the floorplan router can automatically select routing resources to connect the individual module cells based on the topology and constraint conditions of the input logic netlist. In essence, the use method of the wiring resources and the design result have a close and direct relationship.

Embedded function module: mainly refers to Soft processing cores (Soft Core) such as DLL (delay Locked Loop), PLL (phase Locked Loop), DSP and CPU. At present, more and more abundant embedded functional units enable a single-chip FPGA to become a system-level design tool, so that the single-chip FPGA has the capability of software and hardware combined design and gradually transits to a system-on-chip platform.

Embedding a special hard core: the embedded special Hard Core is relative to the soft Core embedded in the bottom layer, and refers to a Hard Core (Hard Core) with strong processing capacity of an FPGA (field programmable gate array), and is equivalent to an ASIC (application specific integrated circuit). In order to improve the performance of the FPGA, FPGA chip manufacturers integrate some dedicated hardmac inside the chip. For example: in order to improve the multiplication speed of the FPGA, a special multiplier is integrated in the mainstream FPGA; in order to be suitable for communication bus and interface standard, a serial-parallel transceiver (SERDES) is integrated in many high-end FPGAs, and the transceiving speed of tens of Gbps can be achieved.

Cloud server based test scheme

Fig. 6a is a schematic structural diagram of a cloud server for implementing one embodiment of the present disclosure. As shown, cloud server 60 includes server 23, interface 24, and programmable device 34.

The server 23 refers to an entity that provides various services (e.g., software, platform, infrastructure) in the cloud computing environment, but does not include an FPGA. The server 23 has a server program 231 deployed thereon, and the server program 231 receives the test command from the client program 111, organizes the test command into a test data packet, and sends the test data packet to the programmable device 34 through the interface 24 between the server 23 and the programmable device 34. The programmable device 34 may be an FPGA device. Since an FPGA is a semi-custom circuit, it has multiple hardware programmable components, such as the programmable input output cells (IOBs), basic programmable logic Cells (CLBs), Programmable Interconnects (PIs), etc., introduced above, and can be used to build various modules according to application requirements. For example, in the present embodiment, the control module 341, the connection channels 1 to n, and the devices under test 1 to n (i.e., the devices under test 1 to n are virtual devices) are respectively constructed based on programmable components on the FPGA, and the FPGA including the above modules is labeled as the programmable device 34 on the drawing. Wherein n is a positive integer greater than or equal to 2. Of course, some FPGAs provide application components specific to some specific application scenarios in addition to the basic FPGA components (the application components are composed of the basic FPGA components), and thus, in practice, it is necessary to determine how to construct various modules according to the component conditions of the FPGA. Furthermore, the programmable device 34 may also be other programmable devices than an FPGA device, such as a self-built development board, an already-produced development board, and so on.

As shown, control module 341 is configured to receive test packets via interface 24. The test data packet specifies at least one device under test and a test command to be executed by the device under test. The connection channels 1 to n have a definite correspondence with the devices under test 1-n, but may not be in a one-to-one correspondence. The control module 341 first parses the test data packet to obtain the identifier and the test command of the specified device to be tested, then determines the connection channel of the specified device to be tested according to the correspondence between the device to be tested and the connection channel, and then sends the test command to the corresponding connection channel, so that the test command is sent to the specified device to be tested, and the specified device to be tested executes the specific operation content. The device under test may also feed back the test result of the test command to the control module 341 and then to the server program 231, so that the research and development personnel may obtain the test result through the client program 111. Of course, the control module 341 may also receive only the test data packet and send the test data packet to the connection channels 1-n, and the connection channels 1-n analyze the test data packet and determine whether the device under test therein is the device under test corresponding to itself, if so, send the test command to the device under test indicated by the test command, and if not, discard the test command. The test command may be an atomic operation to be performed by the device under test or a set of operations to be performed by the device under test.

As shown in the figure, the interface 24 may be any interface in theory, and may be a parallel interface, such as a USB interface or a PCIe interface; it may also be a serial interface, such as an SPI interface, I2C interface, provided that interface 24 must be supported by both server 23 and FPGA.

As shown in the figure, the devices under test 1 to n may be the same or different devices, for example, the devices under test may be memory devices requiring testing, memory controllers, embedded processors, interface devices, embedded systems including embedded processors, and the like.

As shown in the figure, according to a specific test object, different hardware designs may be implemented to implement the connection channels 1 to n, for example, any one of the connection channels 1 to n may be implemented as an axi (advanced eXtensible interface) bus, an apb (advanced Peripheral bus) bus, a UART (universal asynchronous receiver transmitter), an SPI (serial Peripheral interface), and the like. The construction of any one connection channel usually requires at least the basic FPGA components such as the aforementioned programmable input output unit (IOB), basic programmable logic unit (CLB), Programmable Interconnect (PI), etc. More specifically, for example, to implement an AXI bus, an input/output function of the AXI bus is implemented by using a programmable input/output unit to perform programming coding, then each functional unit based on an AXI protocol is implemented by using a basic programmable logic unit to perform coding, and then data transmission between the functional units is implemented by using programmable interconnect coding, thereby implementing the AXI bus. Other types of connection channels are similar to AXI bus implementations.

Further, in order to manage the connection channel and the device to be tested, the control module 341 may maintain data of a correspondence relationship between the connection channel and the device to be tested, and also maintain control logic codes of the connection channel and the device to be tested, when the control module 341 receives the channel creation command, add a corresponding record in the data of the correspondence relationship and upload the control logic codes to the programmable device (the operation may refer to the description of fig. 8 below), when the control module 341 receives the channel deletion command, delete the corresponding record in the data of the correspondence relationship, and erase the corresponding control logic codes from the storage unit of the programmable device.

In summary, in this embodiment, since the connection channels are designed in the programmable device in a hardware programming manner, multiple connection channels can be constructed in the same programmable device, and different connection channels are connected to different devices to be tested for testing, so that multiple devices to be tested can be tested by using the same programmable device, and therefore, research personnel and customers can reuse the same programmable device for testing multiple devices to be tested. In addition, under the condition that the programmable device resource allows, the number of the connection channels and the devices to be tested can be continuously expanded according to the actual situation.

Fig. 6b is a schematic structural diagram of a cloud server for implementing one embodiment of the present disclosure. Fig. 6b is different from fig. 6a in that the devices under test 1 to m are physical devices located outside the programmable device, and the programmable device 34 and the devices under test 1 to m communicate through the interface connection therebetween. The interface between the two interfaces can be any interface theoretically, and can be a parallel interface, such as a USB interface and a PCIe interface; serial interfaces are also possible, such as SPI interface, I2C interface, but provided that these interfaces must be supported for both programmable device 34 and device under test 1-m.

Of course, fig. 6a to 6b may also be applied in combination, that is, the programmable device is used to build the device to be tested to test the control logic of the device to be tested, and the device to be tested is connected to the entity device to be tested through the interface at the same time, so as to perform the synchronous test of the control logic and the electrical performance.

Fig. 7 is a schematic structural diagram of a cloud server for implementing an embodiment of the present disclosure. When testing an embedded processor, it is usually necessary to build an embedded system and test the embedded processor in the embedded system, so the conventional structure of an exemplary embedded system 1 is shown in the figure. However, it should be understood that with the rapid development of semiconductor technology, the embedded system may be implemented on a silicon chip, that is, an embedded system on chip (SoC), in other words, the embedded systems 1-n on the figure may also be embedded systems on chip, and accordingly, the embedded processors in the embedded systems 1-n on the figure are embedded microprocessors in the SoC.

The following first takes the embedded system 1 shown in fig. 7 as an example to describe the components of the embedded system.

An Embedded system (Embedded system) is a special purpose computer system that is fully Embedded within a controlled device and designed for a specific application. The embedded system is a control, monitoring or auxiliary equipment, a machine or equipment for plant operation, according to the definition of the british institute of Electrical engineers. Unlike general-purpose computer systems such as personal computers, embedded systems typically perform predefined tasks with specific requirements. Because the embedded system only aims at a special task, a designer can optimize the embedded system, the size is reduced, and the cost is reduced. Embedded systems are typically mass produced, so individual cost savings can be made, scaling up with yield by hundreds or thousands.

Although the functions, appearance interfaces, operations, and the like of various specific embedded systems are different, even different, the basic hardware structures are different, and have high similarity to the hardware system of a general-purpose computer, but the application characteristics of the embedded systems cause the embedded systems to have greater differences from the general-purpose computer system in the composition and implementation forms of hardware.

First, in order to meet the requirements of the embedded system on speed, volume and power consumption, data that needs to be stored for a long time, such as an operating system, application software, and special data, are not usually used storage media with large capacity and low speed, such as a magnetic disk, but mostly use a random access Memory 602 or a Flash Memory (Flash Memory), as shown in the figure.

In addition, in the embedded system 1, an a/D (analog/digital conversion) interface 607 and a serial interface 605 are required for the need of measurement and control, which is rarely used in general-purpose computers. The a/D interface 607 mainly performs conversion of an analog signal to a digital signal and conversion of a digital signal to an analog signal, which are required in the test. The embedded system 1 often requires testing when applied to industrial production. Because the single chip generates digital signals, which need to be converted into analog signals for testing, unlike general purpose computers, an a/D (analog/digital conversion) interface 607 is required to complete the related conversion. In addition, the industry often requires multiple embedded systems to be connected in series to perform related functions, and therefore a serial interface 605 for connecting multiple embedded systems in series is required, which is not required in general purpose computers.

In addition, as a basic processing unit, the embedded system 1 often needs to be networked in industrial design, and therefore, a network interface 606 for networking the embedded system 1 is needed. This is also mostly not required in general purpose computers. In addition, some embedded systems 1 employ external buses, depending on the application and size. With the rapid expansion of the application field of the embedded system 1, the embedded system 1 tends to be personalized more and more, and the types of buses adopted are more and more according to the characteristics of the embedded system 1. In addition, boundary scan testing is commonly used in processor chips to test the internal circuitry of the embedded processor 603. To accommodate this testing, a debug interface 604 is employed.

The processing core of the embedded system 1 is the embedded processor 603. The embedded processor 603 typically includes an Arithmetic Logic Unit (ALU), registers, and a control unit therein. The arithmetic logic unit performs actual arithmetic processing. The register is used for storing instructions in the arithmetic processing process, intermediate results in the arithmetic processing process, and the like. The control unit completes control of access to the external random access memory and the flash memory. When the instruction to be executed is executed, the arithmetic logic unit carries the instruction to be executed from the random storage or the flash memory to the register, and decodes and executes the instruction.

It should be noted that the embedded processor 603 in the figure may be processor logic only (which may include a processor core and some system programs) if it is only for the purpose of testing the processor logic of the embedded processor.

With continued reference to fig. 7, based on the embedded system 1 shown in the figure, the test command is first sent to the connection channels 1-n, and then the connection channels 1-n send the test command to the embedded processors in the embedded system 1-n via the specific interfaces on the embedded system 1, and after the embedded processors execute the test command, the test result is fed back to the control module 341 via the specific interfaces and the connection channels.

The specific interface may be one of the debug interface 114, the serial interface 115, and the network interface 116, as shown, or may be a type of interface not shown in the figure, such as a Universal Asynchronous Receiver/Transmitter (Universal Asynchronous Receiver/Transmitter). For embedded systems, the debug interface 114 is usually a JTAG interface, and the test link usually uses the debug interface 114 to send and receive information. It is known that JTAG is issued by Joint Test Action Group (Joint Test Action Group), and is currently used as the IEEE 1149.1 international standard Test protocol. However, the so-called JTAG interface is roughly classified into two types, the first type is used to test the electrical characteristics of the chip and detect whether the integrated circuit of the chip has a problem; the second type is for debugging. Whereas a processor supporting the JTAG interface typically contains both modules. That is, if the first type of JTAG interface is used to transmit a test command and receive a test result in order to test the processor itself, but if the second type of JTAG interface is used to test the processor logic of the embedded processor, the test command should be written to an instruction register of the embedded processor or to a memory (e.g., a random access memory or a flash memory) of the embedded system, and read and executed by the embedded processor. The hardware structure and operating mechanism of the JTAG interface make the testing of the integrated circuit chip by software simple and flexible. In addition, the JTAG interface can also be used for online programming, a user programs at a terminal, uploads a code to a cloud server, and then burns the code into a flash memory of the embedded system through the control module via the connecting channel and the JTAG interface.

With continued reference to fig. 7, the interface 24 may be theoretically any interface, and may be a parallel interface, such as a USB interface, a PCIe interface; it may also be a serial interface, for example, an SPI interface, an I2C interface, and establish a communication connection between the server 231 and the control module 341 through the interface 24, provided that the interface 24 must be supported by both the server 23 and the programmable device 34, i.e., both the server 23 and the programmable device 34 must have the hardware elements and software drivers required by the interface 24.

As described above, the control module 341 will determine the device under test to be tested first, and then determine a connection channel according to the device under test, and in order to implement this function, the control module 341 needs to store the correspondence data between the connection channel and the device under test, where the correspondence data can be stored in the memory 343 shown in the figure and read from the memory 343 through the memory controller 342 of the control module 341. It should be noted that although memory 343 is shown as being external to programmable device 34, it may actually be located within programmable device 34. Also, the memory 343 is typically a nonvolatile memory.

It should be noted that, although the above embodiment implements testing of multiple devices under test by establishing multiple connection channels in the same programmable device and testing different devices under test by using different connection channels, since the corresponding relationship between the user and the device under test is not established, each user can access multiple different devices under test, which is not safe enough. To this end, in a further embodiment, a permission verification module (not shown) is used to ensure that each user can only access a specified device under test. The rights check module is typically included in the server program 231, and the server program 231 may include a user management module (not shown), used for managing various users, establishing corresponding relation between the identification of the device to be tested and the user identification, when the server program 231 receives a test command from a client program 111 for a certain user, the corresponding relation between the user identification and the identification of the equipment to be tested is searched through the user identification of the user, the identification of the equipment to be tested which is authorized to operate is determined, the identification is compared with the equipment identification contained in the test command, if the two are the same, the user is authorized to operate the specified device to be tested, the test command is continuously sent to the programmable device, if the two are different, the user is not authorized to operate the specified device to be tested, and the error information with inconsistent authority is fed back to the client program 111. Of course, although the implementation is complicated, the permission verification module may be disposed in the control module 341, and may store the correspondence between the user identifier and the identifier of the device under test in the memory 343, and determine whether the user sending the test command has permission to access the device under test through the permission verification logic similar to that described above.

Table 1 is an exemplary test packet for illustrating that the server program can organize the test commands sent by multiple users in the same packet.

User identification 1	Identification 1 of a device under test	Test Command 1	Test command 2	Test Command 3
					User identification 2	Identification 2 of device under test	Test command 4	Test command 5

The first row of data represents that the user1 (corresponding to the user identifier 1) sends test commands 1 to 3 to the device to be tested 1 (corresponding to the identifier 1 of the device to be tested), and the second row of data represents that the user 2 (corresponding to the user identifier 2) sends test commands 4 and 5 to the device to be tested 2 (corresponding to the identifier 2 of the device to be tested). That is, the test commands of users 1 and 2 are included in the data packet. Of course, the test data packet may only contain the test command of the same user.

FIG. 8 is a flow chart of establishing and using a test environment based on an embodiment of the present disclosure. The flow chart relates to both administrator and normal user roles. And (3) the administrator user creates a test environment for the common user in the FPGA, and the common user performs the test based on the test environment.

Firstly, an administrator user obtains test requirements submitted by n users (step S501), determines to use a programmable component according to the requirement of the test requirements (step S502), then writes a control logic code of the programmable component (step S503), stores the written control logic code in a cloud server (step S504), and burns the control logic code into a storage unit of the FPGA, thereby forming the programmable device 50. The burning operation is completed by the burning program, and the user sends the burning command and the burning data to the burning program through the terminal. The burning program may be installed on the server 23 in fig. 6a and 6b, for example, and when the burning program runs, the external debugging device is operated through the USB interface of the server 23 to complete the burning. In addition, the burning program can be provided by a manufacturer, if the manufacturer provides the burning program, the burning program is usually integrated in the programmable device, and a user sends a burning command and data to the burning program in the programmable device through a terminal to complete burning. As can be seen from the figure, the programmable device 50 forms a control module 501, a plurality of connection channels 1-n, and devices under test 1-n by means of programmable components and control logic code. After the programmable device 50 is successfully built, the devices under test 1-n can be assigned to the users 1-n, respectively. Users 1-n are normal users who have access to only the device under test assigned to them on programmable device 50 through the authorization check. As an optional implementation manner, the device to be tested may be named according to the User identifier to which the device to be tested belongs, for example, a certain device to be tested belongs to User1, and then the identifier of the device to be tested is defined as User1_, where _representsany character, so that it is convenient to determine whether the User has an authority to access the device according to the identifier of the device to be tested.

Continuing with fig. 8, the general user sends a test command through the client program 111 (step S506), performs permission check in the server program (step S507), sends the test command passing permission check to the control module 501, sends the test command to one of the devices under test 1-n through one of the channels, returns the test result to the control module 501 after execution, and obtains the test result through steps S509 and S510. As shown in the figure, steps S501 to S503 and steps S506 and S511 may be implemented in the client program 111. Steps S504-S505 and steps S507 to S510 may be implemented by a server program. The client and server programs can be browser-based applications, and can also be C/S structure-based applications. By means of such an application and the programmable device 50, it is possible to help to implement a test of multiple devices under test using the same programmable device.

In embodiments of the present disclosure, the programmable components may be hardware programmed using Verilog HDL. Verilog HDL is a hardware description language that is currently popular.

In addition, the flow chart can be changed in practical tests. For example, an administrator user may only be responsible for control logic codes of the control module and the connection channel, the device to be tested is built by a common user, the control logic codes are written by the user and uploaded to the programmable device, the common user can check all currently available programmable components on the programmable device on the client program 111, then apply for using the components to the administrator user, and build the device to be tested by himself and write and upload the control logic codes.

In addition, the above embodiments can also be theoretically applied to an ASIC, but since the ASIC has no programmability, only a fixed number of connection channels can be implemented on the ASIC, and a fixed number of devices under test can be tested. That is, the solution based on ASIC implementation is not scalable. Furthermore, there are some variants of FPGAs on the market today that add ASIC logic to the FPGA for processing of specific functions, but these products are still actually assigned to the FPGA.

Commercial value of the disclosed embodiments

As a semi-custom circuit, the FPGA has advantages such as fast logic update and programming after deployment compared with an ASIC chip, and is widely used in a cloud server of a computing center in recent years. The embodiment of the disclosure realizes that a plurality of test cases are designed on the same cloud server. The user can purchase one or more test cases to complete the test work of the own application. The user can also purchase the use permission of the programmable component of the cloud server, and then the test case meeting the self requirement is designed through a hardware programming technology based on the basic function realized on the cloud server. Both of these approaches have market prospects and commercial value.

As will be appreciated by one skilled in the art, the present disclosure may be embodied as systems, methods and computer program products. Accordingly, the present disclosure may be embodied in the form of entirely hardware, entirely software (including firmware, resident software, micro-code), or in the form of a combination of software and hardware. Furthermore, in some embodiments, the present disclosure may also be embodied in the form of a computer program product in one or more computer-readable media having computer-readable program code embodied therein.

Any combination of one or more computer-readable media may be employed. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium is, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer-readable storage medium include: an electrical connection for the particular wire or wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical memory, a magnetic memory, or any suitable combination of the foregoing. In this context, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with a processing unit, apparatus, or device.

A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a chopper. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any other suitable combination. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction system, apparatus, or device.

Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., and any suitable combination of the foregoing.

Computer program code for carrying out embodiments of the present disclosure may be written in one or more programming languages or combinations. The programming language includes an object-oriented programming language such as JAVA, C + +, and may also include a conventional procedural programming language such as C. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).

The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.

Claims (13)

1. A programmable device, comprising:

a plurality of devices under test, including a first device under test;

the control module is used for receiving a test data packet, analyzing the test data packet, obtaining an identifier of the first equipment to be tested and a test command executed by the first equipment to be tested, determining a first connecting channel from a plurality of connecting channels according to the identifier of the first equipment to be tested, and sending the test command to the first connecting channel;

and the plurality of connecting channels comprise the first connecting channel, and the first connecting channel sends the test command to the first device to be tested for execution.

2. The programmable device of claim 1, wherein the control module is further configured to receive and send test result data from the first connection channel.

3. The programmable device of claim 1, wherein the control module further comprises a memory controller to read correspondence data between a connection channel and a device under test from a memory, the control module to retrieve the correspondence data using an identification of the first device under test to determine the first connection channel.

4. The programmable device of claim 1, wherein the first device under test is an embedded processor, the test command being written into an instruction register or flash memory via a JTAG interface for reading and execution by the embedded processor.

5. The programmable device of claim 1, wherein the first device under test is an embedded system, and the test command is written to a flash memory of the embedded system via a JTAG interface for reading and execution by an embedded processor in the embedded system.

6. The programmable device of claim 1, wherein the control module receives the test data packet via an interface type of one of:

PCIe interface, USB interface, UART interface.

7. The programmable device of claim 1, wherein the test data packet includes an identification of a plurality of first devices under test and a plurality of test commands to be executed by the first devices under test.

8. The programmable device of claim 1, wherein the plurality of devices under test are virtual devices built by hardware programming through programmable components provided by the programmable device, or,

the equipment to be tested is a plurality of entity equipment and is connected with the entity equipment through the programmable equipment.

9. The programmable device of claim 8, wherein the plurality of connection channels are implemented as one or more programmable devices of an AXI bus, an APB bus, a universal asynchronous receiver transmitter, and a serial peripheral interface.

10. The programmable device of any one of claims 1 to 9, wherein the programmable device is an FPGA device.

11. A cloud system, comprising: the programmable device of any one of claims 1 to 10 and a cloud server deployed with a server program for receiving the test commands from a client program and organizing and sending the test data packets according to the test commands.

12. The cloud system of claim 11, wherein the server program is further configured to verify that a user issuing the test command has permission to operate the first device under test.

13. The cloud system of claim 11, wherein the server program is further configured to organize multiple test commands in the same test data packet.

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