CN113880043A - Deep silicon etching morphology control method - Google Patents

Deep silicon etching morphology control method Download PDF

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Publication number
CN113880043A
CN113880043A CN202110955977.9A CN202110955977A CN113880043A CN 113880043 A CN113880043 A CN 113880043A CN 202110955977 A CN202110955977 A CN 202110955977A CN 113880043 A CN113880043 A CN 113880043A
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China
Prior art keywords
etching
silicon
oxide layer
silicon wafer
control method
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CN202110955977.9A
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Chinese (zh)
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徐伟
颜培力
张斌
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Shanghai Sirui Technology Co ltd
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Shanghai Sirui Technology Co ltd
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Priority to CN202110955977.9A priority Critical patent/CN113880043A/en
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00198—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising elements which are movable in relation to each other, e.g. comprising slidable or rotatable elements
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00134—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising flexible or deformable structures
    • B81C1/00182—Arrangements of deformable or non-deformable structures, e.g. membrane and cavity for use in a transducer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00444—Surface micromachining, i.e. structuring layers on the substrate
    • B81C1/00468—Releasing structures
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
    • B81C1/00619—Forming high aspect ratio structures having deep steep walls
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C3/00—Assembling of devices or systems from individually processed components
    • B81C3/001—Bonding of two components
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0221—Variable capacitors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00—Specific applications of microelectromechanical systems
    • B81B2201/02—Sensors
    • B81B2201/0228—Inertial sensors
    • B81B2201/0235—Accelerometers

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Pressure Sensors (AREA)
  • Micromachines (AREA)

Abstract

The invention discloses a deep silicon etching morphology control method, which comprises the following steps: step S1, adding a design structure of a release pattern on the layout structure of the silicon chip, and forming a cavity structure at a set position on the silicon chip; step S2, growing at least one oxide layer on the silicon wafer processed in the step S1; step S3, bonding the silicon slice processed in the step S2 with a bare silicon wafer, wherein the bare silicon wafer is positioned above the silicon slice; step S4, etching the bare silicon wafer through deep silicon etching and staying on an oxide layer; and step S5, etching the oxide layer at the bottom of the release pattern. The deep silicon etching morphology control method provided by the invention can realize no damage to the comb tooth structure on the premise of realizing the same structure morphology, and ensure the reliable performance of the device.

Description

Deep silicon etching morphology control method
Technical Field
The invention belongs to the technical field of semiconductors, relates to a deep silicon etching method, and particularly relates to a deep silicon etching morphology control method.
Background
The comb tooth structure capacitance type acceleration sensor is the most common acceleration sensor product which is also mature and popularized. The structure manufacturing process of the acceleration sensor can be well compatible with the conventional integrated circuit manufacturing process, and the sensitive movable shaft of the comb-tooth type acceleration sensor is parallel to the basal plane and is used for responding to the inertial motion in the horizontal (X/Y) direction.
Fig. 1 and fig. 2 disclose a general structure of a comb-tooth structured capacitive acceleration sensor; as shown in fig. 1 and 2, the movable sensitive mass element is composed of a tooth pivot 4, a movable tooth 3, a folded elastic beam 2, a fixed tooth 5 and a substrate. The movable comb teeth 3 are bilaterally and symmetrically manufactured on the tooth pivot 4 and horizontally extend to two sides of the tooth pivot, the other two ends of the comb teeth are provided with folding beams 2 similar to spring structures, the folding beams are fixed on the substrate, one end of each folding beam is fixedly connected to the tooth pivot, and the tooth pivot and the comb teeth are integrally fixed, so that the tooth pivot and the movable comb teeth are always arranged in a suspended parallel manner relative to the substrate and are similar to a template hung between two piles by a rope; the fixed teeth 5 are directly fixed on the base and are immovable, and the fixed teeth 5 are arranged on two sides of the tooth pivot and are symmetrical; each group of movable comb teeth is used as one electrode of the variable capacitor, and the fixed comb teeth is used as the other electrode of the variable capacitor.
The comb tooth structure capacitive acceleration sensor is usually manufactured by bonding a silicon wafer and another silicon wafer with a cavity structure into a whole in a wafer direct bonding mode. And then, etching the upper silicon layer above the cavity structure in a deep silicon etching mode to form a movable comb tooth structure. The idealized comb tooth structure morphology (vertical, flat) plays a crucial role in the performance of the capacitive acceleration sensor, as shown in fig. 3.
The comb tooth structure is divided into a movable structure and a fixed tooth. The width of the comb teeth and the distance between the comb teeth are designed fixed values. When the top silicon wafer is etched through in the deep silicon etching process, the movable structure comb teeth become movable structures. The etching rate characteristic of the wafer level etching process requires excessive etching time to ensure the etching effect of the whole wafer. The etching process still needs to be continued for a while after the comb teeth have been changed to a movable structure. During the over-etching time, the movable comb tooth structure will be inclined due to the self-gravity and the internal electrostatic force, so that the side surface of the movable comb tooth structure is exposed in the bombardment range of the etching plasma to cause the damage of the structure, as shown in fig. 4 to 7.
It can be seen from the design layout (as shown in fig. 8) and the scanning electron microscope fragment diagram that in the same structural region, different structures with the same size have normal appearance, and some have abnormal appearance, which are all movable structures. It is not possible to solve this problem from a wafer process perspective by process optimization, but rather it needs to be solved from a system level perspective.
The system-level solution can increase the width of the folding beam of the comb-tooth structure capacitive acceleration sensor, so that the rigidity of the whole structure is increased to avoid etching damage caused by the inclination of the movable structure. However, increasing the stiffness of the folded beam will result in a reduced sensitivity of the sensor, which is not an optimal solution for the overall system.
In view of the above, there is a need to design a new deep silicon etching method to overcome at least some of the above-mentioned defects of the existing deep silicon etching methods.
Disclosure of Invention
The invention provides a deep silicon etching morphology control method, which can realize no damage to a comb tooth structure on the premise of realizing the same structural morphology and ensure the reliable performance of a device.
In order to solve the technical problem, according to one aspect of the present invention, the following technical solutions are adopted:
a deep silicon etching morphology control method comprises the following steps:
step S1, adding a design structure of a release pattern on the layout structure of the silicon chip, and forming a cavity structure at a set position on the silicon chip; the layout structure comprises a normal bonding area and a corroded buffer area;
etching is not carried out at the position of the silicon chip with the release pattern, and at least one column is formed in the formed cavity structure;
step S2, growing at least one thermal oxidation layer on the silicon wafer processed in the step S1;
step S3, bonding the silicon slice processed in the step S2 with a bare silicon wafer, wherein the bare silicon wafer is positioned above the silicon slice; thinning the bare silicon wafer to a set thickness;
step S4, etching the bare silicon wafer through deep silicon etching and staying on the thermal oxidation layer; after etching is finished, forming a set comb tooth structure on the oxide layer;
step S5, the thermal oxide layer at the bottom of the release pattern is etched clean by using gaseous hydrofluoric acid VHF process.
According to another aspect of the invention, the following technical scheme is adopted: a deep silicon etching morphology control method comprises the following steps:
step S1, adding a design structure of a release pattern on the layout structure of the silicon chip, and forming a cavity structure at a set position on the silicon chip;
step S2, growing at least one oxide layer on the silicon wafer processed in the step S1;
step S3, bonding the silicon slice processed in the step S2 with a bare silicon wafer, wherein the bare silicon wafer is positioned above the silicon slice;
step S4, etching the bare silicon wafer through deep silicon etching and staying on an oxide layer;
and step S5, etching the oxide layer at the bottom of the release pattern.
In one embodiment of the present invention, in step S1, at least one pillar is formed in the cavity structure formed without etching the position of the release pattern on the silicon wafer.
In step S1, the layout structure includes a normal bonding region and an eroded buffer region.
In one embodiment of the present invention, in the step S2, the oxide layer is a thermal oxide layer.
As an embodiment of the present invention, the step S3 further includes: and thinning the bare silicon wafer to a set thickness.
In an embodiment of the invention, in step S4, after the etching is completed, a set comb tooth structure is formed on the oxide layer.
In one embodiment of the present invention, in step S5, the oxide layer at the bottom of the release pattern is etched clean by using a gaseous hf-hf process.
The invention has the beneficial effects that: the deep silicon etching morphology control method provided by the invention can realize no damage to the comb tooth structure on the premise of realizing the same structure morphology, and ensure the reliable performance of the device.
Drawings
Fig. 1 is a schematic top view of a conventional comb-type capacitive acceleration sensor.
Fig. 2 is a SEM scanning electron microscope image of a comb structure of a conventional comb-tooth type capacitive acceleration sensor.
Fig. 3 is a schematic cross-sectional view of a conventional comb-tooth type capacitive acceleration sensor.
FIG. 4 is a schematic diagram of an etching plasma bombarding a conventional comb-tooth type capacitive acceleration sensor.
FIG. 5 is a scanning electron microscope image of a conventional damaged comb tooth structure.
FIG. 6 is a scanning electron microscope image of a conventional damaged comb tooth structure (normal top topography).
FIG. 7 is a scanning electron microscope image of a conventional damaged comb tooth structure (bottom side damage).
FIG. 8 is a scanning electron micrograph of a prior art product used online.
FIG. 9 is a flowchart of a deep silicon etch profile control method in an embodiment of the invention.
Fig. 10 is a schematic diagram of step S1 according to an embodiment of the present invention.
Fig. 11 is a schematic diagram of step S2 according to an embodiment of the present invention.
Fig. 12 is a schematic diagram of step S3 according to an embodiment of the present invention.
Fig. 13 is a schematic diagram of step S4 according to an embodiment of the present invention.
Fig. 14 is a schematic diagram of step S5 according to an embodiment of the present invention.
Detailed Description
Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
For a further understanding of the invention, reference will now be made to the preferred embodiments of the invention by way of example, and it is to be understood that the description is intended to further illustrate features and advantages of the invention, and not to limit the scope of the claims.
The description in this section is for several exemplary embodiments only, and the present invention is not limited only to the scope of the embodiments described. It is within the scope of the present disclosure and protection that the same or similar prior art means and some features of the embodiments may be interchanged.
The steps in the embodiments in the specification are only expressed for convenience of description, and the implementation manner of the present application is not limited by the order of implementation of the steps.
The invention discloses a deep silicon etching morphology control method, and FIG. 9 is a flow chart of the deep silicon etching morphology control method in an embodiment of the invention; referring to fig. 9, the method for controlling deep silicon etching profile includes:
step S1, adding a design structure of the release pattern 11 to the layout structure of the silicon wafer 10, and forming a cavity structure at a set position on the silicon wafer 10, as shown in fig. 10.
In one embodiment, the layout structure includes a normal bonding region and an etched buffer region. At least one pillar is formed in the cavity structure formed without etching the silicon wafer 10 at the position having the release pattern 11.
Step S2, at least one oxide layer 20 is grown on the silicon wafer 11 processed in step S1, as shown in fig. 11.
In one embodiment, the oxide layer 20 is a thermal oxide layer; the thermal oxidation layer has the advantages of better material compactness and the like.
Step S3, bonding the silicon wafer 10 processed in step S2 and a bare silicon wafer 30, wherein the bare silicon wafer 30 is located above the silicon wafer 10. In one embodiment, step S3 further includes: the bare silicon wafer 30 is thinned to a set thickness as shown in fig. 12.
Step S4, the bare silicon wafer 30 is etched through and left on the oxide layer 20 by deep silicon etching, as shown in fig. 13. In one embodiment, after the etching is completed, a set comb structure is formed on the oxide layer.
Step S5, the oxide layer at the bottom of the release pattern is etched clean, as shown in fig. 14. In one embodiment, the thermal oxide layer at the bottom of the release pattern is etched clean using a gaseous hydrofluoric acid VHF process. The etch is isotropic and the thermal oxide layer is etched in both the horizontal and vertical directions. According to the invention, the design of the pillar structure is added in the cavity, and all silicon oxide on the top of the pillar is etched cleanly.
In one use scenario of the invention, the gaseous hydrofluoric acid VHF process is used to etch clean the thermal oxide layer at the bottom part through the position (release pattern) of the special cavity layer pattern etched by the deep silicon.
The gaseous hydrofluoric acid VHF process control requires that the thermal oxidation layer at the bottom of the release pattern is corroded cleanly, and meanwhile, the normal bonding area outside the release pattern is not influenced; and when the layout is designed, adding a corroded buffer area in the normal bonding area.
In summary, the deep silicon etching morphology control method provided by the invention can realize no damage to the comb tooth structure on the premise of realizing the same structure morphology, and ensure the reliable performance of the device.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The description and applications of the invention herein are illustrative and are not intended to limit the scope of the invention to the embodiments described above. Effects or advantages referred to in the embodiments may not be reflected in the embodiments due to interference of various factors, and the description of the effects or advantages is not intended to limit the embodiments. Variations and modifications of the embodiments disclosed herein are possible, and alternative and equivalent various components of the embodiments will be apparent to those skilled in the art. It will be clear to those skilled in the art that the present invention may be embodied in other forms, structures, arrangements, proportions, and with other components, materials, and parts, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention.

Claims (8)

1. A deep silicon etching morphology control method is characterized by comprising the following steps:
step S1, adding a design structure of a release pattern on the layout structure of the silicon chip, and forming a cavity structure at a set position on the silicon chip; the layout structure comprises a normal bonding area and a corroded buffer area;
etching is not carried out at the position of the silicon chip with the release pattern, and at least one column is formed in the formed cavity structure;
step S2, growing at least one thermal oxidation layer on the silicon wafer processed in the step S1;
step S3, bonding the silicon slice processed in the step S2 with a bare silicon wafer, wherein the bare silicon wafer is positioned above the silicon slice; thinning the bare silicon wafer to a set thickness;
step S4, etching the bare silicon wafer through deep silicon etching and staying on the thermal oxidation layer; after etching is finished, forming a set comb tooth structure on the oxide layer;
step S5, the thermal oxide layer at the bottom of the release pattern is etched clean by using gaseous hydrofluoric acid VHF process.
2. A deep silicon etching morphology control method is characterized by comprising the following steps:
step S1, adding a design structure of a release pattern on the layout structure of the silicon chip, and forming a cavity structure at a set position on the silicon chip;
step S2, growing at least one oxide layer on the silicon wafer processed in the step S1;
step S3, bonding the silicon slice processed in the step S2 with a bare silicon wafer, wherein the bare silicon wafer is positioned above the silicon slice;
step S4, etching the bare silicon wafer through deep silicon etching and staying on an oxide layer;
and step S5, etching the oxide layer at the bottom of the release pattern.
3. The deep silicon etching morphology control method according to claim 2, characterized in that:
in step S1, etching is not performed on the position of the silicon wafer having the release pattern, and at least one pillar is formed in the formed cavity structure.
4. The deep silicon etching morphology control method according to claim 2, characterized in that:
in step S1, the layout structure includes a normal bonding region and an eroded buffer region.
5. The deep silicon etching morphology control method according to claim 2, characterized in that:
in step S2, the oxide layer is a thermal oxide layer.
6. The deep silicon etching morphology control method according to claim 2, characterized in that:
the step S3 further includes: and thinning the bare silicon wafer to a set thickness.
7. The deep silicon etching morphology control method according to claim 2, characterized in that:
in step S4, after the etching is completed, a set comb structure is formed on the oxide layer.
8. The deep silicon etching morphology control method according to claim 2, characterized in that:
in step S5, the oxide layer at the bottom of the release pattern is etched clean by using a gaseous hydrofluoric acid VHF process.
CN202110955977.9A 2021-08-19 2021-08-19 Deep silicon etching morphology control method Pending CN113880043A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110955977.9A CN113880043A (en) 2021-08-19 2021-08-19 Deep silicon etching morphology control method

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Application Number Priority Date Filing Date Title
CN202110955977.9A CN113880043A (en) 2021-08-19 2021-08-19 Deep silicon etching morphology control method

Publications (1)

Publication Number Publication Date
CN113880043A true CN113880043A (en) 2022-01-04

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