CN113870908A - Memory chip and memory device - Google Patents

Abstract

A memory chip includes memory cell circuits, peripheral circuits, interconnect structures, and control logic circuits. The peripheral circuit is located under the memory unit circuit and is electrically connected with the memory unit circuit. The interconnect structure is located to the side of the memory cell circuitry. The control logic circuit is located under the interconnection structure, electrically connected with the interconnection structure and the peripheral circuit, and comprises a dynamic random access memory. In the memory device comprising the memory chip, the control logic circuit is integrated in the memory chip, and the memory device does not need to be provided with a controller chip, so that the manufacturing cost of the memory device can be reduced, the signal transmission speed is improved, the size of the memory device can be favorably miniaturized, more memory chips can be arranged in the saved space, and the storage space of the memory device is improved.

Description

Memory chip and memory device

Technical Field

The present disclosure relates to a memory chip and a memory device.

Background

Generally, in an electronic device including a memory chip, a controller chip is usually required to manage or control the memory chip, however, since the controller chip and the memory chip are separately provided, the cost of manufacturing the electronic device, such as the packaging cost, is increased, and further, since the electronic device includes a plurality of chips, it is not favorable for miniaturizing the memory device. However, in recent years, the trend of electronic devices is toward high integration, miniaturization, and high speed.

In view of the foregoing, there is a need to provide a new memory chip to overcome the above problems.

Disclosure of Invention

The present disclosure provides a Memory chip including a Memory cell circuit (Memory cell circuit), a peripheral circuit (peripheral circuit), an Interconnect structure (Interconnect structure), and a Control logic circuit (Control logic circuit). The peripheral circuit is located under the memory unit circuit and is electrically connected with the memory unit circuit. The interconnect structure is located to the side of the memory cell circuitry. The control logic circuit is disposed under the interconnect structure, electrically connects the interconnect structure and the peripheral circuit, and includes a Dynamic Random Access Memory (DRAM).

In some embodiments, the dram includes a capacitor array including a plurality of capacitors, each capacitor including a conductive pillar, an insulating layer covering a side surface and a bottom surface of the conductive pillar, and a conductive contact under the insulating layer.

In some embodiments, the control logic includes a Reduced instruction set Core (RISC Core) coupled to the Memory controller and the dram, and a Memory controller (Memory controller) electrically coupled to the peripheral circuit.

In some embodiments, the control logic further includes a Read-only memory (ROM) coupled to the reduced instruction set core.

In some embodiments, the control logic further includes an Error Correction Circuit (ECC) coupled to the memory controller.

In some embodiments, the control logic further includes an Interface circuit (Interface circuit) and a Power management circuit (Power management circuit), the Interface circuit coupled to the Power management circuit and the reduced instruction set core, and coupled to the interconnect structure.

In some embodiments, the peripheral circuit includes a Logic controller (Logic control), a Register (Register), a Decoder (Decoder), and an input and output controller (I/O control), the Register connecting the Logic controller and the I/O controller, and the Decoder connecting the Logic controller and the I/O controller.

In some embodiments, the memory chip further comprises a power management circuit, and the logic controller is connected to the power management circuit.

In some embodiments, the memory cell circuit is a non-volatile memory (NVM) cell circuit.

The present disclosure provides a memory device comprising at least two memory chips according to any of the foregoing embodiments and at least one bonding wire. These memory chips are arranged in a stack. At least one bond wire electrically connects the interconnect structures in the memory chips to each other.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are intended to provide further explanation of the present disclosure as claimed.

Drawings

The foregoing and other aspects, features, and advantages of the present disclosure will become more apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic diagram of an electronic device according to various embodiments of the present disclosure.

FIG. 2 is a schematic diagram of a memory chip according to various embodiments of the present disclosure.

FIG. 3 is a cross-sectional schematic diagram of a memory chip according to various embodiments of the present disclosure.

Fig. 4 and 5 are schematic diagrams of elements within an electronic device according to various embodiments of the present disclosure.

FIG. 6 is a schematic diagram of a memory chip according to various embodiments of the present disclosure.

Fig. 7 and 8 are schematic diagrams of electronic devices according to various embodiments of the present disclosure.

FIG. 9 is a schematic diagram of a memory device, according to various implementations of the present disclosure.

Detailed Description

In order to make the description of the present disclosure more complete and complete, reference is made to the accompanying drawings and the various embodiments described below, in which like reference numerals refer to the same or similar elements.

In the following description, numerous implementation details are set forth in order to provide a thorough understanding of the present disclosure. It should be understood, however, that these implementation details are not to be interpreted as limiting the disclosure. That is, in some embodiments of the disclosure, such implementation details are not necessary. In addition, for the sake of simplicity, some conventional structures and elements are shown in the drawings in a simple schematic manner.

The present disclosure provides an electronic device including a memory chip. FIG. 1 is a schematic diagram of an electronic device according to various embodiments of the present disclosure. FIG. 2 is a schematic diagram of a memory chip according to various embodiments of the present disclosure.

As shown in fig. 1, the electronic apparatus 100 includes a Host (Host)110 and a memory device 120. The host 110 has a first connector 112. The memory device 120 includes a circuit board 124, a second connector 122, a memory chip 126, and bond wires 128. The second connector 122 and the memory chip 126 are disposed on the circuit board 124. The memory chip 126 is connected to the second connector 122 by a bonding wire 128. When the first connector 112 is connected to the second connector 122, the host 110 can read information from the memory chip 126 or write information into the memory chip 126. The host 110 includes a processor. In some embodiments, the memory chip 126 is a NAND gate memory chip (NAND Flash memory chip). In some embodiments, the memory device 120 may be applied to a Secure digital card (SD card) or a Solid-state drive (SSD). In some embodiments, the first connector 112 and the second connector 122 are Universal Serial Buses (USB).

As shown in fig. 2, the Memory chip 126 includes a semiconductor substrate S1, a Memory cell circuit (Memory cell circuit)126A, a peripheral circuit (peripheral circuit)126B, an Interconnect structure (Interconnect structure) 126C, and a Control logic circuit (Control logic circuit) 126D. The peripheral circuit 126B and the control logic circuit 126D are located on the semiconductor substrate S1. In other words, the peripheral circuit 126B and the control logic circuit 126D are manufactured and designed on the same semiconductor substrate S1. Therefore, it is advantageous to simplify the manufacturing process of the electronic device 100 shown in FIG. 1, and since the control logic 126D is integrated into the memory chip 126 and disposed under the memory unit circuit 126A, the control logic 126D can manage or control the memory unit circuit 126A, and the control logic 126D can receive commands, addresses and data from the host 110, store the information and transmit the information to the memory unit circuit 126A. Therefore, as in the electronic device 100 of fig. 1, a Controller chip (Controller chip) does not need to be provided, in other words, the electronic device 100 does not include a Controller chip, so that the cost of manufacturing the electronic device 100 can be reduced, and the size of the electronic device 100 can be advantageously reduced. The saved space can be provided with more memory chips, and the storage space of the memory can be further increased. Moreover, compared to the structure in which the transmission between the host and the memory chip is performed through the controller chip, the electronic device 100 can achieve a faster transmission speed due to the shorter transmission path between the control logic 126D and the peripheral circuit 126B of the present disclosure.

Referring to fig. 2, the peripheral circuit 126B is disposed below the memory unit circuit 126A and electrically connected to the memory unit circuit 126A. Interconnect structure 126C is located on side SW1 of memory cell circuit 126A. The control logic 126D is located under the interconnect structure 126C, and the control logic 126D is electrically connected to the interconnect structure 126C and the peripheral circuits 126B. Bond wires 128 extend from bond pads 130 on top of interconnect structure 126C. In some embodiments, the memory cell circuit 126A is a non-volatile memory (NVM) cell circuit, such as a memory cell circuit. In some embodiments, the memory cell circuit 126A is a three-dimensional NAND memory (3D NAND flash memory) cell circuit. The term "three-dimensional NAND memory" as used in this disclosure refers to a semiconductor device having transistors of memory cells connected in series in a vertical direction on a substrate placed in a horizontal direction, or referred to as a memory string, such as a NAND string, such that the memory string extends in the vertical direction relative to the substrate, and "vertical" refers to a horizontal surface perpendicular to the substrate. In some embodiments, the semiconductor substrate S1 is a silicon-containing substrate comprising silicon, silicon germanium, silicon carbide, silicon-on-insulator, germanium-on-insulator, glass, gallium nitride, gallium arsenide, and/or other suitable III-V compounds. In some embodiments, the semiconductor substrate S1 is a silicon substrate including monocrystalline silicon, polycrystalline silicon, or amorphous silicon.

As shown in FIG. 2, control logic 126D is located under interconnect structure 126C and memory cell circuit 126A, peripheral circuit 126B is located only under memory cell circuit 126A, and the interface between control logic 126D and peripheral circuit 126B is not aligned with the interface between memory cell circuit 126A and interconnect structure 126C. In other embodiments, the peripheral circuit 126B is located under the interconnect structure 126C and the memory cell circuit 126A, and the control logic circuit 126D is located only under the interconnect structure 126C.

FIG. 3 is a cross-sectional schematic diagram of a memory chip 126, according to various embodiments of the present disclosure. In some embodiments, control logic 126D includes Dynamic random-access memory (DRAM). In some embodiments, a dynamic random access memory includes a capacitor array including a plurality of capacitors. For simplicity, FIG. 3 only shows one of the capacitors C in the DRAM. The required number of capacitors C may be provided in the dram according to design requirements. The capacitor C includes a conductive pillar C1, an insulating layer I covering the side and bottom surfaces of the conductive pillar C1, and a conductive contact C2, the conductive contact C2 being located below the insulating layer I. In some embodiments, the upper surface of conductive pillar C1 is substantially coplanar with the upper surface of insulating layer I. In some embodiments, insulating layer I encapsulates all sides of conductive post C1. However, the capacitor structure of the present disclosure is not limited to the above. In addition, the control logic circuit 126D includes a plurality of transistors F1, such as Metal-oxide-semiconductor field-effect transistors (MOSFETs). For example, the MOSFET is a low voltage MOSFET or a high voltage MOSFET. The peripheral circuit 126B includes a plurality of transistors F2, F3. The transistors F2 and F3 are MOSFETs, for example. For example, transistor F2 is a high voltage MOSFET and transistor F3 is a low voltage MOSFET. In some embodiments, the source and drain of transistors F1, F2, F3 are N + or P +.

The memory cell circuit 126A includes a plurality of metal layers 310, a plurality of insulating layers 320, a semiconductor channel 330, a plurality of gate insulating layers 340, and a plurality of contact vias 350. The plurality of metal layers 310 and the plurality of insulating layers 320 are alternately stacked. A gate insulation layer 340 surrounds the semiconductor channel 330. In the memory chip 126, an area where the memory cell circuit 126A is provided is referred to as a memory cell. In some implementations, the memory cells of the present disclosure are NAND cells. In some embodiments, the semiconductor channel 330 is a silicon channel. Semiconductor channel 330 is further coupled to the source and drain regions to control the operation of memory cell circuitry 126A, such as reading, writing or erasing.

In some embodiments, the control logic 126D may further include other components, such as a reduced instruction set core, a memory controller, a read only memory, etc., which are not shown in FIG. 3 and are further described in FIG. 4 below.

FIG. 4 is a schematic diagram of elements within an electronic device 400 according to various embodiments of the present disclosure. The memory chip 126 includes a semiconductor substrate S1, a memory cell circuit 126A, a peripheral circuit 126B, an interconnect structure 126C, and a control logic circuit 126D.

The control logic 126D includes a dram 410, a Reduced instruction set Core (RISC Core)420 and a Memory controller (Memory controller)422, the RISC Core 420 is coupled to the Memory controller 422 and the dram 410, and the Memory controller 422 is electrically coupled to the peripheral circuit 126B. In some embodiments, the DRAM 410 includes a capacitor array including a plurality of capacitors, the structure of the capacitors is shown as capacitor C in FIG. 3. In some implementations, the memory controller 422 is a NAND controller.

In some embodiments, the control logic 126D also includes a Read-only memory (ROM) 430, the ROM 430 coupled to the reduced instruction set core 420.

In some embodiments, the control logic 126D further includes an Error Correction Circuit (ECC) 432, and the ECC 432 is coupled to the memory controller 422.

In some embodiments, the control logic 126D further includes an Interface circuit (Interface circuit) IC1 and a Power management circuit (Power management circuit)440, the Interface circuit IC1 couples the Power management circuit 440 and the risc core 420, and couples the interconnect structure 126C. In some embodiments, the control logic 126D is electrically connected to the peripheral circuit 126B via the power management circuit 440. In some embodiments, the control logic 126D is electrically connected to the interconnect structure 126C via the interface circuit IC 1. In some embodiments, the control logic 126D also includes an interface circuit IC 2. The interface circuit IC2 is connected to the memory controller 422. The control logic 126D is electrically connected to the peripheral circuit 126B via the interface circuit IC 2.

In some embodiments, as shown in fig. 4, the peripheral circuit 126B includes a Logic controller (Logic control)450, a Register 460, a Decoder (Decoder)470, and an I/O controller (I/O control)480, wherein the Register 460 connects the Logic controller 450 and the I/O controller 480, and the Decoder 470 connects the Logic controller 450 and the I/O controller 480. In some embodiments, the logic controller 450 is coupled to the power management circuit 440.

In some embodiments, the peripheral circuit 126B further includes an interface circuit IC3, and the peripheral circuit 126B is electrically connected to the control logic 126D via the interface circuit IC 3. For example, the peripheral circuit 126B is electrically connected to the control logic 126D by the interface circuit IC2 connected to the interface circuit IC 3.

In some embodiments, the electronic device 400 further includes an interconnect IC4, and the peripheral circuit 126B is electrically connected to the memory cell circuit 126A via the interconnect IC 4.

In some implementations, the host 110 includes an interface circuit 114. The host 110 is connected to the interface circuit IC1 of the interconnect structure 126C via the interface circuit 114.

FIG. 5 is a schematic diagram of elements within an electronic device 500, according to various embodiments of the present disclosure. The difference between fig. 5 and fig. 4 is that the power management circuit 440 of fig. 4 is disposed in the control logic circuit 126D, and the power management circuit 540 of fig. 5 is disposed between the control logic circuit 126D and the peripheral circuit 126B. The power management circuit 440 of fig. 4 is closer to the other elements in the control logic 126D and faster in transmission speed than the power management circuit 540 does.

FIG. 6 is a schematic diagram of a memory chip 626 according to various embodiments of the present disclosure. As shown in FIG. 6, control logic 626D is located below interconnect structure 126C, peripheral circuit 626B is located below memory cell circuit 126A, and the interface between control logic 626D and peripheral circuit 626B is substantially aligned with the interface between memory cell circuit 126A and interconnect structure 126C. The difference between FIG. 6 and FIG. 2 is only the configuration of the peripheral circuits and the control logic.

FIG. 7 is a schematic diagram of an electronic device 700 according to various embodiments of the present disclosure. The electronic apparatus 700 includes a host 110 and a memory device 720. The host 110 has a first connector 112. The memory device 720 includes the circuit board 124, the second connector 122, the first memory chip 726A, the second memory chip 726B, and bond wires 728. The embodiments of the first memory chip 726A and the second memory chip 726B can refer to the embodiments of the memory chip 126, and are not described herein again. The difference between FIG. 7 and FIG. 1 is that the second connector 122 of the electronic device 100 of FIG. 1 is connected to one memory chip 126, and the second connector 122 of the electronic device 700 of FIG. 7 is connected to two memory chips, namely, a first memory chip 726A and a second memory chip 726B. However, the disclosure is not limited thereto, and the number of memory chips connected to the second connector 122 may be adjusted according to design requirements, such as three, four, five, six, etc.

FIG. 8 is a schematic diagram of an electronic device 800 according to various embodiments of the present disclosure. Electronic device 800 includes host 810, circuit board 824, memory chip 826, and bond wires 828. Host 810 is connected to memory chip 826 by bond wires 828. The host 810 can read information from the memory chip 826 or write information to the memory chip 826. Host 810 includes a processor.

FIG. 9 is a schematic diagram of a memory device 900 according to various implementations of the present disclosure. Memory device 900 includes at least two memory chips and at least one bond wire. These memory chips are arranged in a stack. At least one bond wire electrically connects the interconnect structures in the memory chips to each other. Such as memory chips 910 and 920, the memory chips 910 and 920 are stacked. At least one bond wire is, for example, bond wire 930. Bond wires 930 electrically connect the memory chips 910 and 920 to each other. The number of stacked memory chips and the number of bonding wires can be adjusted according to design requirements. The number of memory chips is, for example, two, three, four, five, six, etc.

The memory chip 910 includes a semiconductor substrate S2, a memory cell circuit 910A, a peripheral circuit 910B, an interconnect structure 910C, and a control logic circuit 910D. The peripheral circuit 910B and the control logic circuit 910D are located on the semiconductor substrate S2. The interconnect structure 910C is located on the control logic 910D. The memory cell circuit 910A is located on the peripheral circuit 910B. The memory chip 920 includes a semiconductor substrate S3, a memory cell circuit 920A, a peripheral circuit 920B, an interconnect structure 920C, and a control logic circuit 920D. The peripheral circuit 920B and the control logic circuit 920D are located on the semiconductor substrate S3. Interconnect structure 920C is located on control logic 920D. The memory cell circuit 920A is located on the peripheral circuit 920B. Bond wires 930 extend from bond pads 940 on the top of interconnect structure 910C and connect to bond pads 950 on the top of interconnect structure 920C, electrically connecting interconnect structures 910C and 920C to each other. The embodiments configured in the memory chips 910 and 920 can refer to the embodiments of the memory chip 126, and are not described herein again.

Referring to fig. 8 and 9, in some embodiments, a memory chip 826 of the electronic apparatus 800 may be replaced with a memory device 900. The memory chip 920 of the memory device 900 is connected to the host 810 by bond wires 828. In the memory device 900, since the peripheral circuit 910B and the control logic circuit 910D are manufactured and designed on the same semiconductor substrate S2 and the peripheral circuit 920B and the control logic circuit 920D are manufactured and designed on the same semiconductor substrate S3, it is advantageous to simplify the process of manufacturing the electronic apparatus 800. The control logic 910D is integrated into the memory chip 910 and can manage or control the memory cell circuits 910A. Control logic 910D receives commands, addresses, and data from host 810, stores the information, and transmits the information to memory unit circuit 910A. The control logic 920D is integrated into the memory chip 920 and can manage or control the memory cell circuitry 920A. Control logic 920D may receive commands, addresses, and data from host 810, store the information, and transmit the information to memory cell circuitry 920A. Therefore, the electronic device 800 does not need to be provided with a controller chip, in other words, the electronic device 800 does not contain a controller chip, so that the manufacturing cost can be reduced, and the size of the electronic device 800 can be reduced. The saved space can be provided with more memory chips, and the storage space of the memory can be further increased. Moreover, compared to the structure in which the host and the memory chip are transmitted through the controller chip, the electronic device 800 may achieve a faster transmission speed due to the shorter transmission path between the control logic circuit 910D and the peripheral circuit 910B and the shorter transmission path between the control logic circuit 920D and the peripheral circuit 920B of the present disclosure.

In summary, the present disclosure provides a memory chip and a memory device. The control logic circuit is integrated in the memory chip, therefore, the memory device does not need to be provided with a controller chip, thereby reducing the manufacturing cost of the memory device and improving the signal transmission speed, and being beneficial to the miniaturization of the volume of the memory device.

Although the present disclosure has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

It will be apparent to those skilled in the art that various modifications and variations can be made in the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the appended claims.

[ notation ] to show

100,400,500,700,800 electronic device

110,810 host computer

112 first connector

114, IC1, IC2, IC3, interface circuit

120 memory device

122 second connector

124,824 circuit board

126,626,826,910 memory chip

126A,910A,920A memory cell circuit

126B,626B,910B,920B peripheral circuits

126C,910C,920C interconnect structure

126D,626D,910D,920D control logic

128,728,828,930 bonding wire

130,940,950 bonding pad

310 metal layer

320 insulating layer

330 semiconductor channel

340 gate insulating layer

350 contact via

410 dynamic random access memory

Reduced instruction set core 420

422 memory controller

430 read-only memory

432 error correction circuit

440,540 Power management Circuit

450, logic controller

460 register

470 decoder

480 input and output (I/O) controller

720 memory device

726A first memory chip

726B second memory chip

900 memory device

C is capacitor

C1 conductive column

C2 conductive contact

F1,F2,F3:

I insulating layer

IC4 interconnect structure

S1, S2, S3 semiconductor substrate

SW1 side.

Claims (10)

1. A memory chip, comprising:

a memory cell circuit;

the peripheral circuit is positioned below the memory unit circuit and is electrically connected with the memory unit circuit;

an interconnect structure flanking the memory cell circuitry; and

and the control logic circuit is positioned below the interconnection structure, is electrically connected with the interconnection structure and the peripheral circuit and comprises a dynamic random access memory.

2. The memory chip of claim 1, wherein the dram comprises a capacitor array including a plurality of capacitors, each of the capacitors including a conductive pillar, an insulating layer covering a side surface and a lower surface of the conductive pillar, and a conductive contact under the insulating layer.

3. The memory chip of claim 1, wherein the control logic comprises a reduced instruction set core and a memory controller, the reduced instruction set core is coupled to the memory controller and the dram, and the memory controller is electrically coupled to the peripheral circuitry.

4. The memory chip of claim 3, wherein the control logic further comprises a read only memory, the read only memory coupled to the reduced instruction set core.

5. The memory chip of claim 3, wherein the control logic further comprises an error correction circuit, the error correction circuit coupled to the memory controller.

6. The memory chip of claim 3, wherein the control logic further comprises an interface circuit and a power management circuit, the interface circuit coupled to the power management circuit and the reduced instruction set core and coupled to the interconnect structure.

7. The memory chip of claim 1, wherein the peripheral circuit comprises a logic controller, a register, a decoder, and input and output controllers, the register connecting the logic controller and the input and output controllers, the decoder connecting the logic controller and the input and output controllers.

8. The memory chip of claim 7, further comprising a power management circuit, the logic controller coupled to the power management circuit.

9. The memory chip of claim 1, wherein the memory cell circuit is a non-volatile memory cell circuit.

10. A memory device, comprising:

at least two memory chips according to claim 1, the memory chips being arranged in a stack; and

at least one bonding wire electrically connects the interconnect structures in the memory chips to each other.

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