CN110880517A

CN110880517A - Semiconductor memory device with a memory cell having a plurality of memory cells

Info

Publication number: CN110880517A
Application number: CN201910786022.8A
Authority: CN
Inventors: 福住嘉晃; 青地英明; 松尾美惠; 吉井谦一郎; 进藤浩一郎; 河崎一茂; 佐贯朋也
Original assignee: Toshiba Memory Corp
Current assignee: Kioxia Corp
Priority date: 2018-09-04
Filing date: 2019-08-23
Publication date: 2020-03-13
Also published as: TWI724506B; TW202032764A; CN116600569A

Abstract

Embodiments described herein relate generally to a semiconductor memory device. According to one embodiment, an array chip includes a plurality of memory cells disposed three-dimensionally and a memory-side interconnect layer connected to the memory cells. The circuit chip includes a substrate, a control circuit disposed on the substrate, and a circuit-side interconnect layer disposed on the control circuit and connected to the control circuit. The circuit chip is attached to the array chip with the circuit-side interconnect layer facing the memory-side interconnect layer. The bonding metal is disposed between the memory-side interconnect layer and the circuit-side interconnect layer. The bonding metal is bonded to the memory-side interconnect layer and the circuit-side interconnect layer.

Description

Semiconductor memory device with a memory cell having a plurality of memory cells

Cross Reference to Related Applications

The present application is based on and claims priority from us partial continuation patent application No. 16/121,123, filed on day 4, 9, 2018 and us partial continuation patent application No. 16/409,637, filed on

day

10, 5, 2019; the foregoing U.S. continuation-in-part patent application is incorporated herein by reference in its entirety.

Technical Field

Embodiments described herein relate generally to a semiconductor memory device.

Background

A memory device having a three-dimensional structure has been proposed. In the memory device, a memory hole is formed in a stack body including a plurality of electrode layers stacked via an insulating layer. The electrode layer serves as a control gate layer in the memory cell. A silicon body serving as a channel is provided on the sidewall of the memory hole via the charge storage film.

To reduce the space factor of the control circuitry of a three-dimensional memory array in a chip, a technique for providing the control circuitry directly below the array is also proposed. For example, a configuration is proposed in which bit lines are connected to transistors formed on a substrate via contact plugs formed at end portions of the array and bit line extension layers provided on the lower side of the memory array.

Therefore, a fine interconnect layer equivalent to the bit line is also required under the array. The area around the array is necessary to form deep contacts. Further, there is a problem in that, for example, the bit line is substantially long, the bit line capacity increases, and the operation speed is affected.

Disclosure of Invention

According to one embodiment, a semiconductor memory device includes an array chip, a circuit chip, a bonding metal, a pad, and an external connection electrode. The array chip includes a plurality of memory cells arranged three-dimensionally and a memory-side interconnect layer connected to the memory cells. The array chip does not include a substrate. The circuit chip includes a substrate, a control circuit disposed on the substrate, and a circuit-side interconnect layer disposed on the control circuit and connected to the control circuit. The circuit chip is attached to the array chip with the circuit-side interconnect layer facing the memory-side interconnect layer. The bonding metal is disposed between the memory-side interconnect layer and the circuit-side interconnect layer. The bonding metal is bonded to the memory-side interconnect layer and the circuit-side interconnect layer. The bonding pad is arranged in the array chip. The external connection electrode reaches the pad from a surface side of the array chip.

According to the embodiment, the reliability of the semiconductor memory device can be improved.

Drawings

Fig. 1 is a schematic cross-sectional view of a semiconductor memory device of a first embodiment;

fig. 2 is a schematic plan view showing a layout example of bonding metals of the semiconductor memory device of the first embodiment;

FIG. 3 is a schematic perspective view of a memory cell array of the first embodiment;

fig. 4 is a schematic cross-sectional view of a memory string of the first embodiment;

FIG. 5 is a schematic cross-sectional view of a memory cell of the first embodiment;

fig. 6 and 7 are schematic cross-sectional views showing a method for manufacturing the semiconductor memory device of the first embodiment;

fig. 8 is a schematic cross-sectional view of a semiconductor memory device of the first embodiment;

fig. 9 is a schematic cross-sectional view of a semiconductor memory device of the first embodiment;

fig. 10 is a schematic perspective view of a memory cell array of the first embodiment;

fig. 11 is a schematic cross-sectional view of a semiconductor memory device of the first embodiment;

fig. 12 is a schematic enlarged cross-sectional view of a wire bonding portion of the semiconductor memory device of the first embodiment;

fig. 13A and 13B are schematic enlarged sectional views of a wire bonding portion of the semiconductor memory device of the first embodiment;

fig. 14 is an SEM (scanning electron microscope) image of the semiconductor memory device of the first embodiment;

fig. 15 is a block diagram of a semiconductor memory device of the first embodiment;

fig. 16 is a schematic cross-sectional view of a semiconductor memory device of the first embodiment;

fig. 17 is a schematic plan view showing BGA (or LGA) pin assignment of the semiconductor memory device of the first embodiment;

fig. 18 is a schematic sectional view of a semiconductor memory system of the second embodiment;

fig. 19 is a schematic plan view of a control circuit chip of a combination of the semiconductor memory system of the second embodiment;

fig. 20 is a schematic diagram of a semiconductor memory device of a third embodiment;

fig. 21A and 21B are schematic plan views of the semiconductor memory device shown in fig. 20;

fig. 22A, 22B, 23A, 23B, 24A, and 24B are schematic diagrams of another example of a semiconductor memory device of the third embodiment;

fig. 25 is a schematic cross-sectional view of a circuit chip 700;

fig. 26 is a block diagram of a circuit chip 700;

fig. 27 and 28 are block diagrams of the stacked chip 901 shown in fig. 20;

fig. 29 and 30 are block diagrams of stacked chips shown in fig. 23A;

fig. 31 is a block diagram of the stacked chip 901 shown in fig. 23B;

FIG. 32 is a block diagram of the stacked chip 902 shown in FIG. 23B; and

fig. 33 is a schematic view of a modification of fig. 21A and 21B.

Detailed Description

The embodiments are described below with reference to the drawings. Note that in the drawings, the same components are denoted by the same reference numerals and symbols.

Fig. 1 is a schematic cross-sectional view of a semiconductor memory device of a first embodiment.

The semiconductor memory device of the first embodiment has a structure in which: in which an array chip 100 including a plurality of memory cells arranged three-dimensionally and a circuit chip 200 including a control circuit that controls writing, erasing, and reading of data of the memory cells are pasted together.

After the array wafer and the circuit wafer are pasted together wafer by wafer as described below, the wafer bonding body is cut and divided into chips.

First, the array chip 100 is described. The array chip 100 includes a memory cell array 1 of a three-dimensional structure.

Fig. 3 is a schematic perspective view of the memory cell array 1. Note that in fig. 3, an interlayer insulating layer, an insulating separation film, and the like are not illustrated in order to clearly illustrate the drawing.

In fig. 3, two directions orthogonal to each other are denoted as an X direction and a Y direction. A direction orthogonal to the X direction and the Y direction (XY plane) and in which the multilayer electrode layers WL are stacked is denoted as a Z direction (stacking direction).

The memory cell array 1 includes a plurality of memory strings MS. Fig. 4 is a schematic cross-sectional view of the memory string MS.

Fig. 4 shows a cross-section parallel to the YZ plane in fig. 3.

The memory cell array 1 includes a stacked body including a plurality of electrode layers WL and a plurality of insulating layers 40. The electrode layers WL and the insulating layers 40 are alternately stacked. The stack body is provided on the back gate BG serving as a lower gate layer. Note that the number of layers WL of the electrode layers shown in the drawing is an example. The number of layers of the electrode layers WL may be any number.

As shown below with reference to fig. 6, the back gate BG is provided on the first substrate 10 via the insulating

films

48 and 45. After the array wafer W1 and the circuit wafer W2 are pasted together, the first substrate is removed.

The back gate BG and the electrode layer WL are layers containing silicon as a main component. The back gate BG and the electrode layer WL contain, for example, boron as an impurity for imparting conductivity to the silicon layer. The electrode layer WL may contain a metal silicide. Alternatively, the electrode layer WL is a metal layer.

The insulating layer 40 mainly contains, for example, silicon oxide. For example, the insulating film 48 is a silicon oxide film, and the insulating film 45 is a silicon nitride film.

One memory string MS is formed in a U-shape, including a pair of columnar sections CL extending in the Z-direction and a connection section JP coupling respective lower ends of the pair of columnar sections CL. The columnar section CL is formed, for example, in a columnar or elliptical columnar shape, penetrates the stack body, and reaches the back gate BG.

The drain-side select gate SGD is disposed at an upper end portion of one of a pair of pillar sections CL in the U-shaped memory string MS. The source side select gate SGS is disposed at the other upper end portion. The drain-side select gate SGD and the source-side select gate SGS are disposed on the electrode layer WL of the top layer via an interlayer insulating layer 43.

The drain-side select gate SGD and the source-side select gate SGS are layers containing silicon as a main component. The drain-side select gate SGD and the source-side select gate SGS contain, for example, boron as an impurity for imparting conductivity to the silicon layer.

The drain-side select gate SGD and the source-side select gate SGS serving as the upper select gate and the back gate BG serving as the lower select gate are thicker than one electrode layer WL.

The drain-side select gate SGD and the source-side select gate SGS are separated in the Y direction by an insulating separation film 47. The stacked body under the drain-side select gate SGD and the stacked body under the source-side select gate SGS are separated in the Y direction by an insulating separation film 46. That is, the stacked body between the pair of pillar sections CL of the memory string MS is separated in the Y direction by the insulating

separation films

46 and 47.

On the source side select gate SGS, a source line (e.g., a metal film) SL is provided via an insulating layer 44. A plurality of bit lines (e.g., metal films) BL shown in fig. 1 are disposed on the drain-side select gate SGD and the source lines SL via an insulating layer 44. The bit line BL extends in the Y direction.

Fig. 5 is an enlarged schematic cross-sectional view of a portion of the column section CL.

The pillar section CL is formed in a U-shaped memory hole formed in a stacked body including a multilayered electrode layer WL, a multilayered insulating layer 40, and a back gate BG. In the memory hole, a channel body 20 is provided, which serves as a semiconductor body. The channel body 20 is, for example, a silicon film. The impurity concentration of the channel body 20 is lower than that of the electrode layer WL.

The memory film 30 is disposed between the inner wall of the storage hole and the channel body 20. The memory film 30 includes a barrier insulating film 35, a charge storage film 32, and a tunnel insulating film 31.

The barrier insulating film 35, the charge storage film 32, and the tunnel insulating film 31 are provided between the electrode layer WL and the channel body 20 in this order from the electrode layer WL side.

The channel body 20 is provided in a cylindrical shape extending in the stacking direction of the stacked body. The memory film 30 is disposed in a cylindrical shape to surround the outer circumferential surface of the channel body 20 while extending in the stacking direction of the stacked body. The electrode layer WL surrounds the channel body 20 via the memory film 30. The core insulating film 50 is provided inside the channel main body 20. The core insulating film 50 is, for example, a silicon oxide film.

The barrier insulating film 35 is in contact with the electrode layer WL. The tunnel insulating film 31 is in contact with the channel body 20. The charge storage film 32 is disposed between the barrier insulating film 35 and the tunnel insulating film 31.

The channel body 20 serves as a channel in the memory cell MC. The electrode layer WL serves as a control gate layer for the memory cell. The charge storage film 32 functions as a data memory layer that accumulates charges injected from the channel body 20. That is, the memory cell MC having a structure in which the control gate layer surrounds the channel is formed in the crossing portion of the channel body 20 and the electrode layer WL.

The semiconductor memory device of the first embodiment is a nonvolatile semiconductor memory device which can electrically freely perform erasing and writing of data and can retain stored contents even if power is turned off.

The memory cell MC is, for example, a charge trap type memory cell. The charge storage film 32 contains a large number of trapping sites that trap charge. The charge storage film 32 is, for example, a silicon nitride film.

The tunnel insulating film 31 functions as a potential barrier when charges are injected from the channel body 20 into the charge storage film 32 or when charges stored in the charge storage film 32 are diffused to the channel body 20. The tunnel insulating film 31 is, for example, a silicon oxide film.

Alternatively, as the tunnel insulating film, a stacked film (an ONO film) having a structure in which a silicon nitride film is sandwiched by a pair of silicon oxide films may be used. When the ONO film is used as the tunnel insulating film, an erasing operation can be performed in a low electric field as compared with a single-layer silicon oxide film.

The barrier insulating film 35 prevents the charges stored in the charge storage film 32 from diffusing to the electrode layer WL. The barrier insulating film 35 includes a capping film 34 disposed in contact with the electrode layer WL and a barrier film 33 disposed between the capping film 34 and the charge storage film 32.

The barrier film 33 is, for example, a silicon oxide film. The cap film 34 is a film having a dielectric constant higher than that of silicon oxide, and is, for example, a silicon nitride film. By providing such a cap film 34 in contact with the electrode layer WL, reverse tunneling electrons injected from the electrode layer WL can be suppressed during erasing. That is, by using a stacked film of a silicon oxide film and a silicon nitride film as the barrier insulating film 35, the charge blocking property can be improved.

As shown in fig. 3 and 4, the drain-side select transistor STD is provided at an upper end portion of one of a pair of pillar sections CL in the U-shaped memory string MS. The source side select transistor STS is disposed at the other upper end portion.

The memory cell MC, the drain side select transistor STD, and the source side select transistor STS are vertical transistors in which current flows in the stacking direction (Z direction) of the stacked body.

The drain-side select gate SGD serves as a gate electrode (control gate layer) of the drain-side select transistor STD. An insulating film 51 (fig. 4) serving as a gate layer insulating film of the drain-side select transistor STD is provided between the drain-side select gate SGD and the channel body 20. The channel body 20 of the drain-side select transistor STD is connected to the bit line BL above the drain-side select gate SGD.

The source side select gate SGS serves as a gate electrode (control gate layer) of the source side select transistor STS. An insulating film 52 (fig. 4) serving as a gate layer insulating film of the source side select transistor STS is provided between the source side select gate SGS and the channel body 20. The channel body 20 of the source side select transistor STS is connected to the source line SL above the source side select gate SGS.

The back gate transistor BGT is provided in the connection section JP of the memory string MS. The back gate BG serves as a gate electrode (control gate layer) of the back gate transistor BGT. The memory film 30 provided in the back gate BG functions as a gate layer insulating film of the back gate transistor BGT.

A plurality of memory cells MC including electrode layers WL as respective layers of the control gate layer are provided between the drain side select transistor STD and the back gate transistor BGT. Similarly, a plurality of memory cells MC including electrode layers WL as respective layers of the control gate layer are also provided between the back gate transistor BGT and the source side select transistor STS.

The plurality of memory cells MC, the drain side select transistor STD, the back gate transistor BGT, and the source side select transistor STS are connected in series by the channel body 20, and constitute one memory string MS in a U shape. The plurality of memory strings MS are arranged in the X direction and the Y direction, so that the plurality of memory cells MC are three-dimensionally arranged in the X direction, the Y direction, and the Z direction.

The electrode layer WL is divided into a plurality of blocks in the Y direction and extends in the X direction.

In fig. 1, a region of the end in the X direction in the memory cell array 1 is shown. A staircase structure section 96 of the electrode layer WL is formed at one end of the memory cell array region 81 where the plurality of memory cells MC are disposed.

In the stair structure section 96, the end portions in the X direction of the electrode layers WL of the respective layers are formed in a stair shape. In the stepped structure section 96, a plurality of contact plugs 61 connected to the electrode layers WL of the respective layers formed in a stepped shape are provided. The contact plug 61 is connected to the electrode layers WL of the respective layers in a stepped shape passing through the interlayer insulating layer 69.

In the stepped structure section 96, the back gate BG is connected to the contact plug 63. The select gate SG (drain side select gate SGD and source side select gate SGs) is connected to the contact plug 65.

The contact plug 61 connected to the electrode layer WL is connected to the word interconnect layer 62. The contact plug 63 connected to the back gate BG is connected to the back gate interconnect layer 64. The contact plug 65 connected to the select gate SG connects the select gate interconnect layer 66.

The word interconnect layer 62, the back gate interconnect layer 64, and the select gate interconnect layer 66 are disposed in the same layer. The source lines SL shown in fig. 3 are also disposed in the same layer as the word interconnect layer 62, the back gate interconnect layer 64, and the select gate interconnect layer 66.

The word interconnect layer 62, the back gate interconnect layer 64, the select gate interconnect layer 66, and the source lines SL are formed by patterning the same material layer (e.g., metal layer). Therefore, the word interconnect layer 62, the back gate interconnect layer 64, the select gate interconnect layer 66, and the source lines SL are simultaneously formed in the same layer and formed of the same material to the same thickness.

The word interconnect layer 62 is further connected to the surface level interconnect layer 73, which is formed on the bonding surface side of the circuit chip 200 of the array chip 100, via other plugs and interconnect layers.

The back gate interconnect layer 64, the select gate interconnect layer 66, and the source lines SL are also connected to the surface layer interconnect layer 73 via other plugs and interconnect layers.

The channel body 20 of the pillar section CL and the bit line BL are connected via a plug 67. Further, the bit line BL is connected to the surface layer interconnect layer 73 via other plugs and interconnect layers.

The array chip 100 includes a memory-side interconnect layer for electrically connecting the memory cell array 1 to the circuit chip 200. The memory-side interconnect layer is formed as a multilayer interconnect including a word interconnect layer 62, a back gate interconnect layer 64, a select gate interconnect layer 66, and a surface layer interconnect layer 73.

The surface-layer interconnect layer 73 is connected to the circuit-side interconnect layer 76 of the circuit chip 200 via the

bonding metals

74a and 74 b. The circuit chip 200 includes a substrate 5. The substrate 5 is, for example, a silicon substrate.

The control circuit is formed on a circuit forming surface (a surface facing the array chip 100 side) of the substrate 5. The control circuit is formed as a semiconductor integrated circuit including the transistor 77. The transistor 77 has a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) structure including, for example, a gate electrode 78 and source/drain regions. The source/drain regions of the MOSFET are connected to the circuit-side interconnect layer 76 via plugs 79.

The circuit-side interconnect layer 76 is formed as a multilayer interconnect on the circuit formation surface via the interlayer insulating film 80.

The

bonding metals

74a and 74b are disposed between the surface layer interconnect layer 73 of the array chip 100 and the uppermost interconnect layer (the top layer interconnect layer as viewed from the substrate 5) of the circuit-side interconnect layer 76 of the circuit chip 200. The

bonding metals

74a and 74b are, for example, copper or a copper alloy containing copper as a main component.

The surface layer interconnection layer 73 of the array chip 100 and the circuit side interconnection layer 76 of the top layer of the circuit chip 200 are bonded to the

bonding metals

74a and 74 b. An insulating film 75 is provided around the

bonding metals

74a and 74b between the array chip 100 and the circuit chip 200. The insulating film 75 is a resin film or an inorganic film.

The array chip 100 and the circuit chip 200 are pasted together via the

bonding metals

74a and 74b and the insulating film 75. The memory-side interconnect layer of the array chip 100 and the circuit-side interconnect layer 76 of the circuit chip 200 are electrically connected via

bonding metals

74a and 74 b.

Thus, the memory cell array 1 is connected to the control circuit of the circuit chip 200 via the storage-side interconnect layer, the

bonding metals

74a and 74b, and the circuit-side interconnect layer 76.

According to the first embodiment, the external connection electrode 71 is formed on the array chip 100 side. The pads 70 are disposed in a region closer to the ends than the stair-step structure section 96 in the array chip 100.

For example, in forming the word interconnect layer 62, the back gate interconnect layer 64, the select gate interconnect layer 66, and the source lines SL, the pads 70 are formed by patterning a metal layer (e.g., a tungsten layer). Therefore, the pad 70 is formed in the same layer as the word interconnect layer 62, the back gate interconnect layer 64, the select gate interconnect layer 66, and the source lines SL, and is formed of the same material to the same thickness.

The external connection pads 72 are provided on the surface of the array chip 100 (the surface on the opposite side of the bonding surface from the circuit chip 200). The external connection electrode 71 is disposed between the external connection pad 72 and the pad 70.

The pads 70 are electrically connected to the circuit-side interconnect layer 76 via a memory-side interconnect layer or via holes separately provided. Accordingly, the control circuit formed in the circuit chip 200 is electrically connected to the external connection pad 72 via the pad 70 and the external connection electrode 71. The external connection pads 72 may be connected to a mounting substrate or other chip via, for example, solder balls, metal bumps, or bonding wires.

A plurality of

bonding metals

74a and 74b are disposed in the bonding sections of the array chip 100 and the circuit chip 200. The plurality of

bonding metals

74a and 74b mainly include a plurality of bit line drawing sections 74a electrically connected to the bit line BL and a plurality of word line drawing sections 74b electrically connected to the electrode layer WL.

Fig. 2 is a schematic plan view showing the arrangement relationship of the bit line drawing section 74a and the word line drawing section 74 b.

The bit line take-out section 74a is disposed in a region overlapping the memory cell array region 81 in the stacking direction, in which a plurality of memory strings MS (a region below the memory cell array region 81 in fig. 1) are disposed.

The word line drawing section 74b is disposed in a region overlapping with a region in which the stair structure section 96, the external connection electrode 71, and the like are further formed outside different from the memory cell array region 81 in the stacking direction. In fig. 1, a plurality of word line drawing sections 74b are disposed in a region below the stair structure section 96 and a region below the external connection electrode 71 (pad 70).

A method for manufacturing the semiconductor memory device of the first embodiment is described with reference to fig. 6 and 7.

The components of the array chip 100 and the components of the circuit chip 200 are formed in a wafer state, respectively.

In FIG. 6, the array wafer W1 and the circuit wafer W2 are shown before they are bonded together.

The substrate 10 remains on the array wafer W1 prior to attachment. The back gate BG is formed on the substrate (e.g., silicon substrate) 10 via the silicon oxide film 48 and the silicon nitride film 45. Further, a stacked body including a multilayer electrode layer WL and a select gate SG is stacked on the back gate BG.

After the stacked body is formed, the memory string MS, the staircase structure section 96, and the like are formed. Further, a memory-side interconnect layer is formed. The pads 70 are also formed during the formation of the memory-side interconnect layer.

After the formation of the surface layer interconnect layer 73 of the memory-side interconnect layer, a first bonding metal 91 and a first insulating film 92 are formed on the bonding surface (surface on the opposite side of the substrate 10) of the array wafer W1. The first bonding metal 91 is bonded to the surface layer interconnection layer 73. The first insulating film 92 is formed between the first bonding metal 91 and the first bonding metal 91 (around the first bonding metal 91). The surface (bonding surface) of the first bonding metal 91 is exposed from the first insulating film 92.

The components of the circuit wafer W2 are formed on a different substrate (e.g., a silicon substrate) 5 from the substrate 10 of the array wafer W1.

After a control circuit (semiconductor integrated circuit) including the transistor 77 is formed on the surface of the substrate 5, the circuit-side interconnect layer 76 is formed via the interlayer insulating layer 80.

A second bonding metal 93 and a second insulating film 94 are formed on the bonding surface (the surface on the opposite side of the substrate 5) of the circuit wafer W2. The second bonding metal 93 is bonded to the circuit interconnect layer 76 of the top layer. The second insulating film 94 is formed between the second bonding metal 93 and the second bonding metal 93 (around the second bonding metal 93). The surface (bonding surface) of the second bonding metal 93 is exposed from the second insulating film 94.

The array wafer W1 and the circuit wafer W2 were bonded wafer by wafer with the surfaces on opposite sides of the

substrates

10 and 5 facing each other by applying mechanical pressure.

The first bonding metal 91 and the second bonding metal 93 are, for example, copper or a copper alloy. The first bonding metal 91 and the second bonding metal 93 are bonded to each other as an integrally bonded metal 74, as shown in fig. 7. The first insulating film 92 and the second insulating film 94 are integrally bonded to the insulating film 75.

After the array wafer W1 and the circuit wafer W2 are pasted together, the substrate 10 of the array wafer W1 is removed. For example, the entire substrate 10 is removed by wet etching using nitrohydrofluoric acid.

On the surface from which the substrate 10 is removed, the insulating films (the silicon oxide film 48 and the silicon nitride film 45) formed on the substrate 10 remain as passivation films protecting the surface of the array wafer W1 (the array chip 100).

After the removal of the substrate 10, a through hole 95 reaching the pad 70 is formed from the surface side of the removed substrate 10 (the surface of the silicon oxide film 48). In the through hole 95, as shown in fig. 1, the external connection electrode 71 is embedded.

Alternatively, the external connection electrode 71 may be formed on the bottom section of the via 95 (the upper surface of the pad 70) and the sidewall of the via 95 while leaving a space in the via 95.

In order to drive the memory cell array 1, a high voltage of, for example, about 20V is sometimes required. In order to maintain the breakdown voltage of the transistor 77 of the control circuit (CMOS circuit) (so as to extend the depletion layer), it is desirable to leave the substrate (silicon substrate) 5 having a thickness of about 10 to 20 μm on the circuit chip 200 side. The thick substrate 5 serves as a support body of the semiconductor memory device.

In connecting the control circuit to the external circuit, it is conceivable to form a through-silicon via (TSV) penetrating the substrate 5 from the rear surface side of the substrate 5 and connect the TSV to the circuit-side interconnect layer 76. However, the cost and processing time to etch the thick substrate 5 is large. Further, in order to prevent short-circuiting of the silicon substrate 5 and the via internal electrode, a process of forming an insulating film on the via sidewall is also required.

On the other hand, according to the first embodiment, the through-hole 95 (fig. 7) is formed on the side of the array chip 100 from which the substrate 10 is removed. Since the thickness of the array chip 100 is about several micrometers, a deep etching process for penetrating a substrate having a thickness of several tens of micrometers is not required. It is possible to reduce the cost.

By removing the substrate 10 of the array wafer W1 by wet etching, unlike removing the substrate by grinding, stress applied to the memory cell array 1 is not generated. Thus, yield and reliability are improved.

Methods for forming control circuitry on a substrate and forming an array of memory cells on the control circuitry are also contemplated. However, in some cases, a heating process of 900 ℃ or more is required to form the three-dimensional memory cell array 1. If the control circuit is formed below the cell array in advance, there is a concern about problems such as impurity diffusion of transistors and heat resistance of metal contacts.

Further, in accordance with the future increase in interface speed, it is desired to improve the performance of the transistor. It may also be necessary to form the control circuit using a process having low heat resistance in which a salicide or the like is used.

On the other hand, according to the first embodiment, since the array chip 100 including the memory cell array 1 and the circuit chip 200 including the control circuit are formed by separate wafer processes, high heat treatment of the memory cell array 1 does not affect the control circuit. Therefore, it is possible to form the memory cell array 1 and the control circuit in a highly reliable structure.

In a structure in which a control circuit and a memory cell array are sequentially formed on a substrate, bit lines are formed more to the upper side than a stacked body when viewed from the substrate. Therefore, in connecting the bit line to the control circuit, after the bit line is drawn out to the outer region of the memory cell array region via the interconnect layer formed on the bit line, the deep contact plug is connected to the control circuit on the substrate surface from the drawn-out interconnect layer. This may result in an increase in chip area due to the wiring area for the interconnect. There are also problems in that: the bit line is substantially long, the bit line capacity increases, and the operation speed is affected. The same problem exists with respect to the wiring of the electrode layer (word line).

On the other hand, according to the first embodiment, the side where the bit line BL, the source line SL, the word interconnect layer 62, and the like are formed is bonded to the circuit chip 200 via the

bonding metals

74a and 74 b. Therefore, the interconnection only needs to be led directly downward (toward the bonding surface side).

For example, as described with reference to fig. 2, the bit line drawing section 74a is not drawn out to the outside of (not disposed on) the memory cell array region 81, but is disposed in an overlapping region below the memory cell array region 81.

Therefore, it is possible to suppress an increase in the interconnect length and the interconnect formation region for connecting the bit line BL, the source line SL, the word interconnect layer 62, and the like to the control circuit, and to suppress an operation delay and an increase in the chip area.

As described above, according to the first embodiment, the capacity increase and the reliability improvement of the memory cell can be achieved by an inexpensive process. Furthermore, optimization and speed increase of the control circuit can be achieved.

The pad connected to the external connection electrode may be formed in the same layer as the back gate BG as shown in fig. 8.

Polysilicon is typically used in the back gate BG. Therefore, in order to reduce the resistance of the pad, it is desirable to stack a layer 110 containing a metal such as a metal silicide layer or a metal layer on the back gate BG.

A metal-containing layer 110 is formed on the substrate 10 via the insulating

films

48 and 45 in the wafer stage. The back gate BG is formed on the layer 110. The layer 110 containing the metal and the back gate BG is left by patterning as

pads

110 and 111 in a region further outside than the stepped structure section 96.

After removing the substrate 10, a through hole reaching the pad 110 is formed from the surface side of the array wafer W1. The external connection electrode 112 is formed in the through hole.

The via holes may be shallow compared to the structure shown in fig. 1 in which the pad and the word interconnect layer 62 and the like are formed in the same layer. Further reduction in cost and further improvement in yield can be achieved.

The pads are not limited to being formed in the array chip 100. As shown in fig. 9, a part of the circuit-side interconnect layer 76 of the circuit chip 200 may be used as the pad 122. For example, an interconnect layer of the top layer of the circuit-side interconnect layer 76 viewed from the substrate 5 is formed as the pad 122.

After the substrate 10 of the array wafer W1 is removed, a through hole reaching the pad 122 is formed in a region further outside than the stepped structure section 96 from the surface side of the array wafer W1. The external connection electrode 121 is formed in the through hole. The external connection electrode 121 is not connected to the circuit-side interconnect layer 76 via the memory-side interconnect layer.

Fig. 10 is a schematic perspective view of a memory cell array 2 of another example of the semiconductor memory device of the first embodiment. Note that in fig. 10, as in fig. 3, the insulating layer and the like are not shown in order to clearly show the drawing.

The source layer SL is disposed on the side of the bonding surface opposite to the circuit chip 200. A source side select gate (lower select gate layer) SGS is provided on the source layer SL via an insulating layer.

An insulating layer is disposed on the source-side select gate layer SGS. A stacked body obtained by alternately stacking a plurality of electrode layers WL and a plurality of insulating layers is disposed on the insulating layers.

When viewed from the source layer SL, the insulating layer is disposed on the electrode layer WL of the farthest layer. A drain-side select gate (upper select gate layer) SGD is provided on the insulating layer.

A columnar section CL extending in the Z direction is provided in the stack body. That is, the pillar section CL pierces the drain-side select gate SGD, the multilayer electrode layer WL, and the source-side select gate SGS. One end of the channel body 20 in the pillar section CL is connected to the bit line BL. The other end of the channel body 20 is connected to a source line SL.

The source line SL is formed on the substrate. A source side select gate SGS, a stacked body including a multilayer electrode layer WL, a drain side select gate SGD, and a bit line BL are sequentially formed on the source line SL. An array wafer containing a source line SL, a source side select gate SGS, a stacked body including a multilayer electrode layer WL, a drain side select gate SGD, and a bit line BL, the bit line BL side of which is opposite to the circuit wafer W2, is pasted to the circuit wafer W2.

After the pasting, the substrate is removed. A through hole is formed from the surface side from which the substrate is removed. An external connection electrode is formed in the through hole.

Fig. 11 is a schematic cross-sectional view of a first semiconductor memory device of the embodiment.

The through-hole 120 is provided in the array chip 100. The via 120 penetrates the array chip 100 and reaches the pad 122 of the circuit chip 200. The via 120 extends along the memory string MS and the pillar section CL. The pad 122 is exposed at the bottom of the via 120.

Fig. 12 is a schematic enlarged cross-sectional view of a wire bonding portion of the semiconductor memory device of the first embodiment. The sides of wire 500 and bump 500a are shown in fig. 12.

For example, as shown in fig. 12, the wire 500 is bonded to the pad 122 through the via 120. The wire 500 is, for example, an Au (gold) wire or an Ag (silver) wire. The bump 500a formed at the tip of the wire 500 is directly bonded to the pad 122. The upper surface of the array chip 100 is covered with a protective film 49. The protective film 49 is, for example, a resin film.

Fig. 13A and 13B are schematic enlarged sectional views of a wire bonding portion of the semiconductor memory device of the first embodiment. The sides of wire 500 and bump 500a are shown in fig. 13A and 13B.

In the example shown in fig. 13A, bump 500a is a stud bump having a plurality of bumps formed at the tip of wire 500. Stud bump 500a is bonded to pad 122 through via 120. The height of stud bump 500a is greater than the depth of via 120. In this example, the capillary holding the wire 500 may be located above the upper surface of the protective film 49. The capillary and the wire 500 do not contact the protective film 49 and the side wall of the through-hole 120 during the wire bonding process. This can reduce wire bonding failures.

In the example shown in fig. 13B, the conductive body 123 is disposed on the pad 122 inside the via 120. The conductive body 123 contacts the pad 122. The conductive body 123 is, for example, a Ni — Au alloy, and is formed by electroplating. On the conductive body 123, no pad is formed. A bump 500a formed at the tip of the wire 500 is bonded to the upper surface of the conductive body 123.

In the example shown in fig. 13B, the capillary holding the wire 500 may be located above the upper surface of the protective film 49. The capillary and the wire 500 do not contact the protective film 49 and the side wall of the through-hole 120 during the wire bonding process. This can reduce bonding failures.

As shown in fig. 6, the array wafer W1 is bonded to the circuit wafer W2. Then, after the substrate 10 of the array wafer W1 is removed, the via 120 is formed.

Fig. 14 is an SEM (scanning electron microscope) image of the semiconductor memory device of the first embodiment.

The semiconductor memory device shown in fig. 14 includes a plurality of semiconductor memory devices as shown in fig. 11 to 13B.

A plurality of semiconductor memory devices (or chips) 300 are mounted on a wiring substrate 600 with a wiring network (not shown) provided on the surface or inside of an insulating resin substrate. Each semiconductor memory chip 300 includes an array chip 100 and a circuit chip 200 bonded to the array chip 100, as shown in fig. 11 to 13B. The semiconductor memory chips 300 are stacked in a staircase configuration along at least one side of the semiconductor memory chips 300. The semiconductor memory chip 300 includes a plurality of pads 122 (vias 120) arranged along and at one side edge of the semiconductor memory chip 300. Each of the electrode pads 122 may be exposed for wire bonding. The wiring substrate 600 includes a plurality of electrodes 601. Each electrode 601 is connected to a pad 122 on a different semiconductor memory chip 300 through a wire 500.

Fig. 15 is a block diagram of a semiconductor memory device 300 of the first embodiment.

The semiconductor memory device 300 of the embodiment is connected to a controller (not shown in fig. 15). The controller receives instructions such as data write, data read, and data erase operations from a host device (not shown).

The controller issues commands in response to these instructions and transmits the commands to the semiconductor memory device 300. The semiconductor memory device 300 controls a data read operation, a data write operation, and a data erase operation by the received commands.

In fig. 15, some connections between the respective blocks are indicated by solid arrow lines, but the connections between the blocks are not limited thereto.

As shown, the semiconductor memory device 300 includes an array chip 100 and a circuit chip 200. The array chip 100 includes, for example, a memory cell array 1. The circuit chip 200 includes the remaining components, such as I/O control circuitry 210, logic control circuitry 211, status register 212, address register 213, command register 214, control circuitry 215, ready/busy circuitry 216, voltage generator 217, row decoder 219, sense amplifiers 220, data register 221, and column decoder 222.

The logic control circuit 211 receives, for example, a chip enable signal BCE-0, a command latch enable signal CLE-0, an address latch enable signal ALE-0, a write enable signal BWE-0, and read enable signals RE-0 and BRE-0. The logic control circuit 211 controls the I/O control circuit 210 and the control circuit 215 in response to the received signals.

The chip enable signal BCE-0 is a signal for enabling the semiconductor memory apparatus 300, and is set to a low level. The command latch enable signal CLE-0 is a signal indicating that the input/output signal I/O is a command, and is set to a high level. The address latch enable signal ALE-0 is a signal indicating that the input/output signal I/O is an address, and is set to a high level. The write enable signal BWE-0 is a signal for extracting a reception signal into the semiconductor memory apparatus 300 and is set to a low level whenever a command, an address, and data are received from the controller. Accordingly, a signal is extracted into the semiconductor memory apparatus 300 every time BWE-0 is switched. The read enable signals RE-0 and BRE-0 are signals for enabling the controller to read each data from the semiconductor memory device 300. For example, read enable signal BRE-0 is asserted low and read enable signal RE-0 is asserted high.

The I/O control circuit 210 controls input and output of 8-bit input/output signals I/O < O > to I/O <7>, which are transmitted and received between the controller and the semiconductor memory device 300 through data lines DQ0-0 to DQ 7-0.

More specifically, the I/O control circuit 210 includes an input circuit and an output circuit, and the input circuit receives command signals, address signals, and data and transfers them to the command register 214, the address register 213, and the data register 221. In addition, the output circuit transmits various data held by the semiconductor memory device 300 to the controller in response to an instruction from the controller.

The various data includes, for example, memory data, ID data, parameter information, and status information. The memory data is, for example, data stored in the data register 221. The ID data is unique identification information of the semiconductor memory device 300, such as a product number, a memory capacity, and an interface specification. The parameter information is information such as a set value of a read voltage in a read operation. The state information is, for example, information indicating the result of the write operation, or the like. Hereinafter, an operation of reading memory data from the data register 221 is referred to as "register read", an operation of reading ID data is referred to as "ID read", an operation of reading parameter information is referred to as "acquisition feature", and data output by the acquisition feature is referred to as "GF data".

The command register 214 temporarily stores command signals received from the controller through the I/O control circuit 210 and transmits the command signals to the control circuit 215.

The control circuit 215 controls the status register 212, the ready/busy circuit 216, the voltage generator 217, the row decoder 219, the sense amplifier 220, the data register 221, and the column decoder 222 in response to a command signal held by the command register 214, and performs a data read operation, a data write operation, and a data erase operation.

The status register 212 temporarily holds the status in, for example, a data read operation, a data write operation, and a data erase operation, and notifies the controller whether the operations have been completed normally.

The ready/busy circuit 216 transmits a ready/busy signal RY/BBY to the controller according to the operating condition of the control circuit 215. The ready/busy signal RY/BBY is a signal indicating whether the semiconductor memory device 300 is in a busy state (whether the semiconductor memory device 300 is in a state of not receiving a command from the controller or in a state of receiving a command from the controller) and is at a low level in the busy state.

The voltage generator 217 generates voltages necessary for a data read operation, a data write operation, and a data erase operation, and applies the voltages to the memory cell array 1, the row decoder 219, and the sense amplifier 220 through, for example, a driver (not shown).

The memory cell array 1 includes a plurality of transistors of the memory cells MC (as shown in fig. 4 and 5). For example, the transistor holds data corresponding to a threshold level.

The address register 213 temporarily holds address signals received from the controller via the I/O control circuit 210. The address register 213 then transmits the row address to a row decoder 219 and the column address to a column decoder 222.

For example, in a data write operation and a read operation, the row decoder 219 decodes a row address and selects a word line WL (electrode layer WL) according to the decoding result.

Then, the row decoder 219 applies an appropriate voltage to the word line WL.

For example, in a data write operation and a read operation, the column decoder 222 decodes a column address and selects a latch circuit in the data register 221 according to the decoding result.

The data register 221 includes a plurality of latch circuits (not shown). The latch circuits correspond to the respective bit lines BL and hold write data and read data. For example, in a data write operation, the data register 221 temporarily holds data received from the controller via the I/O control circuit 210. Also, for example, in a data read operation, the data register 221 temporarily holds data read by the sense amplifier 220 and transfers the data to the controller through the I/O control circuit 210.

In a data read operation, the sense amplifier 220 detects data read from a transistor connected to the selected word line WL to the bit line BL. In addition, in the data write operation, the sense amplifier 220 transmits write data to the transistor connected to the selected word line WL. Hereinafter, the data units read and written in bulk by the sense amplifiers 220 are referred to as "pages".

Fig. 16 is a schematic cross-sectional view 300 of the semiconductor memory device of the first embodiment.

The array chip 100 and the circuit chip 200 shown in fig. 16 are bonded to each other as shown in fig. 11. The array chip 100 and the control circuit chip 200 are stacked in the directions indicated by the arrows shown in fig. 16, respectively.

The array chip 100 and the circuit chip 200 are accommodated in a package 301. The package 301 is a Ball Grid Array (BGA) or Land Grid Array (LGA) package. A plurality of conductive balls (or pads) 302 are disposed on a lower surface of the package 301.

Fig. 17 shows a schematic plan view of BGA (or LGA) pin assignment the signal codes shown in fig. 17 correspond to the signal codes shown in fig. 15.

Fig. 18 is a schematic cross-sectional view of a semiconductor memory system 800 of the second embodiment.

The semiconductor memory system 800 shown in fig. 18 includes an array chip 100 and a combined control circuit chip 400 bonded to the array chip 100. The combined control circuit chip 400 will be described later. The array chip 100 and the combined control circuit chip 400 are stacked in the directions indicated by the arrows shown in fig. 18, respectively.

The array chip 100 and the combined control circuit chip 400 are housed in a package 801. The package 801 is a Ball Grid Array (BGA) or Land Grid Array (LGA) package. A plurality of conductive balls (or pads) 802 are disposed on a lower surface of the package 801.

Fig. 19 is a schematic plan view of a combined control circuit chip 400 of the semiconductor memory system of the second embodiment.

The combined control circuit chip 400 includes a control circuit 401 and a Solid State Drive (SSD) controller 402.

The control circuit 401 includes the I/O control circuit 210, the logic control circuit 211, the status register 212, the address register 213, the command register 214, the control circuit 215, the ready/busy circuit 216, the voltage generator 217, the row decoder 219, the sense amplifier 220, the data register 221, and the column decoder 222 shown in fig. 15.

SSD controller 402 contains Error Correction Codes (ECC), front-end interfaces, wear leveling and logical to physical conversion, and NAND back-end interfaces.

The combined control circuit chip 400 is formed on a single monolithic silicon die.

Fig. 20 is a schematic diagram of a semiconductor memory device of a third embodiment.

The semiconductor memory device includes a stacked device 901. The stacked apparatus 901 is mounted on the circuit board 600. The passive devices 603 are mounted on the circuit board 600. The passive device 603 is for example a chip capacitor. A plurality of conductive balls or pads 602 are disposed on the lower surface of the circuit board 600.

The stacked device 901 includes a circuit chip 700 and a plurality of array chips 100-2, 100-3, 100-4. The array chips 100-2, 100-3, 100-4 include the aforementioned memory cell array 1. The circuit chip 700 is a control chip including a combination of the memory cell array 1, the control circuit 401 shown in fig. 19, and the SSD controller 402 shown in fig. 19.

The array chip 100-2 is stacked on the circuit chip 700, the array chip 100-3 is stacked on the array chip 100-2, and the array chip 100-4 is stacked on the array chip 100-3.

Fig. 21A is a schematic plan view of the semiconductor memory device shown in fig. 20. In fig. 21A, the X direction is along one side of the circuit chip 700 and the plurality of array chips 100-2, 100-3, 1004, and the Y direction is perpendicular to the X direction.

The circuit chip 700 and the array chips 100-2, 100-3, 100-4 are stacked in a staircase configuration along the X-direction. The circuit chip 700 is shifted to the array chips 100-2, 100-3, 100-4 in the Y direction.

A plurality of pads 101 are disposed on end portions of the array chips 100-2, 100-3, 100-4. The end portion is formed in a stepped configuration. The pads 101 are arranged along the Y direction.

A plurality of pads 701 are disposed on end portions in the X direction of the circuit chip 700 and end portions in the Y direction of the circuit chip 700. The pads 701 disposed at the end portions in the X direction of the circuit chip 700 are arranged along the Y direction. The pads 701 disposed at the end portion in the Y direction of the circuit chip 700 are arranged along the X direction.

Each

pad

101, 701 is electrically connected to a pad formed on the circuit board 600 by a wire 500.

The number of pads of the circuit chip 700 including the memory cell array 1, the control circuit 401, and the SSD controller 402 is greater than the number of pads of the array chips 100-2, 100-3, 100-4. The pads 701 are arranged along both sides of the circuit chip 700. The circuit chip 700 is shifted to the array chips 100-2, 100-3, 100-4 in the X direction and the Y direction.

As shown in fig. 21B, the size in the Y direction of the circuit chip 700 may be larger than the size in the Y direction of the array chips 100-2, 100-3, 100-4.

As shown in fig. 22A, a plurality of conductive balls 702 may be disposed on the lower surface of the circuit chip 700. The circuit chip 700 is electrically connected to the circuit board 600 through the conductive balls 702.

As shown in fig. 22B, a plurality of conductive balls or bumps 102 may connect the circuit chip 700 and the array chip 100-2. The conductive balls or bumps 102 may connect the array chip 100-2 and the array chip 100-3. The conductive balls or bumps 102 may connect the array chip 100-3 and the array chip 100-4.

As shown in fig. 23A, a plurality of circuit chips 700-1, 700-2, 700-3, 700-4 may be stacked in a staircase configuration on a circuit board 600. Each circuit chip 700-1, 700-2, 700-3, 700-4 is a combined control circuit chip and includes a memory cell array 1, a control circuit 401, and an SSD controller 402.

As shown in fig. 23B, a plurality of stacked

chips

901, 902 may be stacked on the circuit board 600.

The stacked chip 901 includes a circuit chip 700-1, an array chip 100-2, an array chip 100-3, and an array chip 100-4 stacked in a staircase configuration. The stacked chip 902 includes a circuit chip 700-2, an array chip 100-6, an array chip 100-7, and an array chip 100-8 stacked in a staircase configuration.

Each of the circuit chip 700-1, the array chip 100-2, the array chip 100-3, and the array chip 100-4 of the stacked chip 901 includes a first end portion. The first end portion of the lower chip protrudes in the first direction compared to the first end portion of the upper chip. The first end portion is electrically connected to the circuit board 600 through the wire 500.

Each of the circuit chip 700-2, the array chip 100-6, the array chip 100-7, and the array chip 100-8 of the stacked chip 902 includes a second end portion. The second end portion of the lower chip protrudes in a second direction opposite to the first direction, compared to the second end portion of the upper chip. The second end portion is electrically connected to the circuit board 600 through the wire 500.

As shown in fig. 24A, the array chips 100-2, 100-3, 100-4 of the stacked chip 901 may be connected to each other by wires 500. The circuit chip 700-1 may be connected to the array chip 100-2 through wires 500. The circuit chip 700-1 may be connected to the circuit board 600 through the wires 500. The array chips 100-6, 100-7, 100-8 of the stacked chip 902 may be connected to each other by wires 500. The circuit chip 700-2 may be connected to the array chip 100-6 through wires 500. The circuit chip 700-2 may be connected to the circuit board 600 through the wires 500.

As shown in fig. 24B, the array chip 100-2 shown in fig. 24A may be replaced with a circuit chip 700-3. The array chip 100-3 shown in fig. 24A may be replaced with a circuit chip 700-4. The array chip 100-4 shown in fig. 24A may be replaced with a circuit chip 700-5. The array chip 100-6 shown in fig. 24A may be replaced with a circuit chip 700-6. The array chip 100-7 shown in fig. 24A may be replaced with a circuit chip 700-8.

Fig. 25 is a schematic cross-sectional view of a circuit chip 700. The same components as those in fig. 11 are denoted by the same reference numerals and symbols.

The circuit chip 700 includes an array chip 100 and a circuit chip (or CMOS chip) 200. The array chip 100 is bonded to the circuit chip 200 through the bonding metal 74 a.

The array chip 100 includes a memory cell array 1.

The circuit chip 200 includes a substrate 5, and a control circuit 401 and an SSD controller 402 provided on the substrate 5. Each of the control circuit 401 and the SSD controller 402 includes a plurality of transistors 77 and an interconnect layer 76.

The interconnect layer 76 of the control circuit 401 is electrically connected to the interconnect layer 73 of the array chip 100 through the bonding metal 74 a.

The control circuit 401 and the SSD controller 402 are electrically connected to each other through an interconnect layer of the circuit chip 200.

Fig. 26 is a block diagram of a circuit chip 700.

The circuit chip 700 includes an array chip 100, a control circuit 401, and an SSD controller 402. The control circuit 401 is connected to an input-output (I/O) portion of the array chip 100. SSD controller 402 is connected to external host system 900. The control circuit 401 and the SSD controller 402 are connected to each other via a data bus 910 and a control bus 920.

SSD controller 402 includes host IF (interface) 711, host IF controller 712, host command controller 713, wear leveling controller 714, NAND block manager 715, memory location manager 716, data buffer controller 718, data buffer 717, cryptographic module 719, and ECC (error correction code) processor 720.

Host IF 711 is connected to host system 900, data bus 910, and control bus 920. The host IF controller 712, the host command controller 713, the wear leveling controller 714, the NAND block manager 715, the memory location manager 716, the data buffer 717, the cryptographic module 719 and the ECC processor 720 are connected to the control bus 920. The data buffer controller 718, the cryptographic module 719 and the ECC processor 720 are connected to the data bus 910.

Host IF 711 is an interface such as Serial Advanced Technology Attachment (SATA), Serial Attached SCSI (SAS), and peripheral component interconnect express/non-volatile memory express (PCIe/NVMe).

The host IF controller 712 controls the host IF 711.

The host command controller 713 interprets a processing request or command (READ, WRITE) received from the host system 900 via the host IF 711 and controls another element in the storage device to fulfill the request.

The data buffer 717 temporarily stores data written from the host system 900 and data read from the NAND. The data buffer 717 is, for example, a memory (SRAM, DRAM) or a register. The memory is volatile or non-volatile.

The data buffer controller 718 manages a data buffer 717. The data buffer controller 718 manages the use of the data buffer 717 (e.g., data in use or free data). The data buffer controller 718 manages a correspondence relationship of which buffer is a data write in which area and which NAND.

The ECC processor 720 encodes data to be written to the NAND, decodes data read from the NAND, and detects and corrects errors.

The NAND block manager 715 manages the use of NAND blocks. The NAND block manager 715 also manages bad blocks.

The wear leveling controller 714 manages exhaustion. The wear leveling controller 714 monitors the entire NAND and controls so that the depletion of a particular block does not progress too much. The wear leveling controller 714 controls the handling of read disturb and data retention.

The memory location manager 716 translates so-called logical addresses between physical addresses. When an access between addresses of the NAND is requested, the memory location manager 716 converts the address specified by the host system 900. The memory location manager 716 determines to which NAND region WRITE data when a WRITE command is received from the host system 900.

The cryptographic module 719 performs various cryptographic processes on the data.

The control circuit 401 includes a power controller 721, a memory controller 725, an address register 722, a command register 723, a status register 724, a row decoder 726, a column decoder 727, a data cache 728, and a sense amplifier 729.

The power controller 721 is connected to the host system 900. A memory controller 725, address registers 722, command registers 723, and status registers 724 are connected to control bus 920. The column decoder 727 is connected to the data bus 910. A row decoder 726, a column decoder 727, a data cache 728, and a sense amplifier 729 are connected to the memory controller 725. The power controller 721, the row decoder 726, and the sense amplifier 729 are connected to the input/output of the array chip 100.

The row decoder 726 controls the potentials of the electrode layer WL, the drain-side select gate SGD, and the source-side select gate SGS of the memory cell array 1. The sense amplifier 729 reads and amplifies the potential of the bit line BL.

The data writing process is described below.

Memory controller 725 receives write requests from memory location manager 716. When the received write request cannot be immediately executed, the memory controller 725 records an address in the address register 722 and records a command in the command register 723.

When write processing is involved, the memory controller 725 notifies the data to be written in the data buffer 717. Data is read from the data buffer 717 and encrypted in the encryption module 719. Subsequently, the data is error-corrected in the ECC processor 720.

The encoded data is transferred to data cache 728 and waits until the write begins. After preparation, data is transferred from the data cache 728 to the array chip 100 and written to the memory cells.

After the write process, the memory controller 725 reflects the result in the status register 724.

Next, the data reading process is described below.

The memory location manager 716 instructs the memory controller 725 to read the data. When the received read request cannot be immediately executed, the memory controller 725 records an address in the address register 722 and records a command in the command register 723.

When a read process is involved, the sense amplifiers 729 read data from the memory cells of the array chip 100 and store the data in the data cache 728.

The memory controller 725 queries the data buffer 717 for the location in which the read data should be transferred. The data stored in the data cache 728 is transferred to the ECC processor 720 and ECC is performed on the data. The corrected data is decrypted in the cryptographic module 719. The decrypted data is stored in data buffer 717.

The memory controller 725 reflects the end of the read process in the status register 724. The host command controller 713 instructs the host IF controller 712 to transmit data. The data is then transferred from the data buffer 717 to the host system 900.

Fig. 27 is a block diagram of the stacked chip 901 shown in fig. 20.

The stacked chip 901 includes a circuit chip 700 and a plurality of array chips 100-2, 100-3, 100-4. The circuit chip 700 is a combined control circuit chip that includes the SSD controller 402, the array chip 100-1, and the control circuits 401-1, 401-2, 401-3, 401-4. The control circuits 401-1, 401-2, 401-3, 401-4 include the same components as the control circuit 401 described above.

The control circuit 401-1 is connected to the array chip 100-1. The control circuit 401-2 is connected to the array chip 100-2. The control circuit 401-3 is connected to the array chip 100-3. The control circuit 401-4 is connected to the array chip 100-4.

The array chips 100-1, 100-2, 100-3, 100-4 are connected to a power supply 15 through wires.

The control circuit 401-2 is connected to the array chip 100-2 through a wire or a Through Silicon Via (TSV). The control circuit 401-3 is connected to the array chip 100-3 through wires or TSVs. The control circuit 401-4 is connected to the array chip 100-4 through a wire or a TSV.

SSD controller 402 is connected to host system 900 by wires.

As shown in fig. 28, circuit chip 700 may contain a plurality of SSD controllers 402-1, 402-2, 402-3, 402-4.

SSD controller 402-1 is connected to control circuit 401-1. SSD controller 402-2 is connected to control circuit 401-2. The SSD controller 402-3 is connected to the control circuit 401-3. The SSD controller 402-4 is connected to the control circuit 401-4.

According to the structure of fig. 28, elements controlling each array chip 100-1, 100-2, 100-3, 100-4 are separated. This structure can improve performance compared to the structure of fig. 27.

The structure of fig. 27 can reduce the circuit area and power consumption as compared with the structure of fig. 28.

Fig. 29 is a block diagram of the stacked chip shown in fig. 23A.

The circuit chip 700-1 includes an SSD controller 402-1, a control circuit 401-1, and an array chip 100-1.

The circuit chip 700-2 includes an SSD controller 402-2, a control circuit 401-2, and an array chip 100-2.

The circuit chip 700-3 includes an SSD controller 402-3, a control circuit 401-3, and an array chip 100-3.

The circuit chip 700-4 includes an SSD controller 402-4, a control circuit 401-4, and an array chip 100-4.

SSD controllers 402-1, 402-2, 402-3, 402-4 are connected to host system 900 by wires.

According to the configuration of fig. 29, SSD controllers 402-1, 402-2, 402-3, 402-4 are wired or connected to host system 900.

Alternatively, as shown in FIG. 30, each of SSD controllers 402-1, 402-2, 402-3, 402-4 may be connected to host system 900 through separate interconnect lines.

Fig. 31 is a block diagram of the stacked chip 901 shown in fig. 23B.

Fig. 32 is a block diagram of the stacked chip 902 shown in fig. 23B.

As shown in fig. 31, a circuit chip 700-1 of the stacked chip 901 includes an SSD controller 402-1, control circuits 401-1, 401-2, 401-3, 401-4, and an array chip 100-1.

SSD controller 402-1 is connected to host system 900A.

As shown in FIG. 32, the circuit chip 700-2 of the stacked chip 902 includes an SSD controller 402-2, control circuits 401-5, 401-6, 401-7, 401-8, and an array chip 100-5.

SSD controller 402-2 is connected to host system 900B.

The control circuit 401-5 is connected to the array chip 100-5. The control circuit 401-6 is connected to the array chip 100-6. The control circuit 401-7 is connected to the array chip 100-7. The control circuit 401-8 is connected to the array chip 100-8.

The array chips 100-2, 100-3, 100-4, 100-6, 100-7, 100-8 are connected to a power supply 15 through wires.

SSD controller 402-1 and SSD controller 402-2 may be wired or connected to the same host system.

Fig. 33 is a schematic view of a modification of fig. 21A and 21B.

A plurality of pads 705 for NAND I/F are disposed at end portions of the circuit chip 700 in the X direction. The pad 705 for the NAND I/F is connected to the pad 101 of the array chips 100-2, 100-3, 100-4 through the wire 500.

A plurality of pads 706 for a host are disposed at an end portion in the Y direction of the circuit chip 700. The pads 706 for the host are connected to the pads of the circuit board 600 by wires 500.

According to the structure of fig. 33, the end portion (side) of the circuit chip 700 in which the pad 705 for the NAND I/F is disposed is different from the end portion (side) of the circuit chip 700 in which the pad 706 for the host is disposed. This structure can reduce the arrangement pitch and area of the pad 705 for the NAND I/F and the pad 706 for the host.

Since the array chips 100-2, 100-3, 100-4 are stacked in a stair configuration, end portions (sides) of the pads 101 where the array chips 100-2, 100-3, 100-4 are disposed are severely limited by the package size. This may limit the arrangement rule of the pads on the circuit board 600. In the structure of fig. 33, the end portion (side) of the pad 101 where the array chips 100-2, 100-3, 100-4 are disposed is different from the end portion (side) of the connection circuit board 600. This structure can be easily restricted according to the above-described rule.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

Claims

1. A semiconductor memory device, comprising:

an array chip including a plurality of memory cells arranged three-dimensionally and a memory-side interconnect layer connected to the memory cells, and not including a substrate;

a circuit chip including a substrate, a control circuit provided on the substrate, and a circuit-side interconnect layer provided on the control circuit and connected to the control circuit, the circuit chip being attached to the array chip with the circuit-side interconnect layer facing the memory-side interconnect layer;

a bonding metal disposed between and bonded to the memory-side interconnect layer and the circuit-side interconnect layer;

a pad disposed in the array chip; and

external connection electrodes reaching the pads from a surface side of the array chip.

2. The semiconductor memory device according to claim 1, wherein

The array chip includes:

a stack body including a plurality of electrode layers stacked via insulating layers;

a semiconductor body extending in the stacked body in a stacking direction of the stacked body;

a charge storage film disposed between the semiconductor body and the electrode layer;

a plurality of bit lines connected to end portions of the semiconductor body; and

a source line connected to another end portion of the semiconductor body.

3. The semiconductor memory device according to claim 2, wherein

The electrode layer is formed in a step shape at an end of a memory cell array region where the memory cells are arranged, and

the memory-side interconnect layer includes a word interconnect layer connected to the electrode layer formed in the step shape.

4. The semiconductor memory device according to claim 3, wherein

The bonding metal includes a plurality of bit line lead-out sections electrically connected to the bit lines, and

the bit line leading-out section is disposed in a region overlapping with the memory cell array region in the stacking direction.

5. The semiconductor memory device according to claim 3, wherein

The bonding metal includes a plurality of word line lead-out segments electrically connected to the word interconnect layer, and

the pad is disposed in a region overlapping with the word line lead-out section in the stacking direction.

6. The semiconductor memory device according to claim 2, wherein the pad is provided in the same layer as the source line and is formed of the same material as the source line.

7. The semiconductor memory device according to claim 3, wherein the pad is provided in the same layer as the word interconnect layer and is formed of the same material as the word interconnect layer.

8. The semiconductor memory device according to claim 2, wherein

A gate layer is provided in the stack body in a layer on an opposite side of the memory-side interconnect layer, and

the pad is formed in the same layer as the gate layer and is formed of the same material as the gate layer.

9. The semiconductor memory device according to claim 1, further comprising an insulating film provided around the bonding metal.

10. A semiconductor memory device, comprising:

a pad disposed in the circuit chip; and

11. The semiconductor memory device according to claim 10, wherein

The array chip includes:

a source line connected to another end portion of the semiconductor body.

12. The semiconductor memory device according to claim 11, wherein

13. The semiconductor memory device according to claim 12, wherein

14. The semiconductor memory device according to claim 10, wherein the pad is provided in the same layer as the circuit-side interconnect layer and is formed of the same material as the circuit-side interconnect layer.

15. The semiconductor memory device according to claim 10, further comprising an insulating film provided around the bonding metal.

16. A semiconductor memory device, comprising:

the circuit chip includes a pad, and

the array chip includes a via penetrating the array chip and reaching the pad.

17. The semiconductor memory device according to claim 16, wherein

Stacking a plurality of semiconductor memory chips each including the array chip, the circuit chip, and a bonding metal,

each of the semiconductor memory chips includes an end portion along one side of the semiconductor memory chip, and

a plurality of the pads and a plurality of the vias are arranged in the end portion along the one side.

18. The semiconductor memory device according to claim 16, wherein the circuit chip is a combined control circuit chip including the control circuit and a solid state drive controller.

19. A semiconductor memory device, comprising:

a circuit chip including a substrate, control circuitry disposed on the substrate, a solid state drive controller disposed on the substrate, and a circuit-side interconnect layer, the circuit chip being affixed to the array chip, wherein the circuit-side interconnect layer faces the memory-side interconnect layer; and

the control circuit is connected to the memory-side interconnect layer through the circuit-side interconnect layer and the bonding metal,

the control circuit is connected to the solid state drive controller through the circuit side interconnect layer.

20. The semiconductor memory device according to claim 19, wherein

The array chip includes a plurality of semiconductor bodies, a plurality of electrode layers facing the semiconductor bodies, and a plurality of bit lines connected to the semiconductor bodies,

the control circuit includes a row decoder that controls a potential of the electrode layer, and a sense amplifier that senses and amplifies a potential of the bit line.