CN113868988A

CN113868988A - Behavior level modeling method for millimeter wave phase-locked loop

Info

Publication number: CN113868988A
Application number: CN202111126955.8A
Authority: CN
Inventors: 唐路; 兰卓; 许书凝; 张有明; 唐旭升; 李伟
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2021-09-26
Filing date: 2021-09-26
Publication date: 2021-12-31

Abstract

The invention discloses a behavioral modeling method of a millimeter wave phase-locked loop, which researches the non-ideal characteristics and loop parameter optimization of a high-speed ADPLL (advanced digital phase locked Loop) by modeling the behavioral of the ADPLL in a time domain and combining a frequency domain model of intrinsic phase noise of a DCO (digital controlled oscillator) and explores a method for optimizing the loop performance. In addition, the invention adopts C programming language to realize the behavior level model and provides a novel DCO behavior level model, which directly embodies the quantization noise of DCO in the model realization and can more accurately simulate the expression of the quantization noise.

Description

Behavior level modeling method for millimeter wave phase-locked loop

Technical Field

The invention relates to the field of integrated circuit design, in particular to a behavior level modeling method of a millimeter wave phase-locked loop.

Background

Phase-locked loops have found extremely wide application in many fields, such as analog and digital communication fields and radio electronics, and in particular, various types of phase-locked loops are commonly used in modem and phase synchronization in digital communication. The adpll has shown advantages of small area, low power consumption, good system integration, and the like, which are particularly important for wireless communication devices. The method for modeling the circuit behavior level by using high-level programming languages such as MATLAB or C language has the advantages of greatly reducing loop simulation time, flexibly configuring a loop structure and the like, and is strong in transportability, independent of a specific simulation platform and more convenient in data processing.

In an article of K.Kundert, predictingthe Phase Noise and Jitter of PLL-Based Frequency Synthesizers, two methods for Predicting Phase Noise and time domain Jitter are introduced systematically, wherein one method is to establish a behavioral level model by using Verilog A, then add oscillator time domain Jitter modeled by using Gaussian white Noise, simulate the behavioral level of a Phase-locked loop, store the obtained periodic Jitter in a file LAB through a read-write file interface of the Verilog A, read and call a psd function through MAT software to estimate the Phase power spectral density of the Phase-locked loop, and finally obtain simulated Phase Noise data.

In the article "ADPLL design parameters determination through noise model integration" by Jiang B, Xia T: a loop parameter design method of ADPLL is introduced, wherein a noise mathematical model of each module in a loop is discussed and a noise transfer function of each module is obtained, so that the contribution of each module noise to loop phase noise is deduced; and then establishing a transfer function model of the whole loop, and obtaining parameter expressions corresponding to parameters such as loop locking time, loop bandwidth and the like by comparing with a standard expression of a second-order system, so that an available value range of the parameters such as a loop filter and the like can be obtained by restricting the value range of the expressions.

In patent CN101833603A, a sigma-delta fractional-N frequency synthesizer was modeled using the VHDL-AMS language and its performance was simulated with simulator ADMS. The modules of an oscillator, a phase frequency detector, a charge pump, a voltage-controlled oscillator, a filter, a frequency divider, a sigma-delta modulator and the like included in the frequency synthesizer are all subjected to line level modeling. Meanwhile, different jitter noise sources are modeled. The whole work will greatly help the rapid simulation of the frequency synthesizer, and the phase noise and other indexes of the system can be predicted accurately as early as possible in the top-down design. However, compared with the C language, the VHDL-AMS language has less advantages in terms of realization of a loop modeling, independence of a code on a platform, strong portability, convenience in realization of complex functions, subsequent processing of data generated by simulation, and the like.

Disclosure of Invention

The purpose of the invention is as follows: due to the fact that the novel behavior level modeling of the DCO is conducted, quantization noise of the DCO does not need to be added additionally; the intrinsic noise of the oscillator is added into the model by adopting a mode of converting frequency domain modeling into time domain dithering. Compared with the traditional modeling mode, the method can more remarkably reflect the characteristic that the DCO contributes to quantization noise in a loop, and is a more advanced ADPLL behavior-level modeling mode.

Meanwhile, the loop is modeled by the C language, codes are not realized by a platform, the portability is high, the complex functions are more conveniently realized, and the method has more advantages in the aspect of carrying out subsequent processing on data generated by simulation.

The technical scheme is as follows: the invention relates to a behavior level modeling method of a millimeter wave phase-locked loop, wherein the phase-locked loop comprises a DCO (digital data assistant);

the method includes modeling a behavioral level of the DCO as follows:

the DCO mathematical model was established as follows:

f_out＝f_osc+OTW_c·Step_c+OTW_m·Step_m+OTW_f·Step_f (1)

wherein OTW_c、OTW_m、OTW_fCoarse, medium and fine control words, Step, of the numerically controlled oscillator, respectively_c、Step_m、Step_fThe frequency steps of the coarse, medium and fine tuning control words are obtained by converting after simulating the tuning frequency range of the DCO transistor level circuit. Thus modelingThe quantization effect of the DCO is directly expressed, so that only discrete frequency points can be output, and the phenomenon that the frequency falls off along with the increase of the control words can be simulated because the coarse/fine tuning step length is smaller than the medium/fine tuning range (the medium/fine tuning range needs to cover the coarse/medium tuning step length).

Furthermore, the behavior modeling method of the millimeter wave phase-locked loop further comprises noise modeling of the DCO, specifically comprises quantization noise modeling of the DCO and intrinsic noise modeling of the DCO;

1) modeling quantization noise for DCO:

since the DCO can output only discrete frequency points, the DCO output frequency has a target frequency FCW · f in the actual ADPLL_refThe frequency is not equal to the condition that the DCO can output limited discrete frequency points, so that the output frequency of the DCO fluctuates between two or more discrete frequency points when the actual phase-locked loop is locked, and the arithmetic mean value of the frequency is equal to the target frequency.

For the quantization noise generated due to the limited frequency precision of DCO, the quantization noise can be modeled by uniformly distributed white noise in behavior level simulation, and the quantization noise can finally contribute 1/f to a system loop²Phase noise of (2).

2) The intrinsic noise of the DCO is modeled as follows:

the intrinsic noise of DCO includes two categories in behavioral modeling, namely, additive noise, which is also called drift, and non-additive noise, which is also called jitter.

Since the phase noise appears as jitter in the time domain, for the oscillator intrinsic noise of DCO, the intrinsic noise of DCO is converted into time domain jitter and added to the clock edge of the DCO output signal, specifically, the random number of jitter is added to the DCO period as formula (2),

PER[n]＝PER[n-1]+jitter[n]-jitter[n-1] (2)

PER [ n ] is the period of the output signal of the DCO at the nth time, and jitter [ n ] is the jitter value generated by the random number generator at the nth time;

and equation (3) describes the random number variation values generated by the random number generator in the jitter modeling:

wherein, T₀Indicating the period of the DCO output signal, L indicating the DCO at each ideal T₀Single-sided spectral density in the time-series jitter model of (1)₀Representing the DCO output signal frequency.

The jitter introduced by the clocks does not directly affect each other. Delta T_iWhich represents the time difference between the actual clock edge and the ideal clock edge at the ith instant, this difference can be regarded as the instantaneous jitter of the DCO output signal. Since the jitter can be seen as a set of random numbers independent of each other, it can be modeled as additive white gaussian noise. Jitter also appears as white noise in the frequency domain and constitutes the noise floor of the DCO phase noise.

Unlike jitter, drift is affected by all previous clock offsets at each timestamp, and this accumulated error over time can eventually lead to a-20 dB/dec slope in the DCO phase noise curve.

Adding the drift into a behavior level model of the DCO, specifically comprising the following steps:

the drift is represented by formula (4) in the DCO behavior level modeling, and formula (5) is a random number variation value generated by a random number generator in the drift modeling:

PER[n]＝PER[n-1]+wander[n] (4)

where wander [ n ] is the drift value generated by the random number generator at time n, and Δ f represents the frequency deviation of the phase noise.

Furthermore, when the DCO behavior level model is added in the drift or jitter for simulation, the simulation is realized by a mode of generating random numbers, the DCO noise modeling of the invention adopts a Box-Muller method to generate the random numbers of the drift and the jitter and adds the random numbers into the DCO period, thereby avoiding complex function call, being capable of conveniently generating the random numbers obeying Gaussian distribution, and having higher operation efficiency than a linear congruence method.

Further, the behavioral level modeling method of the millimeter wave phase-locked loop of the present invention further includes estimating a power spectral density of the loop phase noise to obtain the loop phase noise, specifically:

firstly, phase power spectrum density of an output signal is calculated by a period estimation method, and then phase noise is obtained by processing.

For power spectral density estimation of loop phase noise, the output signal phase noise of a phase locked loop is generally calculated by sampling the output signal and transforming the signal into the frequency domain using a fast fourier transform, but for the present invention, calculating the phase noise directly using a fourier transform is problematic: 1. because the working frequency of the phase-locked loop modeled by the subject is very high, more output points are available, and direct Fourier transform is difficult to perform; 2. according to the invention, the modeling of the DCO output signal is a digital square wave signal, so that excessive harmonic interference exists if the data of the output signal is directly subjected to Fourier transform, and a simple phase noise image cannot be obtained. The method that the phase power spectral density of an output signal is calculated by a period estimation method and then phase noise is obtained through subsequent processing is adopted, and compared with the method that the phase noise is directly calculated, the method that the phase power spectral density is calculated is easier and more efficient.

Has the advantages that: compared with the prior art, the invention has the following beneficial effects:

1) the DCO model directly expresses the quantization effect of DCO, so that only discrete frequency points can be output, and the phenomenon that the generated frequency falls off along with the increase of control words because the coarse/fine tuning step length is smaller than the medium/fine tuning range (the medium/fine tuning range needs to cover the coarse/medium tuning step length) can be simulated.

2) According to the DCO noise modeling method, the Box-Muller method is adopted to generate the random numbers of drifting and shaking, the random numbers are added into the DCO period, complex function calling is avoided, the random numbers which obey Gaussian distribution can be conveniently generated, and the operation efficiency is higher than that of a linear congruence method.

3) According to the power spectral density estimation of the loop phase noise, the method that the phase power spectral density of the output signal is calculated by using a period estimation method firstly and then the phase noise is obtained through subsequent processing is adopted, compared with the method that the phase noise is directly calculated, the method that the phase power spectral density is calculated is easier and more efficient.

Drawings

Fig. 1 is a diagram of the ADPLL loop architecture proposed by the present invention.

FIG. 2 is a behavioral level model diagram of the DCO of FIG. 1.

Fig. 3 is a diagram of the non-additive noise of the DCO of fig. 1.

Fig. 4 is a graph illustrating the cumulative noise of the DCO of fig. 1.

FIG. 5 is a z-domain model diagram of the DCO of FIG. 1.

FIG. 6 is a behavioral level model diagram of the AFC module of FIG. 1.

FIG. 7 is a comparison of the normal capture and hysteresis of the CKR clock of FIG. 1.

FIG. 8 is a z-domain model diagram of the DLF of FIG. 1.

Detailed Description

The technical scheme of the invention is explained in detail in the following with reference to the attached drawings.

The adpll Loop of the present invention is shown in fig. 1, and includes a variable Phase accumulator vpa (variable Phase accumulator), a reference Phase accumulator rpa (reference Phase accumulator), an automatic Frequency calibration module afc (auto Frequency calibration), a Digital Controlled Oscillator (DCO), a Digital Loop filter dlf (Digital Loop filter), a time-to-Digital converter tdc (time Digital converter), and a subtractor.

Wherein VPA and RPA are used for converting frequency information into phase information, and AFC is used for comparing the values of VPA and RPA; the DCO outputs a signal with a corresponding frequency according to the input multi-bit control word. When the loop starts to work, the frequency of a DCO output signal is quickly locked to a sub-band of a target frequency through an AFC module, the DCO output signal is divided by N through a frequency divider and then enters a TDC and a VPA respectively, the VPA is used for counting the integer part of the period of the CKV after the N is divided, and the TDC quantizes the decimal part of the CKV/N. The output of VPA and TDC is integrated, i.e. the phase value of the output clock CKV/N. The subtracter subtracts the reference phase from the output phase to obtain the error of the phase, and the error is sent to the DLF, and the DLF calculates a new DCO control word according to the phase error and sends the new DCO control word to the input end of the DCO. And slowly locking to the target frequency by adjusting the fine adjustment part of the DCO control word through the phase discrimination loop. The phase detection loop comprises a subtracter, an RPA, a VPA and a TDC. In fig. 1, the DCO output signal divides by N CKV.

A behavior level modeling method of a millimeter wave phase-locked loop comprises the following steps:

step 100, establishing a z-domain model of DCO:

the z-domain model of DCO is shown in fig. 5; for an analog or mixed digital-analog phase-locked loop, the transfer function of the voltage-controlled oscillator is shown in equation (6):

wherein K_VCOFor tuning gain of the voltage-controlled oscillator, it can be found that the transfer function of the voltage-controlled oscillator can be regarded as an integrator; the DCO has a similar function to the vco, and the main difference is that the two control signals are different in type, the former control signal is an analog voltage, and the latter control signal is a multi-bit digital level, so that the z-domain transfer function of the vco can be obtained by referring to the transfer function of the vco as shown in equation (7):

wherein K_DCOFor tuning gain of DCO, T_refIs the reference clock period.

Step 200, establishing a DCO behavior level model:

as shown in fig. 2, the DCO mathematical model is as follows:

f_out＝f_osc+OTW_c·Step_c+OTW_m·Step_m+OTW_f·Step_f (8)

wherein OTW_c、OTW_m、OTW_fCoarse, medium and fine control words, respectively, of the DCO, and Step_c、Step_m、Step_fThe frequency steps of the coarse, medium and fine tuning control words are obtained by converting after simulating the tuning frequency range of the DCO transistor level circuit.

Step 300, implementing an AFC module behavior level model:

the working flow of the AFC module is as shown in fig. 6, the AFC directly compares the VPA and RPA phases, because VPA is 12-bit output and RPA is 20-bit output, it needs to shift VPA output to the left by 8 bits, after comparing the phases, it is determined whether the coarse tuning control word OTWc has been calibrated or not through the AFC internal variable, if not, coarse tuning calibration is performed, if the coarse tuning control word OTWc has been calibrated, the AFC internal variable is rewritten to indicate that the coarse tuning has been calibrated and to check whether the middle tuning control word OTWm is calibrated or not, and the subsequent flow is similar to the coarse tuning.

After the coarse tuning control word OTWc and the middle tuning control word OTWm are calibrated, the AFC operation is completed, and the subsequent fine tuning calibration is completed by the subtractor, VPA, RPA and TDC.

The calibration algorithm of the coarse tuning control word OTWc and the middle tuning control word OTWm is implemented by a dichotomy, and the coarse tuning of the DCO is 4 bits and the middle tuning is 5 bits.

Step 400, the realization of the phase discrimination module and the decision algorithm:

the DCO output signal is divided by a frequency divider N and then respectively enters a TDC and a VPA, the VPA is used for counting the integer part of the period of the CKV after the N frequency division, and the TDC quantizes the decimal part of the CKV/N. The output of VPA and TDC is integrated, i.e. the phase value of the output clock CKV/N. The subtracter is used for subtracting the reference phase from the output phase to obtain a phase error, the phase error is sent to the DLF, and the DLF calculates a new DCO control word according to the phase error and sends the new DCO control word to the input end of the DCO.

Because various signals are transmitted in a digital domain in the ADPLL, and a digital code of phase information can be directly acquired, the ADPLL generally directly calculates a phase difference between a reference signal and a feedback signal by using a subtractor, wherein the reference signal is an RPA output signal, and the feedback signal is a DCO output signal after N frequency division, but because the RPA and the VPA have errors in phase calculation, a decision algorithm needs to be added to acquire effective phase information.

As shown in fig. 7(a), the CKR clock is normally captured; as shown in fig. 7(b), the CKR clock lags, and at this time, the phase estimation of CKV is biased.

The phase error calculation function is realized by using the subtracter, but because the working frequency of the phase-locked loop designed by the embodiment is higher, the frequency division of N needs to be carried out on the output signal of the DCO in order to enable the VPA to work normally, and the result of the high frequency division ratio is the high requirement on the frequency resolution of the counter, so the output of the counter needs to be processed in order to enable the taken counter value to be more accurate. The invention adopts a mode of increasing the counting period to improve the accuracy, namely, a larger counting value is obtained by increasing the counting window, and the relative error of the counter is reduced.

Step 500, implementing DLF:

and the subtracter subtracts the reference phase from the output phase to obtain a phase error, and the phase error is sent to the DLF, and the DLF calculates a new DCO control word according to the phase error and sends the new DCO control word to the input end of the DCO.

By using an infinite impulse response filter and a design in which the coefficients can be configured off-chip, the filter coefficients can be rewritten to the internal registers via the I2C interface. The adopted DLF structure is shown in FIG. 8, and the z-domain transfer function is as follows:

step 600, implementation of a frequency-to-phase converter:

two phase accumulators are designed, namely RPA and VPA, the phase accumulators are essentially counters, for the RPA, the clock is provided by a reference signal, and the numerical value of a phase-locked loop frequency control word FCW is accumulated in each reference signal period; for VPA, the clock signal is provided by the output signal of DCO, and 1 is added in each DCO output signal period, and in design, the subtractor and its subsequent processing module will terminate the change of DCO control word only when the difference between the values of the two phase accumulators reaches a stable value, so we can obtain the relationship shown in equation (10) by simple calculation:

f_out＝FCW·f_ref (10)

wherein f is_outFor the frequency of the DCO output signal, the pll frequency control word FCW is the control word of RPA, also known as the division ratio, f, of the ADPLL_refIs the reference signal frequency.

Step 700, establishing a DCO noise model:

establishing a DCO noise model specifically comprises modeling quantization noise of the DCO and modeling intrinsic noise of the DCO;

step 701, modeling quantization noise of DCO: modeling by uniformly distributed white noise, which ultimately contributes 1/f to the phase-locked loop²Phase noise of (2).

Step 702, the intrinsic noise of the DCO is modeled as follows:

As shown in fig. 3, the intrinsic noise of DCO is converted into time domain jitter and added to the clock edge of the DCO output signal, specifically, the random number of the jitter is added to the DCO period as equation (11),

PER[n]＝PER[n-1]+jitter[n]-jitter[n-1] (11)

and equation (12) describes the random number variation values generated by the random number generator in the jitter modeling:

as shown in fig. 4, which is a diagram of cumulative noise of DCO, equation (13) is a representation manner of drift in DCO behavioral level modeling, and equation (14) is a random number variation value generated by a random number generator in drift modeling:

PER[n]＝PER[n-1]+wander[n] (13)

When the DCO behavioral model is added for simulation in drifting or shaking, the simulation is realized by generating random numbers, and the DCO noise modeling of the invention adopts a Box-Muller method to generate the random numbers for drifting and shaking and add the random numbers into the DCO period.

Step 800, power spectral density estimation of loop phase noise:

compared with the method of directly calculating the phase noise, the method of calculating the phase power spectral density of the output signal by using the period estimation method and then obtaining the phase noise through subsequent processing is easier and more efficient.

Claims

1. A behavior level modeling method of a millimeter wave phase-locked loop is characterized in that the phase-locked loop comprises a Digital Controlled Oscillator (DCO);

the behavioral level modeling method of the phase-locked loop comprises the following steps of behavioral level modeling of DCO:

the DCO mathematical model was established as follows:

f_out＝f_osc+OTW_c·Step_c+OTW_m·Step_m+OTW_f·Step_f (1)

wherein OTW_c、OTW_m、OTW_fCoarse, medium and fine control words, Step, of the numerically controlled oscillator, respectively_c、Step_m、Step_fThe frequency steps of the control words are coarsely, neutrally and finely adjusted.

2. The behavioral level modeling method of the millimeter wave phase-locked loop according to claim 1, wherein the behavioral level modeling method of the loop further comprises noise modeling of DCO, specifically including quantization noise modeling of DCO and intrinsic noise modeling of DCO;

1) modeling quantization noise for DCO: modeling by uniformly distributed white noise, which ultimately contributes 1/f to the phase-locked loop²Phase noise of (2);

2) the intrinsic noise of the DCO is modeled as follows:

the intrinsic noise of DCO is converted into time domain jitter and added to the clock edge of the DCO output signal, specifically, the random number of the jitter is added to the DCO period according to the formula (2),

PER[n]＝PER[n-1]+jitter[n]-jitter[n-1] (2)

PER [ n ] is the period of DCO output signal at nth time, jitter [ n ] is the jitter value generated by the random number generator at nth time;

wherein, T₀Indicating the period of the DCO output signal, L indicating the DCO at each ideal T₀Single-sided spectral density in the time-series jitter model of (1)₀Representing the DCO output signal frequency;

the drift is added to the behavioral level model of the DCO, specifically,

equation (4) is a representation mode of drift in the DCO behavioral level modeling, and equation (5) is a random number variation value generated by a random number generator in the drift modeling:

PER[n]＝PER[n-1]+wander[n] (4)

3. The behavioral level modeling method of the millimeter wave phase-locked loop according to claim 2, characterized in that when adding a DCO behavioral level model for simulation in case of drift or jitter, the method is implemented by generating a random number, and the DCO noise modeling of the present invention uses a Box-Muller method to generate a random number for drift and jitter to add to the DCO cycle.

4. The behavioral level modeling method of a millimeter wave phase-locked loop according to claim 2, wherein the behavioral level modeling method of the loop further comprises obtaining the loop phase noise by estimating a power spectral density of the loop phase noise, and specifically comprises: firstly, phase power spectrum density of an output signal is calculated by a period estimation method, and then phase noise is obtained by processing.