CN113867924A

CN113867924A - Resource management method, device, processor and equipment

Info

Publication number: CN113867924A
Application number: CN202010610413.7A
Authority: CN
Inventors: 周罗青; 程宏才; 王俊捷
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-06-30
Filing date: 2020-06-30
Publication date: 2021-12-31

Abstract

A method for resource management in a device, the method comprising: detecting a state of a thread running on a first processor core; when the fact that the thread running on the first processor core meets the preset condition is detected, the first processor core is controlled to work in a low power consumption mode, wherein the working frequency of the first processor core when working in the low power consumption mode is smaller than a frequency threshold value, and therefore resource waste of the processor is reduced.

Description

Resource management method, device, processor and equipment

Technical Field

The present application relates to the field of communications, and in particular, to a method, an apparatus, a processor, and a device for resource management.

Background

A Central Processing Unit (CPU) of the server includes at least one processor core, each processor core may run at least one polling thread, each polling thread being bound to a shared memory in the server. The data generation module (such as a network card) of the server generates data and stores the data in the shared memory. Each polling thread bound with the shared memory can periodically detect whether the shared memory stores data, and if the shared memory stores data, the data is acquired and processed. At present, data does not exist in a shared memory all the time, but a polling thread bound with the shared memory constantly detects whether the data exists in the shared memory, so that more computing resources and power consumption of a processor are occupied, and the resource waste of the processor is caused.

Disclosure of Invention

The application provides a method and a device for resource management, which are used for reducing resource waste of a processor.

In a first aspect, the present application provides a resource management method, which is applied to a device including at least one processor core. In the method, a state of a thread running on a first processor core is detected, the first processor core being any one of the at least one processor core. When detecting that a thread running on the first processor core meets a preset condition, controlling the first processor core to work in a low power consumption mode, wherein the working frequency of the first processor core is smaller than a frequency threshold value when the first processor core works in the low power consumption mode. When the first processor core is controlled to work in the low power consumption mode, each thread running on the first processor core cannot occupy the computing resource, and the working frequency of the first processor core is smaller than the frequency threshold value, so that the power consumption of the first processor core is very low, the computing resource of a processor where the first processor core is located is saved, and the power consumption of the processor is reduced.

In one possible implementation, the preset condition includes that the states of the threads running on the first processor core are all suspended states. Therefore, the thread running on the first processor core is ensured not to be awakened for a long time, and the first processor core is ensured not to be awakened quickly after being controlled to work in the low power consumption mode.

In another possible implementation manner, the threads running on the first processor core include a first thread, the first thread has a binding relationship with a shared memory included in the device, the first thread is used to detect whether the shared memory stores data, and the shared memory is a memory space in a memory of the device. The state of the first thread is set to a suspend state when the first thread detects that the duration of the shared memory without data exceeds a first time threshold. When the first thread detects that the duration time of the shared memory without data exceeds a first time threshold, the first thread indicates that data cannot be stored in the shared memory for a long time, and after the first thread is set to be in a suspension state, the first thread releases occupied computing resources, so that the waste of the computing resources is avoided.

In another possible implementation manner, the manner of detecting the shared memory by the first thread is periodic detection or real-time detection.

In another possible implementation manner, the first processor core is controlled to work in the low power consumption mode under the condition that the duration that each thread on the first processor core is in the suspended state is detected to exceed the second time threshold. Therefore, the thread running on the first processor core is ensured not to be awakened for a long time, and the first processor core can be controlled to work in a low power consumption mode for a long time.

In another possible implementation manner, when it is detected that the duration of the second thread in the suspended state exceeds a second time threshold, the second thread is migrated to a second processor core, the second thread is any thread running on the first processor core, the second processor core is a processor core already operating in the low power consumption mode in the device, and the load of the second processor core is lower than the load threshold. The load of the second processor core is lower than the load threshold value, so that the number of other threads competing for the computing resources with the second thread can be reduced when the second thread is awakened, and the second thread can compete for the computing resources as soon as possible.

In another possible implementation manner, when the utilization rate of the first processor core is lower than the utilization rate threshold, the third thread is migrated to a third processor core, the third thread is a thread in a non-suspended state on the first processor core, the utilization rate of the first processor core is used for indicating the effective utilization rate of the computing resources of the first processor core, and the third processor core is a processor core in the device and working in a normal working mode. Therefore, each thread on the first processor core can be in a suspended state as soon as possible, and the first processor core is controlled to work in the low power consumption mode as soon as possible.

In another possible implementation, threads in a non-suspended state on a plurality of processor cores in the device are merged onto a portion of the plurality of processor cores. The processor core may be located on one or more processors, such that the thread in the non-suspended state may be centralized to the processor or processors, thereby enabling other processors in the device to be controlled to operate in a low power mode.

In another possible implementation manner, when there is data in the shared memory of the device, the first processor core is controlled to operate in a normal operating mode, and the state of the first thread is set to a normal operating state, where an operating frequency of the first processor core is greater than or equal to a frequency threshold when the first processor core operates in the normal operating mode. Thereby ensuring that the first thread can process the task normally.

In another possible implementation manner, the receiving device includes a notification command triggered by the data generation module, where the notification command is triggered when the data generation module stores data into the shared memory, the notification command includes an identifier of the shared memory, and the notification command includes a command indicating that data exists in the shared memory. The first thread can be awakened to process data immediately when the data exists in the shared memory.

In another possible implementation, the notification command includes at least one of a software signal and a hardware signal.

In another possible implementation, the device includes a processor core that is a virtual processor core or a physical processor core.

In a second aspect, the present application provides an apparatus for resource management, configured to perform the method of the first aspect or any one of the possible implementations of the first aspect. In particular, the apparatus comprises means for performing the method of the first aspect or any one of its possible implementations.

In a third aspect, the present application provides an apparatus for resource management, the apparatus comprising: a processor, a memory, and a communication interface. The processor, the memory and the communication interface can be connected through a bus system. The memory is configured to store one or more programs, and the processor is configured to execute the one or more programs in the memory, so that the detection apparatus performs the method of the first aspect or any possible implementation manner of the first aspect.

In a fourth aspect, the present application provides a processor comprising a processor core configured to perform the method of the first aspect or any possible implementation manner of the first aspect.

In a fifth aspect, the present application provides an apparatus comprising a processor, the processor comprising a processor core, the processor core being configured to perform the method of the first aspect or any possible implementation manner of the first aspect.

In a sixth aspect, the present application provides a computer-readable storage medium having program code stored therein, which when run on a computer, causes the computer to perform the method of the first aspect or any possible implementation manner of the first aspect.

In a seventh aspect, the present application provides a computer program product comprising program code, which, when run on a processor core comprised by a processor, causes the processor core to perform the first aspect or any possible implementation manner of the first aspect.

In an eighth aspect, the present application provides a chip, which includes a memory and a processor, where the memory is used to store a computer instruction, and the processor includes a processor core, and the processor core is used to call and execute the computer instruction from the memory device, so as to execute the method in the first aspect and any possible implementation manner of the first aspect.

The present application can further combine to provide more implementations on the basis of the implementations provided by the above aspects.

Drawings

Fig. 1 is a schematic diagram of a resource scheduling scenario provided in an embodiment of the present application;

FIG. 2 is a schematic structural diagram of an apparatus provided in an embodiment of the present application;

FIG. 3 is a schematic structural diagram of another apparatus provided in an embodiment of the present application;

FIG. 4 is a flowchart of a resource management method according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a migration thread provided by an embodiment of the present application;

FIG. 6 is a diagram illustrating a merged thread according to an embodiment of the present application;

fig. 7 is a schematic diagram of a data processing process of an audio/video conference provided in an embodiment of the present application;

fig. 8 is a schematic structural diagram of a resource management device according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of another apparatus provided in the embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

The method and the device are suitable for resource scheduling scenes including producers and consumers, the consumers and the shared memory are in a binding relationship, the shared memory can be shared between the producers and the consumers, and the producers and the consumers can read and write the shared memory. The consumer has a function of polling the shared memory, and the function of polling the shared memory means that the consumer periodically detects whether data exists in the shared memory.

The producer can store data using the shared memory, and when the consumer detects that there is data in the shared memory, the data is obtained and processed.

It should be noted that: in the scene, the producer does not store data into the shared memory all the time, and the producer stores the data into the shared memory according to the requirement of the upper application.

Alternatively, referring to fig. 1, the producer may also be referred to as a data producing module 1, and the consumer may be a thread 2, for example, the consumer may be a polling thread. The thread 2 and the shared memory 3 have a binding relationship, the thread 2 can periodically detect whether the shared memory 3 has data, the data generation module 1 acquires the data and stores the data into the shared memory 3, and the thread 2 acquires and processes the data when detecting the data from the shared memory 3.

Alternatively, the data generation module 1, the thread 2 and the shared memory 3 shown in fig. 1 may be located in a device, the shared memory 3 is a storage space in a memory of the device, and the shared memory 3 occupies a segment of a memory address in the memory. Thread 2 is bound to the shared memory 3, which means that thread 2 is bound to the segment of memory address, e.g., thread 2 is bound to the start address and the end address of the shared memory 3, and thread 2 can access the segment of memory address.

Optionally, the device may include one or more threads 2, and the memory of the device includes one or more shared memories 3. Each shared memory 3 may be bound to one or more threads 2 in the device. That is to say: the one or more threads 2 can each detect whether there is data in the shared memory 3.

Optionally, one thread 2 may be bound to one shared memory 3, or may be bound to a plurality of shared memories 3.

Optionally, the device is a physical device or a virtual device, for example, the device is a physical device such as a server or a network device, or the device is a virtual device such as a virtual machine or a container, and the network device may be a switch.

Optionally, in the case that the device is a physical device, the data generating module 1 may be a device with computing capability, such as a processor, a network card, or a process or thread running on the device. For example, when the data generating module 1 is a network card, the network card receives data and stores the data into a shared memory 3, the thread 2 bound to the shared memory 3 detects the shared memory 3, and when the data is detected from the shared memory 3, the data is acquired and processed.

Optionally, in a case that the device is a virtual device, that is, the device is a virtual machine or a container, and the data generation module may be a process or a thread running in the virtual machine or the container.

The device may comprise at least one data generation module 1, at least one shared memory 3, and at least one thread 2 bound to any one of the shared memories 3.

Referring to fig. 2, the apparatus includes at least one processor, each processor including at least one processor core. The threads in the device run on processor cores, one processor core may run one or more threads 2. For any one shared memory 3 included in the memory of the device, at least one thread 2 bound to the shared memory 3 may run on one processor core or may run on a different processor core. In case the at least one thread 2 runs on different processor cores, the different processor cores may be located on the same processor or on different processors.

For example, in fig. 2, the apparatus includes a first processor 4 and a second processor 5, the first processor 4 including two processor cores, which are a processor core 41 and a processor core 42, respectively. The second processor 5 comprises a processor core 51. Processor core 41 has thread 21 and thread 22 running thereon, processor core 42 has thread 23 and thread 24 running thereon, and processor core 51 has thread 25 and thread 26 running thereon.

Optionally, the six threads may be bound to different shared memories 3, or some of the six threads may be bound to one shared memory 3. For example, assume that the device includes three shared memories 3 in the memory, and thread 21, thread 22, and thread 23 are all bound to one of the shared memories 3, thread 24 and thread 25 are bound to another of the shared memories 3, and thread 26 is bound to the remaining one of the shared memories 3.

Referring to fig. 2, in the embodiment of the present application, a scheduling module 6 is added in the device, and for any one processor core in the device, the processor core is referred to as a first processor core for convenience of description. The scheduling module 6 detects the state of a thread running on the first processor core; and when detecting that the thread running on the first processor core meets the preset condition, controlling the first processor core to work in a low power consumption mode, wherein the working frequency of the first processor core is smaller than a frequency threshold value when the first processor core works in the low power consumption mode, so that the power consumption of the first processor is reduced. The detailed implementation process of detecting the first processor core and controlling the first processor core will be described in detail in the embodiment shown in fig. 4, and will not be described in detail here.

Optionally, the scheduling module 6 may run on a processor core of the device, in which case the scheduling module 6 is the processor core, or the scheduling module 6 may run on a processor core together with at least one thread in the device, in which case the scheduling module may be a thread or a process running on the processor core, etc.

Among them, it should be noted that: the processor core may be a physical processor core, for example, referring to fig. 2, the first processor 4 and the second processor 5 are both CPUs, and the processor core 41 and the processor core 42 included in the first processor 4 may be CPU cores, or, referring to fig. 3, the processor core may be a virtual physical processor core, but each virtual physical processor core may also run on one or more physical processor cores. For example, in fig. 3, the apparatus includes a virtual processor core 1, a virtual processor core 2, and a virtual processor core 3, the virtual processor core 1 running on the physical processor core 41, and the virtual processor core 2 and the virtual processor core 3 running on the physical processor core 42.

Referring to fig. 4, an embodiment of the present application provides a resource management method, which is applied to the device shown in fig. 2 or 3, where the device includes at least one processor core, and includes:

step 401: a state of a thread running on a first processor core, the first processor core being any one of the at least one processor core, is detected.

One or more threads may run on the first processor core, and for any one thread on the first processor core, the one thread is referred to as the first thread for convenience of description. The first thread has a polling function, and the first thread is bound with a shared memory, wherein the polling function means that the first thread periodically detects whether data exists in the shared memory bound with the first thread, and the shared memory is a storage space in the memory of the device.

The state of the first thread may be set by the first thread. Optionally, the setting of the state of the first thread itself may be:

and when the duration of continuously detecting that no data exists in the shared memory bound with the first thread reaches a first time threshold, the first thread sets the state of the first thread to be a suspended state.

Optionally, the first thread may periodically detect whether there is data in the shared memory bound thereto, or the first thread may detect whether there is data in the shared memory bound thereto in real time.

The first thread does not compete for computing resources on the first processing core after setting its state to the suspend state. While the first thread is in the non-suspended state, it will compete for computing resources on the first processor core.

Optionally, before the state of the first thread is set to the suspend state, when the first thread continuously detects that the time length of no data in the shared memory bound to the first thread reaches a third time threshold, a yielding operation (also referred to as yield operation) is performed to release the computing resource occupying the first processor core, so that the first processor core preferentially runs other threads, and the third time threshold is smaller than the first time threshold.

Optionally, when the first thread is in the non-suspended state, the first thread may detect, in real time or periodically, the shared nature bound to the first thread. The first thread needs to occupy the computing resource of the first processor core to detect the shared memory. After the first thread sets its own state to the suspend state, the first thread will not periodically detect the shared memory. The first processor core can release the computing resources occupied by the first thread, thereby saving the computing resources of the first processor core.

Optionally, when detecting that the first thread sets its own state as the suspend state, the scheduling module obtains the identifier of the first thread and the start time of the suspend state, and stores the identifier of the first thread and the start time of the suspend state in the corresponding relationship between the identifier of the thread and the start time of the suspend state.

For example, referring to fig. 2, assume that a thread 21 on a processor core 41 sets its state to a suspend state when the length of time that it continuously detects that there is no data in the shared memory bound to it reaches a first time threshold, assuming that the current time is t 1.

Accordingly, the scheduling module detects that the state of the thread 21 changes to the suspended state at time t1, obtains the ID1 and the suspended state start time t1 of the thread 21, and correspondingly stores the ID1 and the suspended state start time t1 of the thread 21 in the corresponding relationship between the identifier of the thread and the suspended state start time shown in table 1 below.

For another example, still referring to fig. 2, assume that thread 22 on processor core 1 sets its state to the suspend state when the length of time that it continuously detects that there is no data in the shared memory bound to it reaches a first time threshold, assuming that the current time is t 2.

Accordingly, the scheduling module detects that the state of the thread 22 changes to the suspended state at time t2, obtains the ID2 and the suspended state start time t2 of the thread 22, and correspondingly stores the ID2 and the suspended state start time t2 of the thread 22 in the corresponding relationship between the identifier of the thread and the suspended state start time shown in table 1 below.

TABLE 1

Identification of threads	Suspend state start time
		Identification ID1 of thread 21	t1
Identification ID2 of thread 22	t2
		……	……

The device comprises at least one thread with a polling function, wherein each thread is bound with a shared memory and is used for detecting the shared memory bound with the thread. Before performing step 401, for each thread, the thread registers an identification of the thread and an identification of shared memory bound to the thread in a scheduling module. And the scheduling module correspondingly stores the identifier of the thread and the identifier of the shared memory bound with the thread in the corresponding relation between the identifier of the thread and the identifier of the shared memory. Therefore, the correspondence between the identifier of the thread and the identifier of the shared memory stores the identifier of each thread in the device and the identifier of the shared memory bound to each thread.

For example, referring to FIG. 2, the thread 21 registers the ID1 of the thread 21 and the IM1 of the shared memory 1 bound to the thread 21 with the scheduling module, which saves the correspondence between the ID1 of the thread 21 and the IM1 of the shared memory 1 bound to the thread 21 to the correspondence between the identification of the thread and the identification of the shared memory as shown in Table 2 below.

Similarly, the scheduling module stores the correspondence between the ID2 of the thread 22 and the ID IM2 of the shared memory 2 bound to the thread 22, the correspondence between the ID3 of the thread 23 and the ID IM3 of the shared memory 3 bound to the thread 23, the correspondence between the ID4 of the thread 24 and the ID IM4 of the shared memory 4 bound to the thread 24, the correspondence between the ID5 of the thread 25 and the ID IM5 of the shared memory 5 bound to the thread 25, and the correspondence between the ID6 of the thread 26 and the ID IM6 of the shared memory 6 bound to the thread 26 in the correspondence between the ID of the thread and the ID of the shared memory shown in table 2 below.

TABLE 2

Identification of threads	Identification of shared memory
		Identification of threads 21ID1	Identification IM1 of shared memory 1
Identification ID2 of thread 22	Identification IM2 of shared memory 2
		Identification ID3 of thread 23	Identification IM3 of shared memory 3
Identification ID4 of thread 24	Identification IM4 of shared memory 4
		Identification ID5 of thread 25	Identification IM5 of shared memory 5
Identification ID6 of thread 26	Identification IM6 of shared memory 6

Optionally, the shared memory is a segment of storage space in the device memory, and the identifier stored in the shared memory may include a start address of the storage space, or include a start address and an end address of the storage space, and the like.

Optionally, before step 401 is executed, it is also possible to obtain an identifier of each processor core and an identifier of a thread running on each processor core in the device, and store the identifier of each processor core and the identifier of the thread on each processor core in a corresponding relationship between the identifier of the processor core and the identifier of the thread.

For example, referring to the example shown in fig. 2, the identifier IC1 of the processor core 41, the identifier ID1 of the thread 21 running on the processor core 41, and the identifier ID2 of the thread 22 are obtained, and the identifier IC1 of the processor core 41, the identifier ID1 of the thread 21 running on the processor core 41, and the identifier ID2 of the thread 22 are correspondingly stored in the correspondence relationship between the identifier of the processor core and the identifier of the thread as shown in table 3 below. Similarly, the identifier IC2 of the processor core 42, the identifier ID4 of the thread 24 running on the processor core 42, and the identifier ID5 of the thread 25, and the identifier IC3 of the processor core 51, the identifier ID5 of the thread 25 running on the processor core 51, and the identifier ID6 of the thread 26 are stored in correspondence with the identifier of the processor core and the identifier of the thread as shown in table 3 below.

TABLE 3

Step 402: and when detecting that the thread running on the first processor core meets the preset condition, controlling the first processor core to work in a low power consumption mode, wherein the working frequency of the first processor core is smaller than a frequency threshold value when the first processor core works in the low power consumption mode.

Optionally, the preset condition includes that the states of the threads running on the first processor core are all suspension states. That is, in step 402, when it is detected that the states of the threads running on the first processor core are all suspended states, the first processor core is controlled to operate in the low power consumption mode.

Because the first processor core works in the low power consumption mode, the working frequency of the first processor core is smaller than the frequency threshold value, and therefore the power consumption of the first processor core can be reduced. The frequency threshold may be preset according to actual service requirements, or preset according to empirical values, or may be determined according to statistical historical data. The frequency threshold is used for limiting the working frequency of the processor core in the low power consumption mode, so that the power consumption of the processor core in the low power consumption mode is lower than that in the normal working mode, and the purposes of reducing the power consumption of the whole processor and saving energy are achieved.

Optionally, the preset condition includes that a duration of time that each thread on the first processor core is in the suspended state exceeds a second time threshold. In step 402, the first processor core is controlled to operate in the low power consumption mode when the duration that each thread on the first processor core is in the suspended state is detected to exceed a second time threshold.

Optionally, in implementation, the identifier of each thread on the first processor core is obtained from the correspondence between the identifier of the processor core and the identifier of the thread according to the identifier of the first processor core. And inquiring the corresponding relation between the identifier of the thread and the starting time of the suspended state according to the identifier of each thread, and if the starting time of the suspended state corresponding to each thread is inquired, determining that the state of each thread on the first processor core is the suspended state. And acquiring the duration of each thread in the suspended state according to the current time and the suspended state starting time of each thread, and controlling the first processor core to work in a low power consumption mode under the condition that the duration of each thread in the suspended state exceeds a second time threshold.

For example, referring to fig. 2, taking the processor core 41 as an example, according to the identifier IC1 of the processor core 41, the identifier ID1 of the thread 21 and the identifier ID2 of the thread 22 running on the processor core 41 are obtained from the correspondence between the identifier of the processor core and the identifier of the thread shown in table 3. From the correspondence between the thread ID1 and the thread ID2 of the thread 21 and the suspend state start time shown in table 1, the suspend state start time of the thread 21 is t1, and the suspend state start time of the thread 2 is t 2. According to the current time t3, the suspended state starting time t1 of the thread 21 and the suspended state starting time t2 of the thread 22, the first duration of the suspended state of the thread 21 is t3-t1, and the second duration of the suspended state of the thread 22 is t3-t 2. Assuming that the first duration t3-t1 and the second duration t3-t2 both exceed the second time threshold, the processor core 41 is controlled to operate in the low power consumption mode.

Optionally, the mode for controlling the first processor core to operate in the low power consumption mode may be:

the scheduling module sends an instruction for entering low power consumption to the first processor core, and the first processor receives the instruction and works in a low power consumption mode.

Optionally, the first processor core turns off its own operating clock to implement operation in the low power consumption mode.

For example, assuming that the first processor core is an advanced reduced instruction set processor (ARM), the instruction entering low power consumption sent by the scheduling module to the first processor core is a wait for event (WFE) instruction. The first processor core receives the WFE instruction and closes the working clock of the first processor core.

Although the first processor core works in the low power consumption mode, the first processor core is still powered, so that the first processor core can be awakened in time when the first processor core needs to be awakened to work in the normal working mode.

Optionally, before controlling the first processor to operate in the low power consumption mode, the thread which is processed in the suspended state for a long time on the first processor core can be migrated to other processor cores which operate in the low power consumption mode and have low load.

When implemented: and when the duration that the second thread is in the suspended state is detected to exceed a second time threshold, migrating the second thread to a second processor core, wherein the second thread is any one thread included on the first processor core, the second processor core is a processor core which is operated in a low power consumption mode in the device, and the load of the second processor core is lower than a load threshold.

The first processor core and the second processor core may be located on the same processor or on different processors.

The load threshold may be preset according to actual service requirements, or preset according to empirical values, or may be determined according to statistical historical data.

Because the load of the second processor core is lower than the load threshold, after the second thread is transferred to the second processor core, after the second processor core and the second thread are awakened, the number of threads competing for the computing resource with the second thread is less, and the second thread can obtain the computing resource from the second processor core as soon as possible.

Optionally, after the second thread is migrated to the second processor core, the identifier of the first processor core corresponding to the second thread is updated to the identifier of the second processor in the correspondence between the identifier of the thread and the identifier of the processor core.

For example, still referring to fig. 2, assuming that processor core 42 has been operating in a low power mode, with thread 23 and thread 24 running on processor core 42, the load of processor core 42 is 2, less than load threshold 3. It is also assumed that the state of thread 21 on processor core 41 is a suspended state and that the duration of thread 21 in the suspended state exceeds a second time threshold. Therefore, referring to fig. 5, the thread 21 is migrated to the processor core 42, and the identifier IC1 of the processor core 41 corresponding to the thread 21 is updated to the identifier IC2 of the processor core 42 in the correspondence relationship between the identifier of the processor core and the identifier of the thread as shown in table 3, resulting in the correspondence relationship between the identifier of the processor core and the identifier of the thread as shown in table 4 below.

TABLE 4

Optionally, before controlling the first processor to operate in the low power consumption mode, the thread in the non-suspended state on the first processor core may be migrated to another processor core operating in the normal operating mode, and the thread in the suspended state on the first processor core is reserved, so that the threads on the first processor core are all the threads in the suspended state as soon as possible, and the first processor core is controlled to operate in the low power consumption mode as soon as possible. Optionally, when implemented:

and when the utilization rate of the first processor core is lower than a utilization rate threshold value, migrating a third thread to a third processor core, wherein the third thread is a thread in a non-suspended state on the first processor core, the utilization rate of the first processor core is used for indicating the effective utilization rate of the computing resources of the first processor core, and the third processor core is a processor core which works in a normal working mode in the equipment.

The first processor core and the third processor core may be located on the same processor or on different processors.

Optionally, the first processor core and the third processor core are located on different processors, and the third thread may be migrated to a third processor core on a different processor than the first processor. For the processor where the first processor core is located, each processor core on the processor can meet the condition of entering the low-power-consumption working mode as much as possible, so that the whole processor works in the low-power-consumption mode.

Optionally, when it is detected that the utilization rate of the first processor core is lower than the utilization rate threshold, according to the identifier of the first processor core, the identifier of each thread running on the first processor core is obtained from the correspondence between the identifier of the processor core and the identifier of the thread, the identifier of the thread existing in the correspondence between the identifier of the thread and the start time of the suspended state is removed from the identifier of each thread, and the threads corresponding to the remaining identifiers of each thread are all the threads in the non-suspended state on the first processor core.

Optionally, after the third thread is migrated to the third processor core, the identifier of the first processor core corresponding to the third thread is updated to the identifier of the third processor in the correspondence between the identifier of the thread and the identifier of the processor core.

Optionally, in step 402, for a plurality of processor cores in a normal operating state, threads in a non-suspended state on the plurality of processor cores may be merged onto a part of the plurality of processor cores. Therefore, more threads on the processor core can be in a suspended state, so that more processor cores can be controlled to work in a low power consumption mode.

Optionally, when implemented: determining a plurality of processor cores, wherein the plurality of processor cores all work in a normal working mode, and selecting a part of processor cores from the plurality of processor cores. The threads on the plurality of processor cores that are in the non-suspended state are migrated to a portion of the processor cores, which may include one or more processor cores, such that the threads on more processor cores are in the suspended state. When the remaining non-migrated threads on a certain processor core are in a suspended state, controlling the processor core to work in a low power consumption mode; or controlling the processor core to work in a low power consumption mode when the duration of the thread which is not migrated and is left on the processor core in the suspended state exceeds a second time threshold.

Alternatively, a processor core located on the same processor may be selected from the plurality of processor cores, so that the thread in the non-suspended state is migrated to the processor core included in one processor as much as possible. And enabling processor cores on other processors in the device to meet the condition of entering the low-power-consumption working mode, so that the other processors work in the low-power-consumption mode to reduce the power consumption of more processors.

For example, for the example shown in FIG. 2, assume that processor cores 41, 42, and 51 are all operating in a normal operating mode, with thread 21 on processor core 41 in a suspended state and thread 22 in a non-suspended state. Threads 23 and 24 on processor core 42 are both in a non-suspended state, and thread 25 on processor core 51 is in a suspended state, while thread 26 is in a non-suspended state. This allows merging of threads in the non-suspended state on the three processor cores. For example, referring to FIG. 6, thread 22 on processor core 41 and threads 23 and 24 on processor core 42 are migrated to processor core 51, i.e., the threads in the non-suspended state on the three processor cores are merged onto processor core 51. The processor cores 41 and 42 are then controlled to operate in the low power mode, thereby causing the first processor 4 to operate in the low power mode.

Optionally, when the first processor core is controlled to operate in the low power consumption mode, the record including the identifier of each thread running on the first processor core is also deleted from the correspondence between the identifier of the thread and the initial suspension time.

Optionally, when implemented: acquiring the identification of each thread running on the first processor core from the corresponding relation between the identification of the processor and the identification of the thread according to the identification of the first processor; and deleting the record comprising the acquired identifier of each thread from the corresponding relation between the identifier of each thread and the initial suspension time.

Optionally, it should be noted that: if the first processor core is a virtual processor core, the first processor core runs on a physical processor core and is controlled to work in a low power consumption mode, so that the power consumption of the first processor core is reduced, and the computing resources of the physical processor core can be saved.

Optionally, each virtual processor core running on the physical processor core operates in a low power consumption mode, and the physical processor core may also be controlled to operate in the low power consumption mode, so as to reduce power consumption of a processor core (also referred to as a physical core) where the virtual processor core is located.

Step 403: when data exists in the shared memory bound with the first thread, the first processor core is controlled to work in a normal working mode, and the state of the first thread is set to be a normal working state, wherein the working frequency of the first processor core is larger than or equal to a frequency threshold value when the first processor core works in the normal working mode.

Optionally, when a data generation module in the device stores data into the shared memory bound to the first thread, the data generation module triggers a notification command to the scheduling module, where the notification command includes an identifier of the shared memory.

Optionally, the notification command includes a command for indicating that data exists in the shared memory.

Optionally, the notification command includes at least one of a software signal and a hardware signal.

In step 403, the scheduling module needs to wake up the first processor core and the first thread on the first processor core in the low power mode. When implemented:

and the scheduling module receives the notification command, and determines that data exists in the shared memory corresponding to the identifier of the shared memory according to the identifier of the shared memory included in the notification command. And acquiring the identifier of the first thread bound with the shared memory from the identifier of the thread and the identifier of the shared memory according to the identifier of the shared memory. And acquiring the identifier of the first processor core where the first thread is located from the corresponding relation between the identifier of the processor core and the identifier of the thread according to the identifier of the first thread.

And the scheduling module determines whether the first processor core works in a low power consumption mode or not according to the identifier of the first processor core. And when the first processor core works in the low power consumption mode, controlling the first processor core to work in a normal working mode so as to wake up the first processor core. And when the first processor core works in a normal working mode, setting the state of the first thread into a non-suspended state so as to wake up the first thread.

Optionally, when the first processor core is a virtual processor core, and the physical processor core where the first processor core is located also operates in the low power consumption mode, the physical processor core is controlled to operate in the normal operating mode first, and then the first processor core is controlled to operate in the normal operating mode.

And when the first processor core works in a normal working state and the state of the first thread is set to be a non-suspended state, the first processor core runs the first thread. The first thread periodically detects the shared memory bound with the first thread, acquires data from the shared memory, and processes the data.

Optionally, in step 403, the scheduling module may send an instruction to enter the normal operating mode to the first processor. The first processor receives the instruction and works in a normal working mode.

Optionally, the first processor core starts its own operating clock to implement operating in the normal operating mode.

For example, assuming that the first processor core is an ARM, the instruction sent by the scheduling module to the first processor core to enter the normal operating mode is a send local event (SEVL) instruction. And the first processor core receives the SEVL instruction and starts a working clock of the first processor core so as to realize the working in a normal working mode.

For example, assume that a data generation module of a device stores data to shared memory bound to a thread 21, a notification command is triggered to a scheduling module, the notification command including an identification IM1 of the shared memory. The scheduling module receives the notification command, and determines that data exists in the shared memory corresponding to the identifier IM1 of the shared memory according to the identifier IM1 of the shared memory included in the notification command. According to the identifier IM1 of the shared memory, the identifier ID1 of the thread 21 bound to the shared memory is obtained from the correspondence between the identifier of the thread and the identifier of the shared memory shown in table 3. According to the identifier ID1 of the thread 21, the identifier IC1 of the processor core 41 in which the thread 21 is located is acquired from the correspondence between the identifier of the processor core and the identifier of the thread. Determining that the processor core 41 works in a low power consumption mode according to the identifier IC1 of the processor core 41, and then controlling the processor core 41 to work in a normal working mode to wake up the processor core 41; the state of thread 21 is set to a non-suspended state. Then, the processor core 41 runs the thread 21, and the thread 21 periodically detects the shared memory bound thereto, acquires data from the shared memory, and processes the data.

Optionally, if the data generating module is software (e.g., a thread or a process), the data generating module and the scheduling module may receive a notification command triggered by the data generating module through inter-process communication (IPC) or polling detection by the scheduling module. If the data generating module is a hardware device (e.g. a network card), the scheduling module may receive the notification command triggered by the data generating module by detecting a hardware signal (register or interrupt). Of course, these two mechanisms for receiving the notification command are only examples, and are not limited to these examples, as one way of implementation. For example, the data generation module may also trigger a notification command to the scheduling module by way of a semaphore, etc.

Optionally, the method and the device for processing the cloud service can be used in the common cloud and other scenes, and the device is a server in the public cloud. For example, referring to fig. 7, taking an audio-video conference application in a public cloud as an example, in the audio-video conference application, for one conference, a decryption thread 20, a processing thread 27, an encryption thread 28, a sending thread 29, and the like required for implementing the one conference are often run in a processor of a server. Among them, the decryption thread 20 is bound to the first shared memory 31, the processing thread 27 is bound to the second shared memory 32, the encryption thread 28 is bound to the third shared memory 33, and the sending thread 29 is bound to the fourth shared memory 34. The first shared memory 31, the second shared memory 32, the third shared memory 33, and the fourth shared memory 34 are four different storage spaces in the memory of the server, respectively.

The network card 30 of the server receives audio and video data generated in the conference process, stores the audio and video data into the first shared memory 31, the decryption thread 20 detects the first shared memory 31, detects the audio and video data from the first shared memory 20, acquires the audio and video data and decrypts the audio and video data to obtain decrypted data. At this time, the decryption thread 20 may also be used as a data generating module to store the decryption data into the second shared memory 32, and the processing thread 27 detects the second shared memory 32, detects the decryption data from the second shared memory 32, obtains the decryption data, and processes the decryption data to obtain a processing result. At this time, the processing thread 27 may also be used as a data generating module to store the processing result into the third shared memory 33, and the encryption thread 28 detects the third shared memory, detects the processing result from the third shared memory 33, obtains the processing result, and encrypts the processing result to obtain encrypted data. At this time, the encryption thread 28 may also be used as a data generating module to store the encrypted data into the fourth shared memory 34, and the sending thread 29 detects the fourth shared memory 34, detects the encrypted data from the fourth shared memory 34, obtains the encrypted data, and sends the encrypted data to another device through the communication interface of the device.

The above process is a description of an audio and video data processing process, and when there are a large number of conferences, a large number of decryption threads 20, processing threads 27, encryption threads 28 and sending threads 29 are run on a processor core of the server, thereby causing the power consumption of the processor of the server to be high. The audio and video conference application does not have audio and video data all the time, that is, the server may not receive the audio and video data for a long time, so that part of the processor cores in the server may be controlled to work in a low power consumption mode by the method of the embodiment of the application, so that the power consumption of the processor of the server is reduced.

In the embodiment of the application, the states of the threads running on the first processor core are detected, the states of the threads on the first processor core are all suspension states, and the first processor core is controlled to work in a low power consumption mode. When the processor works in the low power consumption mode, the working frequency of the first processor core is very low, and the required power consumption is correspondingly very low, so that the power consumption of the first processor core is reduced. Before controlling the first processor core to work in the low-power consumption mode, the thread in the non-suspended state on the first processor core is migrated to other processor cores in the normal working state, so that the first processor core is controlled to enter the low-power consumption mode as soon as possible. Furthermore, since the thread on the first processor core can be set to the suspended state, the first processor core can release the computing resource occupied by the thread in the suspended state, so that the computing resource can be saved.

Referring to fig. 8, an embodiment of the present application provides a resource management apparatus 800, where the apparatus 800 is applied in the device in the embodiment shown in fig. 2, fig. 3, or fig. 4, where the device includes at least one processor core, and includes:

a processing unit 801, configured to detect a state of a thread running on a first processor core, where the first processor core is any one of at least one processor core;

the control unit 802 is configured to control the first processor core to operate in a low power consumption mode when the processing unit 801 detects that a thread running on the first processor core meets a preset condition, where an operating frequency of the first processor core is less than a frequency threshold when the first processor core operates in the low power consumption mode.

Optionally, the detailed process of detecting the thread state by the processing unit 801 may refer to relevant contents in step 401 in the embodiment shown in fig. 4. The control unit 802 controls the detailed process of the first processor core, which can be seen in relation to step 402 in the embodiment shown in fig. 4.

Optionally, the preset condition includes that the states of the threads running on the first processor core are all suspension states.

Optionally, the threads run on the first processor core include a first thread, the first thread has a binding relationship with a shared memory included in the device, the shared memory is a storage space in a memory of the device, and the first thread is used to detect whether the shared memory stores data; the state of the first thread is set to a suspend state when the first thread detects that the duration of the shared memory without data exceeds a first time threshold.

Optionally, the control unit 802 is configured to control the first processor core to operate in the low power consumption mode when the processing unit 801 detects that the duration of the suspended state of each thread on the first processor core exceeds the second time threshold.

Optionally, the processing unit 801 is further configured to: and when the duration that the second thread is in the suspended state is detected to exceed a second time threshold, migrating the second thread to a second processor core, wherein the second thread is any one thread running on the first processor core, the second processor core is a processor core which is operated in a low power consumption mode in the equipment, and the load of the second processor core is lower than a load threshold.

Optionally, the processing unit 801 migrates the detailed process of the second thread, which can be referred to as related content in step 402 in the embodiment shown in fig. 4.

Optionally, the processing unit 801 is further configured to: and when the utilization rate of the first processor core is lower than a utilization rate threshold value, migrating a third thread to a third processor core, wherein the third thread is a thread in a non-suspended state on the first processor core, the utilization rate of the first processor core is used for indicating the effective utilization rate of the computing resources of the first processor core, and the third processor core is a processor core which works in a normal working mode in the equipment.

Optionally, the processing unit 801 migrates the detailed process of the third thread, which can be referred to as related content in step 402 in the embodiment shown in fig. 4.

Optionally, the processing unit 801 is further configured to: merging threads in a non-suspended state on a plurality of processor cores in the device onto a portion of the plurality of processor cores.

Optionally, the control unit 802 is further configured to: when data exists in the shared memory, the first processor core is controlled to work in a normal working mode, and the state of the first thread is set to be a normal working state, wherein the working frequency of the first processor core is larger than or equal to a frequency threshold value when the first processor core works in the normal working mode.

Optionally, the control unit 802 controls the detailed processes of the first processor and the first thread, and refer to the related contents in step 403 in the embodiment shown in fig. 4.

Optionally, the apparatus 800 further includes: a receiving unit 803, configured to receive a notification command triggered by a data generation module included in the device, where the notification command is triggered when the data generation module stores data in the shared memory, the notification command includes an identifier of the shared memory, and the notification command includes a command indicating that data exists in the shared memory.

Optionally, the processor core included in the apparatus is a virtual processor core or a physical processor core.

It should be understood that the apparatus 800 of the embodiment of the present application may be implemented by an application-specific integrated circuit (ASIC), or a Programmable Logic Device (PLD), which may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof. When the resource management method shown in fig. 4 can also be implemented by software, the apparatus 800 and its modules may also be software modules.

The apparatus 800 according to the embodiment of the present application may correspond to performing the method described in the embodiment of the present application, and the above and other operations and/or functions of each unit in the apparatus 800 are respectively for implementing the corresponding flow of the method shown in fig. 4, and are not described herein again for brevity.

In an embodiment of the application, the processing unit detects a state of a thread running on a first processor core, the first processor core being any one of the at least one processor core. When detecting that a thread running on the first processor core meets a preset condition, the control unit controls the first processor core to work in a low power consumption mode, wherein the working frequency of the first processor core is smaller than a frequency threshold value when the first processor core works in the low power consumption mode. When the control unit controls the first processor core to work in the low power consumption mode, each thread running on the first processor core cannot occupy the computing resource, and the working frequency of the first processor core is smaller than the frequency threshold value, so that the power consumption of the first processor core is very low, the computing resource of a processor where the first processor core is located is saved, and the power consumption of the processor is reduced.

Referring to fig. 9, an embodiment of the present application provides a schematic diagram of an apparatus 900. The apparatus 900 may be an apparatus in any of the embodiments described above, for example, the apparatus 900 is an apparatus in the embodiment shown in fig. 4. The device 900 comprises at least one processor 901, a memory unit 902, a storage medium 903, a communication interface 904 and a bus system 905. The processor 901, the memory unit 902, the storage medium 903, and the communication interface 904 communicate with each other via a bus system 905.

For any one of the at least one processor 901, the processor 901 includes at least one processor core 9011, and at least one thread 9012 runs on each processor core 9011. The memory unit 902 includes at least one shared memory 9021, and each shared memory 9021 is a memory space in the memory unit 902. Each thread 9012 of the at least one thread 9012 has a binding relationship with one shared memory 9021.

Processor core 9011 of processor 901 may invoke computer executable instructions (e.g., program code) stored in memory unit 902 to implement the operation steps performed by the scheduling module in the embodiment shown in fig. 4. For example, detecting a state of a thread running on a first processor core, the first processor core being any one of the at least one processor core 9011; when detecting that a thread running on the first processor core meets a preset condition, controlling the first processor core to work in a low power consumption mode, wherein the working frequency of the first processor core is smaller than a frequency threshold value when the first processor core works in the low power consumption mode.

Optionally, the storage medium 903 stores the computer execution instruction and an operating system, and when the device 900 starts running, the processor core 9011 in the processor 901 may load the computer execution instruction and the operating system stored in the storage medium 903 into the memory unit 902, and call and run the computer execution instruction in the memory unit 902 in a running environment provided by the operating system.

Alternatively, the processor 901 may be a CPU, a microprocessor, an application-specific integrated circuit (ASIC), or one or more ics for controlling the execution of programs according to the present disclosure. For one embodiment, the processor 901 may include one or more CPUs, such as CPU0 and CPU1 in fig. 9. The processor 901 may also be other general purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general purpose processor may be a microprocessor or any conventional processor or the like.

The bus system 905 in the device 900 may include a power bus, a control bus, a status signal bus, etc., in addition to a data bus. For clarity of illustration, however, the various buses are labeled in the figure as bus system 905.

The communication interface 904 is used for communication with other devices. For example, the processor 901 communicates with the sensing system and the positioning system through the communication interface 904, and the processor 901 communicates with the sensing system and the positioning system through the communication interface 904 to acquire the position and motion attribute information of the obstacle around the moving object.

The storage medium 903 may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. Volatile memory can be Random Access Memory (RAM), which acts as external cache memory. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (static RAM, SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and direct bus RAM (DR RAM).

The bus system 905 may include a power bus, a control bus, a status signal bus, an in-vehicle bus (e.g., a Controller Area Network (CAN) bus), and the like, in addition to a data bus. For clarity of illustration, however, the various buses are labeled in the figure as bus system 905.

It should be understood that the apparatus 900 according to the embodiment of the present application may correspond to the apparatus 800 in the embodiment of the present application, and may correspond to a corresponding main body executing the method in fig. 4 according to the embodiment of the present application, and the above and other operations and/or functions of each module in the apparatus 900 are respectively for implementing the corresponding flow of each method in fig. 4, and are not repeated herein for brevity.

The above embodiments may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded or executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more collections of available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. The semiconductor medium may be a Solid State Drive (SSD).

The above description is only an example of the present application and should not be taken as limiting the present application, and any modifications, equivalents, improvements and the like that are made within the principles of the present application should be included in the scope of the present application.

Claims

1. A resource management method is applied to equipment, wherein the equipment comprises at least one processor core and comprises the following steps:

detecting a state of a thread running on a first processor core, the first processor core being any one of the at least one processor core;

when detecting that a thread running on the first processor core meets a preset condition, controlling the first processor core to work in a low power consumption mode, wherein the working frequency of the first processor core is smaller than a frequency threshold when the first processor core works in the low power consumption mode.

2. The method of claim 1, wherein the preset condition comprises a state of threads running on the first processor core being all suspended.

3. The method of claim 2, wherein the threads running on the first processor core comprise a first thread, the first thread having a binding relationship with a shared memory included in the device, the first thread being configured to detect whether the shared memory stores data, the shared memory being a memory space in a memory of the device;

the state of the first thread is set to a suspended state when the first thread detects that the duration of the shared memory without data exceeds a first time threshold.

4. The method of any of claims 1 to 3, wherein the controlling the first processor core to operate in a low power consumption mode comprises:

and controlling the first processor core to work in a low power consumption mode under the condition that the duration of each thread in the suspended state on the first processor core is detected to exceed a second time threshold.

5. The method of claim 1 or 2, wherein the controlling the first processor core to operate in a low power consumption mode further comprises:

when detecting that the duration of a second thread in a suspended state exceeds a second time threshold, migrating the second thread to a second processor core, wherein the second thread is any thread running on the first processor core, the second processor core is a processor core which is operated in a low power consumption mode in the device, and the load of the second processor core is lower than a load threshold.

6. The method of any of claims 1-5, wherein the controlling the first processor core to operate in a low power consumption mode further comprises:

when the utilization rate of the first processor core is lower than a utilization rate threshold value, migrating a third thread to a third processor core, wherein the third thread is a thread in a non-suspended state on the first processor core, the utilization rate of the first processor core is used for indicating the effective utilization rate of computing resources of the first processor core, and the third processor core is a processor core which works in a normal working mode in the equipment.

7. The method of any of claims 1-6, wherein the controlling the first processor core to operate in a low power consumption mode further comprises:

merging threads in a non-suspended state on a plurality of processor cores in the device onto a portion of the plurality of processor cores.

8. The method of any of claims 1-7, wherein the controlling the first processor core to operate after the low power mode further comprises:

when data exist in the shared memory of the equipment, the first processor core is controlled to work in a normal working mode, and the state of the first thread is set to be a normal working state, wherein the working frequency of the first processor core is greater than or equal to a frequency threshold value when the first processor core works in the normal working mode.

9. The method of any of claims 1 to 8, wherein the device comprises a processor core that is a virtual processor core or a physical processor core.

10. A resource management apparatus, applied in a device including at least one processor core, comprising:

a processing unit configured to detect a state of a thread running on a first processor core, the first processor core being any one of the at least one processor core;

the control unit is used for controlling the first processor core to work in a low power consumption mode when the processing unit detects that the thread running on the first processor core meets a preset condition, wherein the working frequency of the first processor core is smaller than a frequency threshold when the first processor core works in the low power consumption mode.

11. The apparatus of claim 10, wherein the preset condition comprises a state of threads running on the first processor core being all suspended.

12. The apparatus of claim 11, wherein the threads running on the first processor core comprise a first thread, the first thread having a binding relationship with a shared memory included in the device, the first thread being configured to detect whether the shared memory stores data, the shared memory being a memory space in a memory of the device;

13. The apparatus of any of claims 10 to 12, wherein the control unit is to control the first processor core to operate in a low power consumption mode if the processing unit detects that a duration of time for which threads on the first processor core are in a suspended state exceeds a second time threshold.

14. The apparatus as claimed in claim 10 or 11, wherein said processing unit is further configured to:

15. The apparatus of any of claims 10 to 14, wherein the processing unit is further configured to:

16. The apparatus of any of claims 10 to 15, wherein the processing unit is further configured to:

17. A processor, characterized in that it comprises a processor core adapted to implement the operating steps of the method according to any one of claims 1 to 9.

18. An apparatus, characterized in that the apparatus comprises a processor comprising a processor core for implementing the operating steps of the method according to any one of claims 1 to 9.