CN113853067A - Method for manufacturing wiring substrate - Google Patents
Method for manufacturing wiring substrate Download PDFInfo
- Publication number
- CN113853067A CN113853067A CN202110697059.0A CN202110697059A CN113853067A CN 113853067 A CN113853067 A CN 113853067A CN 202110697059 A CN202110697059 A CN 202110697059A CN 113853067 A CN113853067 A CN 113853067A
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- seed layer
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/188—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by direct electroplating
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/10—Glass or silica
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/14—Metallic material, boron or silicon
- C23C14/18—Metallic material, boron or silicon on other inorganic substrates
- C23C14/185—Metallic material, boron or silicon on other inorganic substrates by cathodic sputtering
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
- C23C16/401—Oxides containing silicon
- C23C16/402—Silicon dioxide
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
- C23C28/30—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer
- C23C28/32—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one pure metallic layer
- C23C28/322—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one pure metallic layer only coatings of metal elements only
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
- C23C28/30—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer
- C23C28/34—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates
- C23C28/345—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates with at least one oxide layer
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
- C25D17/10—Electrodes, e.g. composition, counter electrode
- C25D17/12—Shape or form
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/34—Pretreatment of metallic surfaces to be electroplated
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/245—Reinforcing conductive patterns made by printing techniques or by other techniques for applying conductive pastes, inks or powders; Reinforcing other conductive patterns by such techniques
- H05K3/246—Reinforcing conductive paste, ink or powder patterns by other methods, e.g. by plating
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/31—Coating with metals
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/22—Electroplating: Baths therefor from solutions of zinc
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0723—Electroplating, e.g. finish plating
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
- H05K3/242—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/381—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
Abstract
Provided is a method for manufacturing a wiring substrate having a wiring layer with a predetermined wiring pattern using a solid electrolyte membrane. First, a substrate with a seed layer is prepared. The tape seed layer substrate includes: an insulating substrate having a main surface composed of a 1 st region and a 2 nd region which is a region other than the 1 st region; and a conductive seed layer disposed on the 1 st region. And forming a conductive layer at least on the 2 nd area to obtain a 1 st processed substrate. Next, an insulating layer is formed on the 1 st processed substrate. Next, the seed layer is exposed. And then, forming a metal layer on the surface of the seed layer. Here, a solid electrolyte membrane containing a solution containing metal ions is disposed between the 2 nd treatment substrate and an anode, and a voltage is applied between the anode and the seed layer while the solid electrolyte membrane is brought into pressure contact with the seed layer. Then, the insulating layer and the conductive layer are removed.
Description
Technical Field
The present invention relates to a method for manufacturing a wiring board.
Background
Conventionally, in the manufacture of wiring boards, plating methods have been widely used for forming wiring. However, the plating method requires washing with water after the plating treatment, and thus requires treatment of a waste liquid. Therefore, patent document 1 describes a method for forming a metal coating as follows: a solid electrolyte membrane is disposed between an anode and a cathode (substrate), a solution containing metal ions is disposed between the anode and the solid electrolyte membrane, the solid electrolyte membrane is brought into contact with the substrate, and a voltage is applied between the anode and the substrate to deposit a metal on the surface of the substrate.
Documents of the prior art
Patent document
Patent document 1: japanese patent laid-open No. 2014-185371
Disclosure of Invention
Problems to be solved by the invention
Patent document 1 does not describe a method for forming a metal coating film having a predetermined pattern. Accordingly, the present invention provides a method for manufacturing a wiring substrate having a wiring layer with a predetermined wiring pattern using a solid electrolyte membrane.
Means for solving the problems
According to one aspect of the present invention, there is provided a method of manufacturing a wiring board including an insulating base material and a wiring layer having a predetermined wiring pattern provided on the insulating base material, the method including:
step (a) of preparing a substrate having a seed layer,
here, the tape seed layer substrate includes:
the insulating base material has a main surface composed of a 1 st region and a 2 nd region, wherein the 1 st region has a predetermined pattern corresponding to the wiring pattern, and the 2 nd region is a region other than the 1 st region; and
a conductive seed layer disposed on the 1 st region;
a step (b) of forming a conductive layer at least on the 2 nd region to obtain a 1 st treated substrate;
a step (c) of forming an insulating layer on the 1 st process substrate, the seed layer and the conductive layer being covered with the insulating layer;
etching the insulating layer, and exposing the seed layer while leaving the insulating layer on the conductive layer on the 2 nd region to obtain a 2 nd processing substrate;
a step (e) of forming a metal layer on the surface of the seed layer,
here, a solid electrolyte membrane containing a solution containing metal ions is disposed between the 2 nd treatment substrate and an anode, and a voltage is applied between the anode and the seed layer while the solid electrolyte membrane is brought into pressure contact with the seed layer; and
and (f) removing the insulating layer and the conductive layer.
Effects of the invention
In the manufacturing method of the present invention, a wiring substrate having a wiring layer with a predetermined wiring pattern can be manufactured using the solid electrolyte membrane.
Drawings
Fig. 1 is a flowchart illustrating a method of manufacturing a wiring substrate according to an embodiment.
Fig. 2 is a conceptual diagram illustrating a step of forming a seed layer.
Fig. 3 is a conceptual diagram illustrating a step of forming a conductive layer.
Fig. 4 is a conceptual diagram illustrating a step of forming an insulating layer.
Fig. 5 is a conceptual diagram illustrating a step of exposing the seed layer.
Fig. 6 is a conceptual diagram illustrating a step of forming a metal layer.
Fig. 7 is a conceptual diagram illustrating a step of removing the insulating layer and the conductive layer.
Fig. 8 is a conceptual diagram illustrating a step of removing the insulating layer and the conductive layer.
Fig. 9 is a schematic cross-sectional view showing a film formation apparatus used in a step of forming a metal layer.
Fig. 10 is a schematic cross-sectional view of the film forming apparatus shown in fig. 9, showing the case lowered to a predetermined height.
Description of the reference numerals
1: wiring substrate, 2: wiring layer, 10: tape seed layer substrate, 11: insulating base material, 12: conductive layer, R1: region 1, R2: region 2, 13: seed layer, 14: metal layer, 16: insulating layer, 20: treated substrate 1, 30: treated substrate 2, 50: film forming apparatus, 51: anode, 52: solid electrolyte membrane, L: solutions containing metal ions (metal solutions)
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the drawings referred to in the following description, the same members or members having the same functions are denoted by the same reference numerals, and redundant description may be omitted. For convenience of explanation, the dimensional ratio of the drawings may be different from the actual ratio, and a part of the member may be omitted from the drawings. In the present application, the numerical range indicated by the symbols "to" includes ranges in which the numerical values described before and after the symbols "to" are respectively a lower limit value and an upper limit value.
As shown in fig. 1, the method for manufacturing a wiring substrate according to the embodiment includes: a step (S1) of preparing a seed layer-carrying substrate; a step (S2) for improving the adhesion between the insulating base material and the seed layer; a step (S3) of forming a conductive layer; a step (S4) of alloying the metal constituting the seed layer and the metal constituting the conductive layer; a step (S5) of forming an insulating layer; a step (S6) for exposing the seed layer; a step (S7) of forming a metal layer; and a step (S8) of removing the insulating layer and the conductive layer. Further, the step (S2) and the step (S4) are not essential. Hereinafter, each step will be described.
(1) Step of preparing a substrate having a seed layer (S1)
First, as shown in fig. 2, the seed layer 13 is formed in the 1 st region R1 on the main surface 11a of the insulating substrate 11, and the tape seed layer substrate 10 is obtained. The 1 st region R1 is a region having a predetermined pattern corresponding to the wiring pattern of the wiring substrate manufactured by the manufacturing method of the embodiment. The main surface 11a of the insulating substrate 11 is composed of the 1 st region R1 and the 2 nd region R2 which is a region other than the 1 st region R1.
As the insulating substrate 11, for example, a substrate made of resin such as a glass epoxy resin substrate and containing glass, a resin substrate, a glass substrate, or the like can be used. Examples of the resin used for the insulating substrate 11 include PET resin, PI (polyimide) resin, LCP (liquid crystal polymer), epoxy resin, ABS resin, AS resin, AAS resin, PS resin, EVA resin, PMMA resin, PBT resin, PPS resin, PA resin, POM resin, PC resin, PP resin, PE resin, polymer alloy resin including elastomer and PP, thermoplastic resin such AS modified PPO resin, PTFE resin, and ETFE resin, thermosetting resin such AS phenol resin, melamine resin, amino resin, unsaturated polyester resin, polyurethane, diallyl phthalate, silicone resin, and alkyd resin, and resin obtained by adding cyanate resin to epoxy resin.
The material of the seed layer 13 is not particularly limited as long as it is conductive. The material of the seed layer 13 may be Cu or Ag or an alloy thereof. The seed layer 13 may have a thickness of 20nm or more, preferably 1000 μm or more, from the viewpoint of in-plane uniformity of the metal layer 14 described later, and may have a thickness of 1 μm or less, preferably 300nm or less, from the viewpoint of manufacturing cost.
The seed layer 13 may be formed by any method. For example, the seed layer 13 can be formed by applying a dispersion of metal particles containing Cu, Ag, or an alloy thereof to the 1 st region R1 and solidifying the dispersion. In order to form fine wiring, the metal particles preferably have a smaller particle diameter, and may have a particle diameter of 1nm or more and 100nm or less, for example. The metal particles may have a particle diameter of 20nm or less. This lowers the melting point of the metal particles, and sintering of the metal particles is facilitated. As a dispersion medium of the dispersion liquid, a liquid that is volatilized by heating, such as decanol, can be used. The dispersion may also contain additives. Examples of the additive include linear fatty acid salts having 10 to 17 carbon atoms. Examples of the method of applying the dispersion include printing methods such as screen printing, ink jet printing, and transfer printing. The method for curing the dispersion is not particularly limited. For example, the dispersion liquid can be solidified by volatilizing the dispersion medium by heating and sintering the metal particles.
The seed layer 13 may be formed in the 1 st region R1 by disposing a metal mask on the insulating substrate 11 and performing vacuum vapor deposition, sputtering, or the like.
In order to improve the adhesion between the seed layer 13 and the insulating substrate 11, the main surface 11a of the insulating substrate 11 may be subjected to a surface treatment before the seed layer 13 is formed. For example, a layer such as an undercoat layer may be formed on the main surface 11a of the insulating substrate 11. As the undercoat layer, polyimide, polyamideimide, or the like can be used. The principal surface 11a of the insulating substrate 11 may be roughened. Roughening can be performed by laser irradiation, etching, desmear treatment, mechanical processing (grinding ), or the like.
The 1 st region R1 may be constituted by only 1 continuous region, or may include a plurality of independent regions. When the 1 st region R1 includes a plurality of independent regions, the seed layers 13 formed in the independent regions are electrically connected to each other via the conductive layer 12 described later. Therefore, it is not necessary to provide a lead wiring for use in the step of forming a metal layer (S7) described later for each seed layer 13 formed in each individual region.
(2) Step of improving the adhesiveness (S2)
Next, the adhesion between the insulating substrate 11 and the seed layer 13 is improved. For example, the adhesion can be improved by heating the substrate 10 with the seed layer 13 in an inert atmosphere. The insulating substrate 11 and/or the seed layer 13 may be heated while being pressurized, whereby the adhesiveness can be further improved. This step (S2) may be performed as needed after the step of preparing the seed layer-carrying substrate (S1) and before the step of forming the metal layer (S7). In the case where the step (S2) of forming the conductive layer is performed before the step (S3), the tape seed layer substrate 10 may be heated to a temperature equal to or higher than the heat-resistant temperature of the conductive layer 12 described later. That is, as a material of the conductive layer 12, a low melting point material such as Sn can be used. In addition, this step (S2) is not an essential step.
By improving the adhesion between insulating substrate 11 and seed layer 13, seed layer 13 can be prevented from peeling off from insulating substrate 11 when solid electrolyte membrane 52 is separated from metal layer 14, for example, in the step of forming a metal layer (S7). In the wiring substrate 1 (see fig. 8) manufactured by the manufacturing method of the embodiment, the adhesion between the wiring layer 2 and the insulating base material 11 can be improved.
(3) Step of Forming conductive layer (S3)
As shown in fig. 3, the conductive layer 12 is formed on the tape seed layer substrate 10, and the 1 st processed substrate 20 is obtained. The conductive layer 12 is formed at least in the 2 nd region R2 of the main surface 11a of the insulating substrate 11. As shown in fig. 3, the conductive layer 12 may be formed on the seed layer 13 in addition to the 2 nd region R2. In the case where the conductive layer 12 is formed on the 2 nd region R2 and the seed layer 13, it is not necessary to use a patterning method, and thus the manufacturing process becomes simple.
The conductive layer 12 has sufficient conductivity for forming a metal layer 14 described later. Examples of the material of the conductive layer 12 include FeSi2、CoSi2、MoSi2、WSi2、VSi2、ReSi1.75、CrSi2、NbSi2、TaSi2、TiSi2、ZrSi2Silicide of isometals (Silides), especially transition metal Silicide, TiO2Conductive metal oxides such as SnO, GeO, and ITO (indium tin oxide), Pd, and SMetals such as n, Cu, Ti, Al, and Cr, Pd, Sn, Cu, Ti, Al, Cr, and Si, or alloys containing at least one of these metals, and conductive resins. In particular, the conductive layer 12 may contain a metal that is easily oxidized (i.e., has a lower standard redox potential) than the metal contained in the seed layer 13. Thus, the conductive layer 12 can be easily etched in the step of exposing the seed layer (S6) and the step of removing the insulating layer and the conductive layer (S8), which will be described later. When the seed layer 13 contains Ag, the conductive layer 12 may contain Pd, Sn, or Cu, or an alloy thereof. Since Pd, Sn, and Cu are alloyed with Ag, the metal contained in the seed layer 13 and the metal contained in the conductive layer 12 can be alloyed by the alloying step (S4) described later.
The conductive layer 12 may have a natural oxide film on the surface. The natural oxide film is an oxide film naturally formed on the surface of a substance when the substance is left in the atmosphere. Examples of the natural oxide film include a passivation film formed on the surface of Ti, Al, Cr or an alloy containing at least one of these, and SiO formed on the surface of Si or silicide2. The conductive layer 12 may have a thickness smaller than that of the seed layer 13, may have a thickness of 20nm or more, preferably 100 μm or more, from the viewpoint of in-plane uniformity of the metal layer 14 described later, and may have a thickness of 300nm or less from the viewpoint of manufacturing cost.
The conductive layer 12 may be formed by any method. For example, the conductive layer 12 can be formed by a PVD (physical vapor deposition) method such as a sputtering method, a CVD (chemical vapor deposition) method, or an electroless plating method.
(4) Step of alloying (S4)
In the case where the seed layer 13 contains Ag, and the conductive layer 12 contains Pd, Sn, or Cu, or an alloy thereof, the metal contained in the seed layer 13 may be alloyed with the metal contained in the conductive layer 12. This can suppress migration of Ag contained in the seed layer 13. Alloying may be performed by heating the 1 st treated substrate 20. As the heating means, any means such as a reflow furnace, an infrared lamp, a laser, and a xenon lamp can be used. The step (S4) may be performed as needed after the step (S3) of forming the conductive layer and before the step (S7) of forming the metal layer. In addition, this step (S4) is not an essential step.
(5) Step of Forming insulating layer (S5)
As shown in fig. 4, an insulating layer 16 is formed on the 1 st process substrate 20, and the seed layer 13 and the conductive layer 12 are covered with the insulating layer 16.
The material of the insulating layer 16 is not particularly limited as long as it is insulating. An example of the material of the insulating layer 16 is SiO2、Al2O3、TiO2Oxides such as SiOC (carbon-doped silicon oxide), polysilane, polysilazane, epoxy resins, and acrylate resins.
The insulating layer 16 can be formed by any method such as a CVD method, a sputtering method, a spray coating method, a spin coating method, or a dip coating method. Further, the spray coating method refers to the following method: a raw material solution containing a metal element is atomized by an ultrasonic oscillator to form mist, and the mist is supplied to a substrate and decomposed and/or reacted on the surface of the substrate by thermal energy or the like, thereby forming a thin film containing the metal element on the surface of the substrate.
The insulating layer 16 may have a thickness greater than that of the seed layer 13. In particular, the insulating layer 16 may have a thickness 2.5 to 10 times the thickness of the seed layer 13. Thus, the surface of the insulating layer 16 becomes sufficiently flat, and the No. 2 processed substrate 30 having a flat surface is easily formed in the subsequent step (S6) of exposing the seed layer.
(6) Exposing the seed layer (S6)
As shown in fig. 5, the insulating layer 16 is etched so that the insulating layer 16 on the conductive layer 12 on the 2 nd region R2 remains and the conductive layer 12 on the seed layer 13 is exposed, and the conductive layer 12 on the seed layer 13 is removed to expose the surface of the seed layer 13. The conductive layer 12 on the seed layer 13 may be removed by etching. In the case where the conductive layer 12 is not formed on the seed layer 13 in the step of forming the conductive layer 12 (S3), and in the case where the metal contained in the conductive layer 12 and the metal contained in the seed layer 13 are completely alloyed in the step of alloying (S4), the removal of the conductive layer 12 is not necessary, and the insulating layer 16 may be etched so that the insulating layer 16 on the conductive layer 12 on the 2 nd region R2 remains and the surface of the seed layer 13 or the layer of the alloy of the seed layer 13 and the conductive layer 12 is exposed.
As shown in fig. 5, the entire surface of the insulating layer 16 may be etched without using a patterning method. The etching of the insulating layer 16 in the 2 nd region R2 is not essential, and the insulating layer 16 in at least the 1 st region R1 may be etched.
The insulating layer 16 and the conductive layer 12 can be etched by either a dry etching method or a wet etching method. Examples of the dry etching include a reactive gas etching method, a sputter etching method, a plasma etching method, an ion milling method, a Reactive Ion Etching (RIE) method, a reactive ion beam etching method, a radical etching method, a photoexcitation etching method, a laser-assisted etching method, and a laser ablation etching method. In the reactive ion etching method, a Capacitively Coupled Plasma (CCP), an Inductively Coupled Plasma (ICP), or a microwave ECR (Electron Cyclotron Resonance) plasma can be used. Examples of the wet etching include chemical etching using a solution of an acid or an alkali such as HF as an etching solution, and Chemical Mechanical Polishing (CMP) in which chemical etching and mechanical polishing are combined.
An etching gas or an etching liquid used for etching the insulating layer 16 and the conductive layer 12 may be appropriately selected depending on the material of each of the insulating layer 16 and the conductive layer 12. As an example of the etching gas, CF can be given4、SF6Boron, chlorine, HBr, BCl3. As the etching solution, an acid solution such as HF or an alkali solution can be used. For example, the insulating layer 16 is made of SiO2SiOC, polysilane or polysilazane, the compound can be formed by using CF4The reactive ion etching of the gas etches the insulating layer 16. The insulating layer 16 is made of SiO2Or SiOC, the insulating layer 16 may be etched by wet etching using an HF solution. In the case where the insulating layer 16 is formed of an epoxy-based resin or an acrylate-based resin, O may be used2/CF4Mixed gases or O2/SF6/CHF3 The insulating layer 16 is etched by reactive ion etching using a mixed gas or wet etching using an alkali solution. In the case where the conductive layer 12 is formed of silicide, CF may be used4The conductive layer 12 is etched by reactive ion etching with gas.
In this way, the No. 2 treated substrate 30 including the insulating substrate 11, the conductive seed layer 13 provided in the No. 1 region R1, the conductive layer 12 provided in the No. 2 region R2, and the insulating layer 16 provided on the conductive layer 12 was obtained. In the second process substrate 30, the heights of the surface of the seed layer 13 and the surface of the insulating layer 16 from the main surface 11a of the insulating substrate 11 may be substantially equal. Thus, the surface of the 2 nd treated substrate 30 becomes sufficiently flat, and therefore, in the subsequent step of forming a metal layer (S7), the solid electrolyte membrane 52 can be easily brought into uniform contact with the 2 nd treated substrate 30.
(7) Step of Forming Metal layer (S7)
As shown in fig. 6, a metal layer 14 is formed on the surface of the seed layer 13. Examples of the material of the metal layer 14 include Cu, Ni, Ag, Au, and the like, and Cu is preferable. The metal layer 14 may have a thickness of 1 μm or more and 100 μm or less, for example.
Fig. 9 and 10 show an example of a film formation apparatus 50 used for forming the metal layer 14. The film forming apparatus 50 includes: a metal anode 51 disposed so as to face the seed layer 13, a solid electrolyte membrane 52 disposed between the anode 51 and the 2 nd process substrate 30, and a power supply unit 54 for applying a voltage between the anode 51 and the seed layer 13.
The film forming apparatus 50 further includes a housing 53. The anode 51 and a solution (hereinafter, referred to as a metal solution) L containing ions of a metal which is a material of the metal layer 14 are accommodated in the case 53. As shown in fig. 9, the case 53 may partition a space containing the metal solution L between the anode 51 and the solid electrolyte membrane 52. In this case, the anode 51 may be a plate-like member formed of a material (e.g., Cu) that is the same as the material of the metal layer 14 and is soluble in the metal solution L, or a plate-like member formed of a material (e.g., Ti) that is insoluble in the metal solution L. In the film formation apparatus 50 that accommodates the metal solution L between the anode 51 and the solid electrolyte film 52, since the solid electrolyte film 52 and the 2 nd process substrate 30 can be pressed against each other at a uniform pressure, the metal layer 14 can be uniformly formed on the seed layer 13 over the entire surface of the 2 nd process substrate 30. Therefore, the film formation apparatus 50 is suitable for forming a fine wiring pattern.
Although not shown, the anode 51 and the solid electrolyte membrane 52 may be in contact with each other. In this case, the anode 51 may be formed of a porous body that allows the metal solution L to permeate therethrough, and the opposite surface of the anode 51 to the surface in contact with the solid electrolyte membrane 52 may be in contact with the space that accommodates the metal solution L.
Examples of the material of the solid electrolyte membrane 52 include resins having a cation exchange function, such as fluorine-based resins (registered trademark) of Nafion (manufactured by dupont), hydrocarbon-based resins, polyamic acid resins, and SELEMIONs (CMV, CMD, and CMF series) manufactured by asahi glass. When the solid electrolyte membrane 52 is brought into contact with the metal solution L, the metal solution L permeates into the solid electrolyte membrane 52. As a result, the solid electrolyte membrane 52 contains the metal solution L therein. The solid electrolyte membrane 52 may have a thickness of about 5 μm to about 200 μm, for example.
The metal solution L contains a metal (for example, Cu, Ni, Ag, Au, or the like) in an ionic state as a material of the metal layer 14. The metal solution L may contain nitrate ions, phosphate ions, succinate ions, sulfate ions, pyrophosphate ions. The metal solution L may be an aqueous solution of a salt of a metal such as nitrate, phosphate, succinate, sulfate, pyrophosphate, or the like.
The film deposition apparatus 50 further includes a lifting device 55 for lifting and lowering the housing 53 above the housing 53. The lifting device 55 may include, for example, a hydraulic or pneumatic cylinder, an electric actuator, a linear guide, a motor, and the like.
The housing 53 has a supply port 53a and a discharge port 53 b. The supply port 53a and the discharge port 53b are connected to the tank 61 via a pipe 64. The metal solution L sent from the tank 61 by the pump 62 connected to the pipe 64 flows into the casing 53 from the supply port 53a, is discharged from the casing 53 through the discharge port 53b, and returns to the tank 61. A pressure regulating valve 63 is provided downstream of the discharge port 53b in the pipe 64. The pressure of the metal solution L in the housing 53 can be adjusted by the pressure regulating valve 63 and the pump 62.
The film formation apparatus 50 further includes a metal base 56 on which the 2 nd process substrate 30 is placed, and a conductive member 57 for electrically connecting the conductive layer 12 or the seed layer 13 of the 2 nd process substrate 30 and the metal base 56. The conductive member 57 may be a metal plate that covers a part of the edge of the 2 nd processed substrate 30 and is locally bent to be in contact with the metal chassis 56. Thereby, the metal base 56 is electrically connected to the conductive layer 12 and the seed layer 13 through the conductive member 57. Further, the conductive member 57 may be detachable from the No. 2 treatment substrate 30.
The negative electrode of the power supply unit 54 is electrically connected to the conductive layer 12 and the seed layer 13 via the metal base 56, and the positive electrode of the power supply unit 54 is electrically connected to the anode 51.
The metal layer 14 can be formed using the film forming apparatus 50 as follows.
As shown in fig. 9, the No. 2 processing substrate 30 and the conductive member 57 are placed at predetermined positions on the metal base 56. Next, as shown in fig. 10, the housing 53 is lowered to a predetermined height by the lifting device 55.
Next, the metal solution L is pressurized by the pump 62. Then, the metal solution L in the case 53 is maintained at a predetermined pressure by the pressure regulating valve 63. The solid electrolyte film 52 is deformed so as to follow the surface of the No. 2 process substrate 30, that is, the surface of the seed layer 13 and the insulating layer 16, and is in contact with the surface of the seed layer 13 and the insulating layer 16. Thereby, the metal solution L contained in the solid electrolyte membrane 52 is in contact with the surfaces of the seed layer 13 and the insulating layer 16. The solid electrolyte membrane 52 is uniformly pressed against the surfaces of the seed layer 13 and the insulating layer 16 by the pressure of the metal solution L in the case 53.
A voltage is applied between the anode 51 and the seed layer 13 by the power supply unit 54. Then, the metal ions contained in the metal solution L in contact with the seed layer 13 are reduced on the surface of the seed layer 13, and metal is deposited on the surface of the seed layer 13. On the other hand, no metal is deposited on the surface of the insulating layer 16 because no reduction reaction of metal ions occurs. Thereby, the metal layer 14 is selectively formed on the surface of the seed layer 13. Further, the voltage applied between the anode 51 and the seed layer 13 may be set as appropriate. By applying a higher voltage, the metal deposition rate can be increased. Further, the metal solution L may be heated. This can increase the metal deposition rate.
After the metal layer 14 having a predetermined thickness is formed, the application of the voltage between the anode 51 and the seed layer 13 is stopped, and the pressurization of the metal solution L by the pump 62 is stopped. Then, the case 53 is raised to a predetermined height (see fig. 9), and the solid electrolyte membrane 52 is separated from the metal layer 14. The No. 2 processed substrate 30 on which the metal layer 14 is formed is removed from the metal base 56.
(8) A step of removing the insulating layer and the conductive layer (S8)
As shown in fig. 7, the insulating layer 16 is removed, and then, as shown in fig. 8, the conductive layer 12 is removed. Thereby, the wiring layer 2 having a predetermined wiring pattern including the seed layer 13 and the metal layer 14 is formed on the insulating base material 11.
The insulating layer 16 and the conductive layer 12 can be removed by etching. The etching method for the insulating layer 16 and the conductive layer 12 may be either dry or wet. Examples of the dry etching include a reactive gas etching method, a sputter etching method, a plasma etching method, an ion milling method, a Reactive Ion Etching (RIE) method, a reactive ion beam etching method, a radical etching method, a photoexcitation etching method, a laser-assisted etching method, and a laser ablation etching method. In the reactive ion etching method, a Capacitively Coupled Plasma (CCP), an Inductively Coupled Plasma (ICP), or a microwave ECR (Electron Cyclotron Resonance) plasma can be used.
An etching gas or an etching liquid used for etching the insulating layer 16 and the conductive layer 12 can be appropriately selected depending on the material of each of the insulating layer 16 and the conductive layer 12. As an example of the etching gas, CF can be given4、SF6Boron, chlorine, HBr, BCl3. As the etching solution, an acid solution such as HF or an alkali solution can be used. For example, the insulating layer 16 is made of SiO2SiOC, polysilane or polysilazaneMay be prepared by using CF4The reactive ion etching of the gas etches the insulating layer 16. The insulating layer 16 is made of SiO2Or SiOC, the insulating layer 16 may be etched by wet etching using an HF solution. In the case where the insulating layer 16 is formed of an epoxy-based resin or an acrylate-based resin, O may be used2/CF4Mixed gases or O2/SF6/CHF3 The insulating layer 16 is etched by reactive ion etching using a mixed gas or wet etching using an alkali solution. In the case where the conductive layer 12 is formed of silicide, CF may be used4The conductive layer 12 is etched by reactive ion etching with gas.
As described above, the wiring substrate 1 including the insulating substrate 11 and the wiring layer 2 having a predetermined wiring pattern provided on the insulating substrate 11 is manufactured.
In this embodiment, as described above, by forming the insulating layer 16 on the conductive layer 12 formed in the 2 nd region R2, in the step of forming the metal layer 14 (S2), metal can be selectively deposited on the surface of the seed layer 13. That is, it is possible to prevent metal deposition in regions other than the predetermined wiring pattern.
According to the intensive studies of the present inventors, in the case where the insulating layer 16 is not formed on the conductive layer 12 formed in the 2 nd region R2, when a higher voltage is applied and the metal solution L is heated in the step of forming the metal layer 14 (S7), there is a possibility that metal is deposited on the conductive layer 12. However, in the manufacturing method of the embodiment, such unintended deposition of metal is prevented by forming the insulating layer 16 on the conductive layer 12. Therefore, in the step (S7) of forming the metal layer 14, the high voltage application and/or the heating of the metal solution L can be performed, and thereby the metal deposition rate can be increased and the time for manufacturing the wiring substrate 1 can be shortened.
In the manufacturing method according to the embodiment, since the wiring substrate 1 can be manufactured without using a resist mask, the manufacturing cost of the wiring substrate 1 can be reduced and the manufacturing time can be shortened.
While the embodiments of the present invention have been described above in detail, the present invention is not limited to the above embodiments, and various design changes can be made without departing from the scope of the present invention described in the claims.
[ examples ] A method for producing a compound
The present invention will be specifically described below with reference to examples, but the present invention is not limited to these examples.
Example 1
A glass epoxy substrate (glass fiber-reinforced epoxy laminate) was prepared as an insulating substrate. An Ag layer having a predetermined pattern was formed as a seed layer on the main surface of the insulating substrate using an ink containing silver nanoparticles. Thus, a tape seed layer substrate was obtained.
In order to sinter the seed layer and improve the adhesion between the seed layer and the insulating substrate, the surface of the tape seed layer substrate was irradiated with laser light (wavelength 1064nm, beam diameter 1.6mm, output 150W) for 0.2 seconds in an inert atmosphere, and the tape seed layer substrate was heated.
Subsequently, a Ti layer having a thickness of 300nm was formed as a conductive layer on the seed layer base material by a sputtering method. The conductive layer is formed on the entire main surface of the substrate with the seed layer. That is, the seed layer and the region of the main surface of the insulating base material not covered with the seed layer are covered with the conductive layer. Thus, the 1 st treated substrate was obtained.
Formation of SiO on the No. 1 treated substrate by CVD method2And a film forming an insulating layer covering the seed layer and the conductive layer.
And etching the whole insulating layer by an ion milling method to expose the conductive layer on the seed layer. Further, the conductive layer on the seed layer was removed by ion milling. Thereby, the surface of the seed layer is exposed. The conductive layer and the insulating layer remain on the main surface of the insulating substrate in the region not covered with the seed layer, and the surfaces of the conductive layer and the insulating substrate are not exposed.
Using the film formation apparatus 50 shown in fig. 9 and 10, a Cu layer was formed as a metal layer on the surface of the seed layer under the following conditions.
Cathode: seed layer
Anode: oxygen-free copper wire
Solid electrolyte membrane: nafion (registered trademark) (thickness about 8 μm)
Metal solution: 1.0mol/L copper sulfate aqueous solution
Pressure pressing the solid electrolyte membrane against the seed layer: 1.0MPa
Voltage application: 0.5V
Current density: 0.23mA/cm2
Then, by using CF4The residual insulating layer and conductive layer are removed by gas capacitively coupled plasma etching. Thus, a wiring layer of a predetermined wiring pattern composed of a seed layer and a metal layer is formed on the insulating base material. Thus, a wiring board including the insulating base material and the wiring layer was obtained.
Example 2
A wiring board was produced in the same manner as in example 1, except that a glass substrate was used as the insulating substrate and that the output of the laser beam irradiated to the surface of the seed layer substrate was set to 180W.
Example 3
A wiring substrate was produced in the same manner as in example 1, except that polyimide was applied as an undercoat layer on the main surface of the insulating substrate by a spin coating method before forming the seed layer, and the substrate with the seed layer was heated to 120 ℃ for 30 minutes in an inert atmosphere instead of laser irradiation.
Example 4
A wiring substrate was produced in the same manner as in example 2, except that polyimide was applied as an undercoat layer on the main surface of the insulating base material by a spin coating method before the seed layer was formed.
Example 5
A wiring substrate was produced in the same manner as in example 1, except that the main surface of the insulating substrate was roughened before the seed layer was formed and the tape seed layer substrate was heated to 120 ℃ for 30 minutes in an inert atmosphere instead of laser irradiation.
Comparative example 1
A glass epoxy substrate was prepared as an insulating substrate. The thickness is formed on the whole main surface of the insulating base material by sputteringWSi of 100nm2The layer serves as a conductive layer.
Next, on the conductive layer, an Ag layer having a predetermined pattern was formed as a seed layer using an ink containing silver nanoparticles.
Using the film formation apparatus 50 shown in fig. 9 and 10, a Cu layer was formed as a metal layer on the surface of the seed layer under the same conditions as in example 1.
Then, by using CF4The conductive layer was etched by gas capacitively coupled plasma etching using the metal layer as a mask. Thus, a wiring layer of a predetermined wiring pattern including the remaining conductive layer, seed layer, and metal layer is formed on the insulating base material. Thus, a wiring board including the insulating base material and the wiring layer was obtained.
Comparative example 2
A wiring substrate was produced in the same manner as in comparative example 1, except that the base material was heated to 200 ℃ for 30 minutes in an inert atmosphere after the conductive layer was formed and before the seed layer was formed.
< evaluation of adhesion >
Tape peeling tests were performed on the wiring boards produced in examples 1 to 5 and comparative examples 1 and 2. The wiring layers of the wiring boards of comparative examples 1 and 2 were peeled off from the insulating base material. The wiring layers of the wiring boards of examples 1 to 5 were not peeled off from the insulating base material. The wiring boards of examples 1 to 5 showed higher adhesion between the wiring layer and the insulating layer base material than the wiring boards of comparative examples 1 and 2.
Example 6
A glass substrate was prepared as an insulating substrate. A Cu layer having a predetermined pattern and a thickness of 300nm was formed as a seed layer on the main surface of the insulating substrate by a screen printing method using an ink containing copper nanoparticles. Thus, a tape seed layer substrate was obtained.
In order to sinter the seed layer and improve the adhesion between the seed layer and the insulating substrate, the surface of the tape seed layer substrate was irradiated with laser light (wavelength 1064nm, beam diameter 1.6mm, output 180W) for 1 second in an inert atmosphere, and the tape seed layer substrate was heated.
Next, WSi was formed on the base material with seed layer to a thickness of 300nm by sputtering2The layer serves as a conductive layer. The conductive layer is formed on the entire main surface of the substrate with the seed layer. That is, the seed layer and the region of the main surface of the insulating base material not covered with the seed layer are covered with the conductive layer. Thus, the 1 st treated substrate was obtained.
Polysilazane was applied to the 1 st treated substrate by a spray coating method to form an insulating layer covering the seed layer and the conductive layer.
And etching the whole insulating layer by an ion milling method to expose the conductive layer on the seed layer. Further, the conductive layer on the seed layer is removed by ion milling. Thereby, the surface of the seed layer is exposed. The conductive layer and the insulating layer remain on the main surface of the insulating substrate in the region not covered with the seed layer, and the surfaces of the conductive layer and the insulating substrate are not exposed.
Using the film formation apparatus 50 shown in fig. 9 and 10, a Cu layer was formed as a metal layer on the surface of the seed layer under the following conditions.
Cathode: seed layer
Anode: oxygen-free copper wire
Solid electrolyte membrane: nafion (registered trademark) (thickness about 8 μm)
Metal solution: 1.0mol/L copper sulfate aqueous solution
Pressure pressing the solid electrolyte membrane against the seed layer: 1.0MPa
Voltage application: 0.5V
Current density: 0.23mA/cm2
Then, by using CF4The residual insulating layer and conductive layer are removed by gas capacitively coupled plasma etching. Thus, a wiring layer of a predetermined wiring pattern composed of a seed layer and a metal layer is formed on the insulating base material. Thus, a wiring board including the insulating base material and the wiring layer was obtained.
Example 7
Except that an insulating layer and a via hole covering the seed layer and the conductive layer were formed by coating epoxy acrylate on the No. 1 treatment substrate by dip coatingOver using O2/CF4A wiring board was produced in the same manner as in example 6, except that the residual insulating layer was removed by the mixed gas capacitively-coupled plasma etching.
Example 8
Except that SiO is formed on the No. 1 treated substrate by the CVD method2A wiring substrate was produced in the same manner as in example 6, except that an insulating layer covering the seed layer and the conductive layer was formed as a film.
Example 9
Except that SiO was formed on the No. 1 treated substrate by sputtering2A wiring substrate was produced in the same manner as in example 6, except that an insulating layer covering the seed layer and the conductive layer was formed as a film.
Comparative example 3
A wiring substrate was produced in the same manner as in example 6, except that the insulating layer was not formed and etched.
< evaluation of controllability of Metal deposition site >
The wiring board of comparative example 3 was observed with a microscope (magnification: 100 times). In the region other than the region corresponding to the wiring pattern, deposition of Cu was observed. That is, a Cu layer not included in the wiring layer was observed. Based on the microscopic image, the ratio of the area of the Cu layer not included in the wiring layer to the area of the region other than the region corresponding to the wiring pattern was calculated using image analysis software WinROOF. The area ratio of the Cu layer was 1%.
Similarly, the wiring boards of examples 6 to 9 were observed with a microscope. In the region other than the region corresponding to the wiring pattern, no deposition of Cu was observed.
Claims (6)
1. A method for manufacturing a wiring substrate having an insulating base material and a wiring layer having a predetermined wiring pattern provided on the insulating base material, the method comprising:
step (a), preparing a substrate with a seed layer,
the tape seed layer substrate includes:
the insulating base material has a main surface composed of a 1 st region and a 2 nd region, wherein the 1 st region has a predetermined pattern corresponding to the wiring pattern, and the 2 nd region is a region other than the 1 st region; and
a conductive seed layer disposed on the 1 st region;
a step (b) of forming a conductive layer at least on the 2 nd region to obtain a 1 st treated substrate;
a step (c) of forming an insulating layer on the 1 st process substrate, the seed layer and the conductive layer being covered with the insulating layer;
etching the insulating layer, and exposing the seed layer while leaving the insulating layer on the conductive layer on the 2 nd region to obtain a 2 nd processing substrate;
a step (e) of forming a metal layer on the surface of the seed layer,
in the step (e), a solid electrolyte membrane containing a solution containing metal ions is disposed between the 2 nd process substrate and an anode, and a voltage is applied between the anode and the seed layer while the solid electrolyte membrane is brought into pressure contact with the seed layer; and
and (f) removing the insulating layer and the conductive layer.
2. The method of manufacturing a wiring substrate according to claim 1,
after step (a) and before step (e), further comprising:
and (g) improving the adhesion between the insulating base material and the seed layer.
3. The method of manufacturing a wiring substrate according to claim 2,
said step (g) is performed before said step (b).
4. The method for manufacturing a wiring substrate according to any one of claims 1 to 3,
in the step (b), the conductive layer is formed on the 2 nd region and the seed layer.
5. The method for manufacturing a wiring substrate according to any one of claims 1 to 4,
the seed layer and the conductive layer each comprise a metal,
the metal contained in the conductive layer is easier to oxidize than the metal contained in the seed layer.
6. The method for manufacturing a wiring substrate according to any one of claims 1 to 5,
the seed layer and the conductive layer each comprise a metal,
the method for manufacturing a wiring substrate further includes, after the step (b) and before the step (e):
and (h) alloying the metal contained in the seed layer with the metal contained in the conductive layer.
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| JP2020109734A JP7306337B2 (en) | 2020-06-25 | 2020-06-25 | Wiring board manufacturing method |
| JP2020-109734 | 2020-06-25 |
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| US (1) | US11425824B2 (en) |
| JP (1) | JP7306337B2 (en) |
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| US11425824B2 (en) | 2022-08-23 |
| KR20220000361A (en) | 2022-01-03 |
| CN113853067B (en) | 2024-04-19 |
| JP7306337B2 (en) | 2023-07-11 |
| TW202203722A (en) | 2022-01-16 |
| US20210410291A1 (en) | 2021-12-30 |
| JP2022007054A (en) | 2022-01-13 |
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| KR102548962B1 (en) | 2023-06-29 |
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