CN113849187A - Quantum line noise-oriented compiling optimization method and device - Google Patents
Quantum line noise-oriented compiling optimization method and device Download PDFInfo
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Abstract
The invention provides a compiling and optimizing method and device for quantum line noise. The method comprises the following steps: constructing a quantum line to be optimized into a directed acyclic graph, and traversing the quantum line to be optimized based on a graph traversal method; and for each traversed sub-line, checking whether the sub-line meets a pattern matching rule, if so, replacing an original quantum logic gate group with higher noise in the sub-line by using a target quantum logic gate group with lower noise according to the pattern matching rule, and finally obtaining an equivalent quantum line with lower noise. The invention can effectively reduce the quantum circuit noise, improve the execution accuracy of the quantum program on a real quantum computer, and reduce the resource and time expenditure in the running process of the quantum program.
Description
Technical Field
The invention relates to the technical field of quantum computers, in particular to a compiling optimization method and device for quantum line noise.
Background
The current quantum computer development is in the NISQ (medium scale quantum computer with noise) stage, and quantum noise is a major obstacle to building large scale quantum computers. The NISQ device has severe limitations on the number of quantum bits available to the algorithm and the maximum line depth achievable.
Quantum compilation is the translation of quantum algorithms implemented in high-level quantum programming languages into executable code on quantum computers. Since quantum computers typically support a limited set of basic operations, a quantum compiler needs to compile complex quantum algorithms into the basic operations supported by the quantum computer. The quantum compiling optimization mainly studies how to reduce the total quantum gate number, the line depth and the like, and since the accuracy of the final result is affected by system noise, a compiler aiming at the NISQ equipment aims at maximizing the overall fidelity. Quantum compilation optimization is important for quantum computers, and existing quantum compilers employ many compilation optimization techniques, wherein optimization to reduce the effects of noise is achieved primarily by minimizing the number of quantum operands generated by compilation.
At present, a compiling and optimizing method which is more effective for quantum line noise is called a peephole optimizing technology. The idea of the optimization technology is as follows: the compiler finds a particular pattern for a certain sub-line in traversing the quantum line and replaces the sub-line with an equivalent sub-line with less quantum operations or shorter quantum line depth. The replacement operation is equivalent replacement, the semantics of the original quantum program is kept, and the purpose of reducing quantum noise is achieved by simplifying quantum circuits.
In a real quantum computer, different quantum logic gates have different noises, the compiling and optimizing method mainly realizes the optimization of the noise of the quantum circuit by simplifying the quantum circuit, and the method has the problems of low accuracy of the final quantum algorithm executed on the real quantum computer, high actual operation cost and high cost aiming at the problems of insufficient analysis and optimization of the noise of the quantum circuit and high noise of the generated quantum circuit.
Disclosure of Invention
Aiming at the problems of high noise and low execution accuracy of a quantum circuit generated by the current quantum compiling tool, the invention provides a compiling optimization method and device facing to the quantum circuit noise, which can improve the execution accuracy of a quantum algorithm on a real quantum computer and reduce the running expense of the quantum algorithm caused by the quantum noise.
In one aspect, the present invention provides a quantum wire noise-oriented compiling and optimizing method, including:
constructing a quantum line to be optimized into a directed acyclic graph, and traversing the quantum line to be optimized based on a graph traversal method;
and for each traversed sub-line, checking whether the sub-line meets a pattern matching rule, if so, replacing an original quantum logic gate group with higher noise in the sub-line by using a target quantum logic gate group with lower noise according to the pattern matching rule, and finally obtaining an equivalent quantum line with lower noise.
Further, the constructing the quantum wires to be optimized into a directed acyclic graph specifically includes:
the operation of the quantum logic gate on different quantum bits is used as a node of the directed acyclic graph, and the evolution relation of the state of the quantum bits is used as an edge of the directed acyclic graph, so that the whole quantum circuit to be optimized is constructed into the directed acyclic graph.
Further, a pattern matching rule is predefined in a configuration file; the pattern matching rule refers to that an original quantum logic gate group to be replaced and a target quantum logic gate group are used as rules in a replacement process, the original quantum logic gate group to be replaced and the target quantum logic gate group are in an equivalent relation, and the noise of the target quantum logic gate group is smaller than that of the original quantum logic gate group to be replaced.
Further, the target quantum logic gate set with lower noise is used to replace the original quantum logic gate set with higher noise in the sub-line, and finally the equivalent quantum line with lower noise is obtained, specifically:
deleting the original quantum logic gate group for each sub-line according with the pattern matching rule, inserting a target quantum logic gate group in a corresponding position, and regenerating the sub-line;
and finally obtaining the equivalent quantum circuit with lower noise after traversing and replacing all the sub-circuits which accord with the pattern matching rule.
In another aspect, the present invention provides a quantum wire noise-oriented coding optimization apparatus, including:
the quantum line traversal module is used for constructing the quantum line to be optimized into a directed acyclic graph and traversing the quantum line to be optimized based on a graph traversal method;
and the quantum line noise optimization module is used for checking whether the sub-line accords with the pattern matching rule or not aiming at each traversed sub-line, and if so, replacing the original quantum logic gate group with higher noise in the sub-line by using the target quantum logic gate group with lower noise according to the pattern matching rule, thereby finally obtaining the equivalent quantum line with lower noise.
Further, the constructing the quantum wires to be optimized into a directed acyclic graph specifically includes:
the operation of the quantum logic gate on different quantum bits is used as a node of the directed acyclic graph, and the evolution relation of the state of the quantum bits is used as an edge of the directed acyclic graph, so that the whole quantum circuit to be optimized is constructed into the directed acyclic graph.
Further, the quantum wire noise optimization module is further configured to predefine a pattern matching rule in a configuration file; the pattern matching rule refers to that an original quantum logic gate group to be replaced and a target quantum logic gate group are used as rules in a replacement process, the original quantum logic gate group to be replaced and the target quantum logic gate group are in an equivalent relation, and the noise of the target quantum logic gate group is smaller than that of the original quantum logic gate group to be replaced.
Further, the target quantum logic gate set with lower noise is used to replace the original quantum logic gate set with higher noise in the sub-line, and finally the equivalent quantum line with lower noise is obtained, specifically:
deleting the original quantum logic gate group for each sub-line according with the pattern matching rule, inserting a target quantum logic gate group in a corresponding position, and regenerating the sub-line;
and finally obtaining the equivalent quantum circuit with lower noise after traversing and replacing all the sub-circuits which accord with the pattern matching rule.
The invention has the beneficial effects that:
the invention provides a compiling optimization method and a device for quantum line noise, which adopt a quantum line traversal method based on a graph and a quantum line noise optimization method based on pattern matching in the compiling process of a quantum program, namely: firstly, the quantum wires are regarded as directed acyclic graphs, and then the quantum wires are traversed in a graph traversal mode; and then, according to the principle that quantum logic gates can be mutually converted, in the process of traversing the quantum circuit, based on a pattern matching rule, equivalently replacing the quantum logic gate group with higher noise with the quantum logic gate group with lower noise, thereby obtaining the quantum circuit which is equivalent to the original quantum circuit and has lower noise, achieving the purpose of reducing the noise of the whole quantum circuit in the compiling process, effectively reducing the noise of the quantum circuit, improving the execution accuracy of the quantum program on a real quantum computer, and reducing the resource and time overhead in the running process of the quantum program.
Drawings
Fig. 1 is a schematic flowchart of a quantum wire noise-oriented compiling and optimizing method according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a quantum wire noise-oriented compiling and optimizing apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
As shown in fig. 1, an embodiment of the present invention provides a method for compiling and optimizing quantum wire noise, including the following steps:
s101: constructing a quantum line to be optimized into a directed acyclic graph, and traversing the quantum line to be optimized based on a graph traversal method;
specifically, the constructing a quantum wire to be optimized into a directed acyclic graph specifically includes: the operation of the quantum logic gate on different quantum bits is used as a node of the directed acyclic graph, and the evolution relation of the state of the quantum bits is used as an edge of the directed acyclic graph, so that the whole quantum circuit to be optimized is constructed into the directed acyclic graph.
Traversing the quantum line to be optimized based on a graph traversal method, specifically: after the quantum circuit to be optimized is abstracted into the directed acyclic graph, the traversal process of the quantum circuit is the traversal process of the graph, and the traversal problem of the sub-circuit in the quantum circuit is the finding problem of the subgraph in the graph. In the compiling process of the quantum wire, the whole quantum wire is traversed by adopting a graph traversal mode.
S102: and for each traversed sub-line, checking whether the sub-line meets a pattern matching rule, if so, replacing an original quantum logic gate group with higher noise in the sub-line by using a target quantum logic gate group with lower noise according to the pattern matching rule, and finally obtaining an equivalent quantum line with lower noise.
Specifically, a pattern matching rule is predefined in a configuration file; the pattern matching rule refers to that an original quantum logic gate group to be replaced and a target quantum logic gate group are used as rules in a replacement process, the original quantum logic gate group to be replaced and the target quantum logic gate group are in an equivalent relation, and the noise of the target quantum logic gate group is smaller than that of the original quantum logic gate group to be replaced.
During traversal of the quantum wire, an equivalent replacement of the set of quantum logic gates in the quantum wire is implemented based on the defined pattern matching rules. The equivalent replacement process comprises deletion of the original quantum logic gate group and insertion of the target quantum logic gate group, and in order to ensure the correctness of the replaced quantum circuit, a method for regenerating the quantum circuit is adopted, namely: the method comprises the following steps of replacing the original quantum logic gate group with higher noise in the sub-line by the target quantum logic gate group with lower noise to finally obtain the equivalent quantum line with lower noise, wherein the steps are as follows: deleting the original quantum logic gate group for each sub-line according with the pattern matching rule, inserting a target quantum logic gate group in a corresponding position, and regenerating the sub-line; and finally obtaining the equivalent quantum circuit with lower noise after traversing and replacing all the sub-circuits which accord with the pattern matching rule.
Example 2
As shown in fig. 2, an embodiment of the present invention provides a quantum wire noise-oriented compiling and optimizing apparatus, including: quantum wire ergodic module and quantum wire noise optimizing module; wherein:
the quantum line traversal module is used for constructing the quantum line to be optimized into a directed acyclic graph, and traversing the quantum line to be optimized based on a graph traversal method. The quantum circuit noise optimization module is used for checking whether each traversed sub-circuit accords with a pattern matching rule or not, if so, replacing an original quantum logic gate group with higher noise in the sub-circuit by using a target quantum logic gate group with lower noise according to the pattern matching rule, and finally obtaining an equivalent quantum circuit with lower noise; in addition, the quantum wire noise optimization module is also used for predefining a pattern matching rule in a configuration file; the pattern matching rule refers to that an original quantum logic gate group to be replaced and a target quantum logic gate group are used as rules in a replacement process, the original quantum logic gate group to be replaced and the target quantum logic gate group are in an equivalent relation, and the noise of the target quantum logic gate group is smaller than that of the original quantum logic gate group to be replaced.
As an implementation manner, the constructing the quantum wire to be optimized as a directed acyclic graph specifically includes: the operation of the quantum logic gate on different quantum bits is used as a node of the directed acyclic graph, and the evolution relation of the state of the quantum bits is used as an edge of the directed acyclic graph, so that the whole quantum circuit to be optimized is constructed into the directed acyclic graph.
As an implementable manner, the target quantum logic gate set with lower noise is used to replace the original quantum logic gate set with higher noise in the sub-line, and finally the equivalent quantum line with lower noise is obtained, specifically:
deleting the original quantum logic gate group for each sub-line according with the pattern matching rule, inserting a target quantum logic gate group in a corresponding position, and regenerating the sub-line; and finally obtaining the equivalent quantum circuit with lower noise after traversing and replacing all the sub-circuits which accord with the pattern matching rule.
Compared with the prior quantum compiling optimization technology, the invention adopts the quantum circuit noise optimization method based on the mode matching, so that the noise of the quantum logic gate in the optimized quantum circuit is reduced, the execution accuracy of the quantum algorithm on a real quantum computer is improved, and the operation expense of the quantum algorithm is reduced.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (8)
1. The compiling optimization method facing quantum line noise is characterized by comprising the following steps:
constructing a quantum line to be optimized into a directed acyclic graph, and traversing the quantum line to be optimized based on a graph traversal method;
and for each traversed sub-line, checking whether the sub-line meets a pattern matching rule, if so, replacing an original quantum logic gate group with higher noise in the sub-line by using a target quantum logic gate group with lower noise according to the pattern matching rule, and finally obtaining an equivalent quantum line with lower noise.
2. The method for quantum wire noise-oriented compilation optimization according to claim 1, wherein the constructing the quantum wire to be optimized as a directed acyclic graph specifically comprises:
the operation of the quantum logic gate on different quantum bits is used as a node of the directed acyclic graph, and the evolution relation of the state of the quantum bits is used as an edge of the directed acyclic graph, so that the whole quantum circuit to be optimized is constructed into the directed acyclic graph.
3. The method of claim 1, wherein a pattern matching rule is predefined in a configuration file; the pattern matching rule refers to that an original quantum logic gate group to be replaced and a target quantum logic gate group are used as rules in a replacement process, the original quantum logic gate group to be replaced and the target quantum logic gate group are in an equivalent relation, and the noise of the target quantum logic gate group is smaller than that of the original quantum logic gate group to be replaced.
4. The method for compiling and optimizing quantum wire noise according to claim 1, wherein the target quantum logic gate set with lower noise is used to replace the original quantum logic gate set with higher noise in the sub-wire, so as to obtain the equivalent quantum wire with lower noise, specifically:
deleting the original quantum logic gate group for each sub-line according with the pattern matching rule, inserting a target quantum logic gate group in a corresponding position, and regenerating the sub-line;
and finally obtaining the equivalent quantum circuit with lower noise after traversing and replacing all the sub-circuits which accord with the pattern matching rule.
5. A quantum-line-noise-oriented coding optimization apparatus, comprising:
the quantum line traversal module is used for constructing the quantum line to be optimized into a directed acyclic graph and traversing the quantum line to be optimized based on a graph traversal method;
and the quantum line noise optimization module is used for checking whether the sub-line accords with the pattern matching rule or not aiming at each traversed sub-line, and if so, replacing the original quantum logic gate group with higher noise in the sub-line by using the target quantum logic gate group with lower noise according to the pattern matching rule, thereby finally obtaining the equivalent quantum line with lower noise.
6. The apparatus for quantum wire noise-oriented coding optimization according to claim 5, wherein the constructing the quantum wire to be optimized as a directed acyclic graph specifically comprises:
the operation of the quantum logic gate on different quantum bits is used as a node of the directed acyclic graph, and the evolution relation of the state of the quantum bits is used as an edge of the directed acyclic graph, so that the whole quantum circuit to be optimized is constructed into the directed acyclic graph.
7. The quantum wire noise-oriented compiling and optimizing device of claim 5 wherein the quantum wire noise optimizing module is further configured to pre-define a pattern matching rule in a configuration file; the pattern matching rule refers to that an original quantum logic gate group to be replaced and a target quantum logic gate group are used as rules in a replacement process, the original quantum logic gate group to be replaced and the target quantum logic gate group are in an equivalent relation, and the noise of the target quantum logic gate group is smaller than that of the original quantum logic gate group to be replaced.
8. The apparatus for compiling and optimizing quantum wire noise according to claim 5, wherein the target quantum logic gate set with lower noise is used to replace the original quantum logic gate set with higher noise in the sub-wire, so as to obtain the equivalent quantum wire with lower noise, specifically:
deleting the original quantum logic gate group for each sub-line according with the pattern matching rule, inserting a target quantum logic gate group in a corresponding position, and regenerating the sub-line;
and finally obtaining the equivalent quantum circuit with lower noise after traversing and replacing all the sub-circuits which accord with the pattern matching rule.
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