CN116414396A - LLVM (logical level virtual machine) target definition file generation method and device and electronic equipment - Google Patents

Abstract

The invention discloses a method, a device and electronic equipment for generating a target definition file of LLVM, wherein the method comprises the following steps: reading each basic operation instruction in an external target platform information table; adding a type field and a condition field according to the first description information as a basis operation instruction; converting the basic operation instruction added with the field into a mode statement according to the second description information; the pattern statement is entered into the target definition file. The technical scheme provided by the invention realizes the function that the LLVM target definition file can be accurately and automatically generated.

Description

LLVM (logical level virtual machine) target definition file generation method and device and electronic equipment

Technical Field

The invention relates to the field of computer instruction compiling, in particular to a target definition file generation method and device of LLVM and electronic equipment.

Background

LLVM (Low Level Virtual Machine, low-level virtual machine) is a compiler infrastructure framework that contains a series of modular compiler components and tool chains to develop the compiler front-end and back-end. It provides a suite of intermediate languages (Intermediate Representation, IR) suitable for compiler systems, around which a large number of transformations and optimizations are implemented. The code instruction of the programmer can be converted into an intermediate language, and then the intermediate language after transformation and optimization is converted into the assembly language code related to the target platform. To implement these transformations, a large number of files of the LLVM-capable target definition (target definition, td) are written, where the files are in the format of td, describing the instructions supported by the target platform and the correspondence between the instructions describing the target platform and the LLVM intermediate language (after the intermediate language is input into the LLVM, the LLVM is transformed and optimized to split the intermediate language code into several basic blocks, where the basic blocks are all linearly executed codes, i.e. only the program of the segment can be entered from the beginning of the program of the segment, no other program can jump into the program of the segment Duan Xu, only the program of the segment can be exited from the last row of the program of the segment, no other program in the middle can jump out of the program of the segment, then the basic blocks are converted into a selective acyclic graph, i.e. the SelectionDAG, which is an expression form for the basic block graph, where the dependency of the instructions can be more easily represented, and the correspondence between the instructions of the target platform and the LLVM intermediate language is the relationship represented by the combination of one or more nodes in the selective acyclic graph. In popular terms, the working principle of the target platform (such as the CPU manufactured by each manufacturer) is recorded in the target definition file, so that the LLVM can convert the programmer code converted into the intermediate language into the assembly language conforming to the working principle of the target platform according to the target definition file. The current task of generating the target definition file is completed by manual writing, which requires a lot of manpower and time, so how to automatically and accurately generate the target definition file, thereby reducing the cost of manpower and time is a problem to be solved urgently.

Disclosure of Invention

In view of this, the embodiment of the invention provides a method, a device and an electronic device for generating an object definition file of an LLVM, so as to realize the function of accurately and automatically generating the object definition file of the LLVM.

According to a first aspect, the present invention provides a method for generating an object definition file of LLVM, the method comprising: reading each basic operation instruction in an external target platform information table, wherein the external target platform information table comprises first description information for describing instruction forms supported by a target platform and second description information for describing corresponding relations between each instruction form and nodes in a selective directed acyclic graph, and the basic operation instruction is used for representing instruction operation actions supported by the target platform; adding a type field and a condition field for the basic operation instruction according to the first description information, wherein the type field is used for representing operand types supported by the basic operation instruction, and the condition field is used for representing whether the basic operation instruction supports conditional execution or not; converting the basic operation instruction added with the field into a mode statement according to the second description information, wherein the mode statement is used for matching with the nodes in the selective directed acyclic graph; and inputting the mode statement into a target definition file.

Optionally, before the converting the basic operation instruction added with the field into the mode statement according to the second description information, the method further includes: binary coding is carried out on the basic operation instruction added with the field according to the first description information; and adding an implicit state register field and instruction stream information for the basic operation instruction after the addition field according to the first description information, wherein the implicit state register field is used for representing a state register implicitly defined and used by the basic operation instruction, and the instruction stream information is used for representing a scheduling process of the target platform hardware when the instruction runs.

Optionally, the reading each basic operation instruction in the external target platform information table includes: reading operation names supported by a target platform recorded in the first description information and operands corresponding to the operation names; and splicing each operation name and the corresponding operand into each basic operation instruction.

Optionally, adding a condition field to the basic operation instruction according to the first description information includes: determining whether the base operation instruction supports conditional execution based on the first description information; and if the basic operation instruction supports conditional execution, adding a condition register field and/or a condition register switch field to the basic operation instruction based on condition logic supported by the basic operation instruction, wherein the condition logic is used for representing whether a corresponding condition state value is true or false when the basic operation instruction is executed.

Optionally, the converting the basic operation instruction with the added field into a mode statement according to the second description information includes: determining whether the basic operation instruction is an operation for a vector according to the first description information; if the judgment result is yes, counting all vector data types supported by the basic operation instruction through vector register digit of the target platform and a type field of the basic operation instruction; and converting the basic operation instruction into a plurality of corresponding mode sentences under the condition of each vector data type according to the second description information.

Optionally, the counting, by the vector register bit number of the target platform and the type field of the base operation instruction, all vector data types supported by the base operation instruction includes: calculating the ratio of the number of bits of the vector register to the number of bits of the type field to obtain the maximum number of elements of the vector supported by the basic operation instruction; traversing all target values to the power n of 2 in the maximum element number, and counting vector data types corresponding to the target values to obtain all the vector data types, wherein n is a positive integer.

Optionally, the converting the basic operation instruction with the added field into a mode statement according to the second description information further includes: and if the basic operation instruction supports conditional execution, combining the mode statement with a selection statement and/or a vector selection statement to generate a second mode statement supporting conditional execution, wherein the selection statement and the vector selection statement are statements for condition judgment in an intermediate language of the LLVM.

According to a second aspect, the present invention provides an object definition file generating apparatus of LLVM, the apparatus comprising: the system comprises a basic instruction generation module, a target platform information table and a target platform information table, wherein the basic instruction generation module is used for reading each basic operation instruction in the external target platform information table, the external target platform information table comprises first description information for describing instruction forms supported by the target platform and second description information for describing the corresponding relation between each instruction form and a node in a selected directed acyclic graph, and the basic operation instruction is used for representing instruction operation actions supported by the target platform; a field adding module, configured to add a type field and a condition field to the basic operation instruction according to the first description information, where the type field is used to characterize an operand type supported by the basic operation instruction, and the condition field is used to characterize whether the basic operation instruction supports conditional execution; the mode conversion module is used for converting the basic operation instruction added with the field into a mode statement according to the second description information, and the mode statement is used for matching with the node in the selective directed acyclic graph; and the input file module is used for inputting the mode statement into the target definition file.

According to a third aspect, an embodiment of the present invention provides an electronic device, including: the system comprises a memory and a processor, wherein the memory and the processor are in communication connection, the memory stores computer instructions, and the processor executes the computer instructions, thereby executing the method in the first aspect or any optional implementation manner of the first aspect.

According to a fourth aspect, embodiments of the present invention provide a computer readable storage medium storing computer instructions for causing the computer to perform the method of the first aspect, or any one of the alternative embodiments of the first aspect.

The technical scheme that this application provided has following advantage:

according to the technical scheme, an external target platform information table equivalent to a target platform technical manual is firstly obtained, and first description information for describing instruction forms supported by a target platform and second description information of corresponding relations between the instruction forms and nodes in a selective directed acyclic graph are recorded in the table. And summarizing all basic operation instructions supported by the target platform and representing operation actions based on the first description information, determining the data types supported by each basic operation instruction and whether the execution of conditions is supported according to the records in the first description information, correspondingly adding an upper type field and a condition field for the basic operation instruction, converting the basic operation instruction into a plurality of mode sentences according to the corresponding relation between the basic operation instruction recorded in the second description information and one or more nodes in the selected directed acyclic graph, inputting the mode sentences into a target definition file, ensuring that the relation between the instructions defined by the target platform and the intermediate languages can be accurately, reliably and completely saved in the target definition file, enabling the target definition file to be automatically generated, saving manual writing steps, enabling LLVM to traverse each mode sentence in the target definition file during compiling, determining the node of the selected directed acyclic graph, matching the intermediate language corresponding to a certain section of program developed by a developer with one or more mode sentences, and converting the intermediate language into the instructions of the target platform according to the mode sentence specification form.

In addition, in another embodiment, the basic operation instruction added with the type field and the condition field is binary coded, and the implicit state register field and the instruction stream information are added for the basic operation instruction added with the field according to the first description information, so that the function of converting the intermediate language into the assembly language is realized, and the intermediate language can be converted into the binary language which can be directly recognized by a machine. Based on the target definition file automatically generated in the embodiment, the compiling efficiency of the compiler is further improved.

Drawings

The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings, which are illustrative and should not be construed as limiting the invention in any way, in which:

FIG. 1 is a schematic diagram showing steps of a method for generating a target definition file of LLVM according to an embodiment of the present invention;

FIG. 2 is a flow chart of a method for generating a destination definition file of LLVM according to an embodiment of the present invention;

FIG. 3 is a schematic flow chart of a method for generating a destination definition file of LLVM according to one embodiment of the present invention;

FIG. 4 is a schematic flow chart showing the execution of the judgment condition of the LLVM goal definition file generation method according to one embodiment of the present invention;

FIG. 5 is a schematic diagram showing a structure of a device for generating a target definition file of LLVM according to an embodiment of the present invention;

fig. 6 shows a schematic structural diagram of an electronic device according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, based on the embodiments of the invention, which a person skilled in the art would obtain without making any inventive effort, are within the scope of the invention.

Referring to fig. 1 and fig. 2, in one embodiment, a method for generating an object definition file of LLVM specifically includes the following steps:

step S101: reading each basic operation instruction in an external target platform information table, wherein the external target platform information table comprises first description information for describing instruction forms supported by a target platform and second description information of corresponding relations between each instruction form and nodes in a selective directed acyclic graph, and the basic operation instruction is used for representing instruction operation actions supported by the target platform;

Step S102: adding a type field and a condition field for the basic operation instruction according to the first description information, wherein the type field is used for representing the operand type supported by the basic operation instruction, and the condition field is used for representing whether the basic operation instruction supports conditional execution or not;

step S103: converting the basic operation instruction added with the field into a mode statement according to the second description information, wherein the mode statement is used for matching with the nodes in the selective directed acyclic graph;

step S104: the pattern statement is entered into the target definition file.

Specifically, the external target platform information table contains first description information for describing the instruction form (table entries are respectively assembly form character strings, operation codes, operands) of all target platforms supported by the target platform, and second description information of the corresponding relation between each target platform instruction and the selected directed acyclic graph (basically can be regarded as an intermediate language), the target platform information table is basically equivalent to the electronic form of the technical manual of the target platform, and the target platform instructions of scalar and vector are respectively defined through the two tables, wherein the assembly form character strings, the operation codes, the operands of the instructions and the corresponding relation with the IR are included. And then, all information recorded in an external target platform information table is accurately and completely input into a target definition file through three-step information extraction and information matching, so that manual operation is avoided. First, each basic operation instruction used for representing the instruction operation action supported by the target platform in the external target platform information table is read, wherein the instruction does not include type information and conditional execution information, but only includes operands and operation codes, for example: the assembled form of the basic operation instruction of one addition instruction is addrs 0 rs1, meanwhile, if the addition instruction with 32-bit floating point number data type information is add.f32rd rs0 rs1, the instruction is indicated to be the addition instruction of 32-bit floating point number, the addition instruction executed under the same condition is add.pprdrs 0 rs1, wherein pp represents a condition register, and the execution time of the instruction is judged according to the numerical value in pp. In this embodiment, a corresponding AsmString field (an instruction class attribute in an LLVM object definition file, which is used to describe a target platform instruction assembly language format) is first generated according to an instruction name and each operand name, so as to form a basic operation instruction. For example: for a floating point addition instruction add.f32.pp rd rs0 rs1 with conditional execution recorded in the first description information, firstly, according to the instruction name, enabling asmstring= "add", then according to the operand name, adding operand information, at this time, asmstring= "add rd rs0 rs1", then sequentially judging the operand type of the instruction, for example: and sequentially judging whether the instruction supports f16, f32, i8, i16, i32 and the like, and generating a basic operation instruction with a corresponding type field if the instruction is of a supported data type. And finally judging whether the instruction supports conditional execution according to the recorded content in the first description information, thereby adding a condition field into the instruction. The gradual automatic, accurate and complete generation of instruction information is ensured.

Then, the basic operation instruction added with the field is converted into a mode statement according to the second description information, for example: (add b, c) represents a mode of addition, (add (mul b, c), d) represents a combination of multiplication and addition, and belongs to a mode, and LLVM can replace the mode of addition with target platform instruction addrs 0 rs0 according to the definition of target platform mode statement (Pattern); and replacing a multiply-add mode by a multiply target platform instruction muladdrrs 0 rs1 rs2 (representing rd=r0+r1×r2), wherein a mode statement is a combination of single or multiple selective directed acyclic graph nodes in the LLVM, the purpose of creating the mode statement is to correspond an intermediate language to the target platform instruction, so that the LLVM can match the intermediate language of a specific combination with the mode statement, and if the mode statement is matched with the corresponding mode statement, the intermediate language instruction of the specific combination is replaced by the target platform instruction. In this embodiment, the specific implementation is that the pats are used to describe the correspondence in the code, taking multiply add as an example: the def Pat < (add rs0, (mul rs1, rs 3)), (mul rs0, rs1, rs 2) >, the sentence is a pattern sentence, a large number of other pattern sentences which are the same as the pattern sentence in application are input into the target definition file, an accurate and complete target definition file can be obtained, the accurate, complete and complete target definition file containing all instruction information of the target platform is automatically generated through the three steps of the foundation, the type and the condition, the labor cost is reduced, and the LLVM can complete the functions of searching patterns and replacing.

Specifically, as shown in fig. 3, in an embodiment, before the step S103, a LLVM object definition file generating method further includes the following steps:

step one: and binary encoding is carried out on the basic operation instruction added with the field according to the first description information.

Step two: and adding an implicit state register field and instruction flow information for the basic operation instruction with the added field according to the first description information, wherein the implicit state register field is used for representing a state register implicitly defined and used by the basic operation instruction, and the instruction flow information is used for representing a scheduling process of the target platform hardware when the instruction runs.

Specifically, in this embodiment, in order to further improve the efficiency of compiling by the compiler, in addition to the necessary fields of the assembly language instruction being added to the target definition file, the necessary fields for converting the intermediate language into the binary language are added to the target definition file, so that the compiler compiles the intermediate language according to the target definition file provided by this embodiment, not only the assembly language instruction but also the binary language instruction can be obtained. Firstly, binary encoding is performed on the basic operation instruction processed in the previous embodiment to determine binary layout information, for example: instruction binary layout information is defined and the Inst field (i.e., binary field used to describe the target platform instruction binary format) is initialized. Inst {31-28} = rd, inst {27-24} = rs0, inst {23-20} = rs1, inst {7-0} = 13, indicating encoded information for the "add rd rs0 rs1" instruction, where binary encoded 31-28 bits are used to represent the relevant operation and state of register rd, and 27-24 bits are used to represent register rs0, and so on. An implicit status register field is then added to the base operation instruction, for example: intermediate results of execution of an instruction may be stored in or read from a default register, with some registers being implicit, defined by default, or used, while the developer knows that the information is implicitly known at programming time, the computer needs to inform the implicit information when executing binary language to enable the machine to read from or write to the default register, thus requiring the addition of implicit status register fields. And finally, adding an instruction pipeline information field on the basic operation instruction, so that the target platform can divide the operation of one instruction into a plurality of tiny steps through the instruction pipeline information, and each step is completed by a special circuit. In this embodiment, the added instruction pipeline information includes the number of instruction cycles required for executing an instruction of an entry mark platform, the input register is read in the number of cycles, the output register is written in the number of cycles, and in order to complete the function of the instruction, specific hardware resources in the chip need to be occupied, the duration is occupied, and detailed records such as occupation start from the number of cycles are recorded, so that it is ensured that the target definition file generated by this embodiment can be accurately converted into the binary language corresponding to the intermediate language. Through the steps, the addition of all binary information is completed, so that the compiler compiles intermediate languages according to the target definition file provided by the embodiment, not only can assembly language instructions be obtained, but also binary language instructions can be obtained, and the efficiency and the application range of the compiler are improved.

Specifically, in this embodiment, the step S101 specifically includes the following steps:

step three: and reading the operation names supported by the target platform recorded in the first description information, and the operation names correspond to the operands.

Step four: and splicing each operation name and the corresponding operand into each basic operation instruction.

Specifically, in the step of reading each basic operation instruction in the external target platform information table, the complete basic operation instruction is obtained twice, and reference may be made to the descriptions of steps S101 to S104, for example: according to the instruction name, asmstring= "add", then according to the operand name, adding operand information, at this time asmstring= "add rd rs0 rs1". Therefore, detailed information recorded in an external target platform information table is completely and accurately read, the accuracy of automatically generating the target definition file is improved, the labor cost is reduced, the generation efficiency of the target definition file is improved, and the information loss and confusion of records in the target definition file caused by manual writing are avoided.

Specifically, as shown in fig. 4, in an embodiment, the step of adding the condition field in the step S102 includes:

Step five: it is determined whether the base operation instruction supports conditional execution based on the first description information.

Step six: if the basic operation instruction supports conditional execution, a condition register field and/or a condition register switch field are added to the basic operation instruction based on condition logic supported by the basic operation instruction, wherein the condition logic is used for representing whether a corresponding condition state value is true or false when the basic operation instruction is executed.

Specifically, for each basic operation instruction, it is first required to determine whether the instruction supports conditional execution according to the first description information, and if so, it is further required to determine whether the supported conditional logic of the instruction is positive or negative, so-called positive: when the value in the condition register is true, i.e. 1, the current instruction is executed, and when the value in the condition register is false, i.e. 0, the current instruction is not executed, and the logic of negative execution is opposite to the logic of positive execution. In this embodiment, the field to be added by the basic operation instruction that is executed positively is a condition register, and the basic operation instruction that is executed negatively needs to invert the condition register field by adding a condition register switch field, for example: taking the basic instruction add rd rs0 rs1 as an example, if the target platform supports conditional execution and the condition register is called pp, then add pp rd rs0 rs1 represents an add instruction with conditional execution, when the value in pp is 1, the sum of rs0+rs1 is stored into rd, otherwise, the instruction is not executed, and the value of rd remains unchanged. The instruction can be executed when pp is 1 or 0 by the condition register switch. By way of example above, adding a "condition register switch" to an instruction, add 1pp rd rs0 rs1, with a newly added 1 indicating that the function of the instruction is the same as that of the instruction in the example above, and if a 0 is written, then the instruction becomes add 0pp rd rs0 rs1, and the corresponding condition logic indicates that when the value in pp is 0, the instruction stores the sum of rs0+ rs1 into rd, otherwise the value of rd remains unchanged without executing the instruction. In this embodiment, for any one basic operation instruction, if the instruction supports both positive execution and negative execution, a condition register field and a condition register switch field are added corresponding to two cases, so as to generate two different instructions, so that the target definition file includes all the forms of the instruction supported by the target platform, and accuracy of the target definition file is improved.

In addition, in this embodiment, in addition to the scalar instruction, the vector instruction is processed, if the target platform instruction supports the conditional execution of the vector element, the conditional execution information is added to the basic operation instruction, so as to generate the conditional execution instruction with the vector condition, where the additional fields are a vector condition register and a vector condition register switch, and the addition principle is the same as that of the scalar, and the description is omitted herein.

Specifically, in one embodiment, the step S103 specifically includes the following steps:

step seven: it is determined whether the base operation instruction is an operation performed on the vector based on the first description information.

Step eight: if the judgment result is yes, calculating all vector data types supported by the statistics basic operation instruction through vector register digit of the target platform and a type field of the basic operation instruction.

Step nine: and converting the basic operation instruction into a plurality of corresponding mode sentences under the condition of different vector data types according to the second description information.

Specifically, the mode statements of the LLVM are of a type, and different data types supported by operands of the instruction belong to different mode statements. For example: the pattern statement of addition (add a, b), 32-bit addition and 8-bit addition are different pattern statements, i32 represents a 32-bit integer, i8 represents an 8-bit integer, the addition pattern statement of i32 is (add (i 32 a), (i 32 b)), and the addition pattern statement of i8 is (add (i 8 a), (i 8 b)). Meanwhile, the addition of the vector and the scalar also belongs to different pattern sentences, and the same vector, and the number of vector elements (for example, the number of vector a [1,2,3,4] elements is 4, and the number of vector a [1,2] elements is 2) also belongs to different pattern sentences. Therefore, different vector data types need to be calculated for different vector element numbers, and then mode sentences are converted for the vector data types. The vector data type is related to the number of bits of the vector register of the type field and the target platform, and the longer the number of bits of the vector register, the more vector data types are supported, in this embodiment, the vector data type is calculated by the ratio of the number of bits of the vector register to the number of bits of the type field, and the specific calculation steps are as follows:

1. And calculating the ratio of the number of bits of the vector register to the number of bits of the type field to obtain the maximum number of elements of the vector supported by the basic operation instruction.

2. Traversing all target values to the power n of 2 in the maximum element number, and counting vector data types corresponding to the target values to obtain all vector data types, wherein n is a positive integer.

Firstly, all data types supported by basic operation instructions with fields added are acquired, a data format list is generated and used for recording all data types supported by each basic operation instruction, then the ratio of the number of vector register bits to the number of data types is calculated to obtain the maximum number of vector elements supported, then all data (because binary system is adopted, all instructions and data are binary coded, the number of vector elements of the instructions and data to be represented by n bits is required to be n times of 2) of all 2 contained in the maximum number of elements are calculated, and then all corresponding vector data types can be obtained, and then a pattern statement corresponding to all vector data types is generated.

For example: an integer vector is denoted by v { x } i { y } and represents that the vector element type is an integer of y bits, the vector containing x elements, say v4i16 represents that the vector is a vector of 16 bit integers of 4 elements. If the target platform vector register is 512 bits, and assuming that the data type supported by an addition basic operation instruction is an i16 data vector, the maximum element number of the vector supported by the instruction is 512/16=32, that is, the vector data type of the maximum element number is v32i16, and the vector data type of the minimum element number is v2i16, all i16 type vectors that can be processed by the target platform include { v2i16, v4i16, v8i16, v16i16, v32i16}, and all pattern statements of vector addition are:

(add(v2i16 a),(v2i16 b))

(add(v4i16 a),(v4i16 b))

(add(v8i16 a),(v8i16 b))

(add(v16i16 a),(v16i16 b))

(add(v32i16 a),(v32i16 b))

The operation instructions after adding the fields corresponding to the 5 mode sentences are vadd.i16rd rs0rs1, and the above 5 mode sentences are required to be stored for the instruction in the target definition file, so that the intermediate language can be ensured to accurately convert the sentences under any condition. And (3) through the processing from the step seven to the step nine, finding out all the mode sentences corresponding to the basic operation instructions after each field is added. All instruction information supported by the target platform is completely stored in the target definition file, so that the error of a compiler in compiling is avoided, and the compiling accuracy is ensured.

Specifically, in an embodiment, the step S103 further includes:

step ten: if the basic operation instruction supports conditional execution, combining the mode statement with a selection statement and/or a vector selection statement to generate a second mode statement supporting conditional execution, wherein the selection statement and the vector selection statement are statements for condition judgment in an intermediate language of the LLVM. Specifically, the selection statement (select statement) is an instruction in the LLVM intermediate language, and has three parameters, the first parameter is a bool type, when the first parameter is 1, the instruction returns the value of the second parameter (the second parameter has the current instruction, i.e. the current instruction is executed), otherwise returns the value of the third parameter (the third parameter is null, i.e. no operation), the vector selection statement (vselect statement) is a vector version of the vector selection statement, and when the basic operation instruction supports conditional execution, the generated mode statement also needs to correspondingly generate the mode statement with conditional execution logic to ensure the consistency of the mode statement and the instruction supported by the target platform. If the conditional logic is negative, the last two parameters of the selection statement or the vector selection statement are exchanged.

Through the steps, the technical scheme provided by the application firstly obtains an external target platform information table which is equivalent to a target platform technical manual, and the table is recorded with first description information for describing instruction forms supported by the target platform and second description information of corresponding relations between the instruction forms and nodes in the selective directed acyclic graph. And summarizing all basic operation instructions supported by the target platform and representing operation actions based on the first description information, determining the data types supported by each basic operation instruction and whether the execution of conditions is supported according to the records in the first description information, correspondingly adding an upper type field and a condition field for the basic operation instruction, converting the basic operation instruction into a plurality of mode sentences according to the corresponding relation between the basic operation instruction recorded in the second description information and one or more nodes in the selected directed acyclic graph, inputting the mode sentences into a target definition file, ensuring that the relation between the instructions defined by the target platform and the intermediate languages can be accurately, reliably and completely saved in the target definition file, enabling the target definition file to be automatically generated, saving manual writing steps, enabling LLVM to traverse each mode sentence in the target definition file during compiling, determining the node of the selected directed acyclic graph, matching the intermediate language corresponding to a certain section of program developed by a developer with one or more mode sentences, and converting the intermediate language into the instructions of the target platform according to the mode sentence specification form.

In addition, in another embodiment, the basic operation instruction added with the type field and the condition field is binary coded, and the implicit state register field and the instruction stream information are added for the basic operation instruction added with the field according to the first description information, so that the function of converting the intermediate language into the assembly language is realized, and the intermediate language can be converted into the binary language which can be directly recognized by a machine. Based on the target definition file automatically generated in the embodiment, the compiling efficiency of the compiler is further improved.

Therefore, the automatically generated target definition file provided by the embodiment of the invention greatly improves the development efficiency of the compiler and the richness of the mode sentences while reducing the manual writing workload, so that the search range for optimizing the instructions can be enlarged and the code performance compiled by the compiler can be improved.

As shown in fig. 5, this embodiment further provides a device for generating an object definition file of LLVM, which is characterized in that the device includes:

the basic instruction generating module 101 is configured to read each basic operation instruction in an external target platform information table, where the external target platform information table includes first description information for describing an instruction form supported by the target platform, and second description information corresponding to a node in the selective directed acyclic graph in each instruction form, where the basic operation instruction is used to characterize an instruction operation action supported by the target platform. For details, refer to the related description of step S101 in the above method embodiment, and no further description is given here.

The field adding module 102 is configured to add, to the base operation instruction, a type field and a condition field according to the first description information, where the type field is used to characterize an operand type supported by the base operation instruction, and the condition field is used to characterize whether the base operation instruction supports conditional execution. For details, refer to the related description of step S102 in the above method embodiment, and no further description is given here.

The mode conversion module 103 is configured to convert the basic operation instruction with the field added into a mode statement according to the second description information, where the mode statement is used for matching with a node in the selective directed acyclic graph. For details, see the description of step S103 in the above method embodiment, and the details are not repeated here.

An input file module 104, configured to input the pattern statement into the target definition file. For details, refer to the related description of step S101 in the above method embodiment, and no further description is given here.

The embodiment of the invention provides a device for generating a target definition file of an LLVM, which is used for executing the method for generating the target definition file of the LLVM provided by the embodiment, and the implementation mode and principle of the method are the same, and details are referred to the related description of the embodiment of the method and are not repeated.

Through the cooperation of the above components, the technical scheme provided by the application firstly obtains an external target platform information table equivalent to a target platform technical manual, and the table records first description information for describing the instruction forms supported by the target platform and second description information of the corresponding relation between each instruction form and the nodes in the selective directed acyclic graph. And summarizing all basic operation instructions supported by the target platform and representing operation actions based on the first description information, determining the data types supported by each basic operation instruction and whether the execution of conditions is supported according to the records in the first description information, correspondingly adding an upper type field and a condition field for the basic operation instruction, converting the basic operation instruction into a plurality of mode sentences according to the corresponding relation between the basic operation instruction recorded in the second description information and one or more nodes in the selected directed acyclic graph, inputting the mode sentences into a target definition file, ensuring that the relation between the instructions defined by the target platform and the intermediate languages can be accurately, reliably and completely saved in the target definition file, enabling the target definition file to be automatically generated, saving manual writing steps, enabling LLVM to traverse each mode sentence in the target definition file during compiling, determining the node of the selected directed acyclic graph, matching the intermediate language corresponding to a certain section of program developed by a developer with one or more mode sentences, and converting the intermediate language into the instructions of the target platform according to the mode sentence specification form.

In addition, in another embodiment, the basic operation instruction added with the type field and the condition field is binary coded, and the implicit state register field and the instruction stream information are added for the basic operation instruction added with the field according to the first description information, so that the function of converting the intermediate language into the assembly language is realized, and the intermediate language can be converted into the binary language which can be directly recognized by a machine. Based on the target definition file automatically generated in the embodiment, the compiling efficiency of the compiler is further improved.

Therefore, the automatically generated target definition file provided by the embodiment of the invention greatly improves the development efficiency of the compiler and the richness of the mode sentences while reducing the manual writing workload, so that the search range for optimizing the instructions can be enlarged and the code performance compiled by the compiler can be improved.

Fig. 6 shows an electronic device according to an embodiment of the invention, comprising a processor 901 and a memory 902, which may be connected via a bus or otherwise, in fig. 6 by way of example.

The processor 901 may be a central processing unit (Central Processing Unit, CPU). The processor 901 may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination thereof.

The memory 902 is used as a non-transitory computer readable storage medium for storing non-transitory software programs, non-transitory computer executable programs, and modules, such as program instructions/modules corresponding to the methods in the method embodiments described above. The processor 901 executes various functional applications of the processor and data processing, i.e., implements the methods in the above-described method embodiments, by running non-transitory software programs, instructions, and modules stored in the memory 902.

The memory 902 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, at least one application program required for a function; the storage data area may store data created by the processor 901, and the like. In addition, the memory 902 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, memory 902 optionally includes memory remotely located relative to processor 901, which may be connected to processor 901 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

One or more modules are stored in the memory 902 that, when executed by the processor 901, perform the methods of the method embodiments described above.

The specific details of the electronic device may be correspondingly understood by referring to the corresponding related descriptions and effects in the above method embodiments, which are not repeated herein.

It will be appreciated by those skilled in the art that implementing all or part of the above-described methods in the embodiments may be implemented by a computer program for instructing relevant hardware, and the implemented program may be stored in a computer readable storage medium, and the program may include the steps of the embodiments of the above-described methods when executed. The storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a Flash Memory (Flash Memory), a Hard Disk (HDD), or a Solid State Drive (SSD); the storage medium may also comprise a combination of memories of the kind described above.

Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations are within the scope of the invention as defined by the appended claims.

Claims (10)

1. A method for generating an object definition file of LLVM, the method comprising:

reading each basic operation instruction in an external target platform information table, wherein the external target platform information table comprises first description information for describing instruction forms supported by a target platform and second description information for describing corresponding relations between each instruction form and nodes in a selective directed acyclic graph, and the basic operation instruction is used for representing instruction operation actions supported by the target platform;

adding a type field and a condition field for the basic operation instruction according to the first description information, wherein the type field is used for representing operand types supported by the basic operation instruction, and the condition field is used for representing whether the basic operation instruction supports conditional execution or not;

converting the basic operation instruction added with the field into a mode statement according to the second description information, wherein the mode statement is used for matching with the nodes in the selective directed acyclic graph;

and inputting the mode statement into a target definition file.

2. The method of claim 1, wherein before converting the basic operation instruction added with the field into the pattern statement according to the second description information, the method further comprises:

Binary coding is carried out on the basic operation instruction added with the field according to the first description information;

and adding an implicit state register field and instruction stream information for the basic operation instruction after the addition field according to the first description information, wherein the implicit state register field is used for representing a state register implicitly defined and used by the basic operation instruction, and the instruction stream information is used for representing a scheduling process of the target platform hardware when the instruction runs.

3. The method of claim 1, wherein the reading of each base operation instruction in the external target platform information table comprises:

reading operation names supported by a target platform recorded in the first description information and operands corresponding to the operation names;

and splicing each operation name and the corresponding operand into each basic operation instruction.

4. The method of claim 1, wherein adding a condition field to the base operation instruction according to the first description information comprises:

determining whether the base operation instruction supports conditional execution based on the first description information;

and if the basic operation instruction supports conditional execution, adding a condition register field and/or a condition register switch field to the basic operation instruction based on condition logic supported by the basic operation instruction, wherein the condition logic is used for representing whether a corresponding condition state value is true or false when the basic operation instruction is executed.

5. The method of claim 4, wherein converting the basic operation instruction added with the field into the pattern statement according to the second description information, comprises:

determining whether the basic operation instruction is an operation for a vector according to the first description information;

if the judgment result is yes, counting all vector data types supported by the basic operation instruction through vector register digit of the target platform and a type field of the basic operation instruction;

and converting the basic operation instruction into a plurality of corresponding mode sentences under the condition of each vector data type according to the second description information.

6. The method of claim 5, wherein counting all vector data types supported by the base operation instruction through vector register bits of a target platform and a type field of the base operation instruction comprises:

calculating the ratio of the number of bits of the vector register to the number of bits of the type field to obtain the maximum number of elements of the vector supported by the basic operation instruction;

traversing all target values to the power n of 2 in the maximum element number, and counting vector data types corresponding to the target values to obtain all the vector data types, wherein n is a positive integer.

7. The method of claim 5, wherein converting the basic operation instruction added with the field into a pattern statement according to the second description information, further comprises:

and if the basic operation instruction supports conditional execution, combining the mode statement with a selection statement and/or a vector selection statement to generate a second mode statement supporting conditional execution, wherein the selection statement and the vector selection statement are statements for condition judgment in an intermediate language of the LLVM.

8. An object definition file generating apparatus of LLVM, the apparatus comprising:

the system comprises a basic instruction generation module, a target platform information table and a target platform information table, wherein the basic instruction generation module is used for reading each basic operation instruction in the external target platform information table, the external target platform information table comprises first description information for describing instruction forms supported by the target platform and second description information for describing the corresponding relation between each instruction form and a node in a selected directed acyclic graph, and the basic operation instruction is used for representing instruction operation actions supported by the target platform;

a field adding module, configured to add a type field and a condition field to the basic operation instruction according to the first description information, where the type field is used to characterize an operand type supported by the basic operation instruction, and the condition field is used to characterize whether the basic operation instruction supports conditional execution;

The mode conversion module is used for converting the basic operation instruction added with the field into a mode statement according to the second description information, and the mode statement is used for matching with the node in the selective directed acyclic graph;

and the input file module is used for inputting the mode statement into the target definition file.

9. An electronic device, comprising:

a memory and a processor in communication with each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the method of any of claims 1-7.

10. A computer readable storage medium storing computer instructions for causing the computer to perform the method of any one of claims 1-7.

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