CN113838926A - High-frequency transverse bipolar transistor circuit with high voltage and high gain modes - Google Patents
High-frequency transverse bipolar transistor circuit with high voltage and high gain modes Download PDFInfo
- Publication number
- CN113838926A CN113838926A CN202110934402.9A CN202110934402A CN113838926A CN 113838926 A CN113838926 A CN 113838926A CN 202110934402 A CN202110934402 A CN 202110934402A CN 113838926 A CN113838926 A CN 113838926A
- Authority
- CN
- China
- Prior art keywords
- region
- sio
- bipolar transistor
- base region
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 24
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 24
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 24
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 238000002955 isolation Methods 0.000 claims description 14
- 230000015556 catabolic process Effects 0.000 abstract description 12
- 238000004891 communication Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
Abstract
The invention discloses a high-frequency transverse bipolar transistor circuit with high voltage and high gain modes. The circuit comprises a polysilicon layer (2101), a SiGe base region (2103), a Si emitter region (2104), a Si collector region (2105), and SiO2A buried oxide layer (2107), a transistor (21) formed of a Si substrate (2108), and a mode control terminal (22). In a first mode (high voltage mode), Breakdown Voltage (BV) of transistors in the high frequency lateral bipolar transistor circuitCBOAnd BVCEO) Up to 7.5V and over 2.0V. In a second mode (high gain mode), the peak current gain of the transistor (21) in the high frequency lateral bipolar transistor circuit is up to 150 or more. The mode control terminal (22) switches the high frequency lateral bipolar transistor circuit by controlling a mode control signal supplied to the transistor (21) at the substrate electrode (2112)And (4) working modes.
Description
Technical Field
The invention relates to a transverse bipolar transistor circuit, in particular to a high-frequency transverse bipolar transistor circuit with high voltage and high gain modes, which is applied to microwave communication, high-speed mixed signal circuits and the like.
Background
With the continuous development of SOI technology and the advent of nanotechnology era, the lateral bipolar transistor itself has the advantages of small substrate parasitic capacitance, low leakage current, low power consumption, latch-up avoidance, etc., and will play an increasingly important role in radio frequency/microwave communications, wireless local area networks, and digital-analog mixed signal circuits.
FIG. 1 shows a schematic longitudinal cross-sectional view of a conventional high-frequency lateral bipolar transistor, which is mainly composed of a polysilicon layer (1), a SiGe base region (3), a Si emitter region (4), a Si collector region (5), and SiO2An insulating layer (7) and a Si substrate (8). Fig. 2 shows a Ge composition distribution diagram of a base region of a conventional high-frequency lateral bipolar transistor, wherein the introduction of a SiGe base region can effectively improve the high-frequency characteristics of the lateral bipolar transistor. However, when the lateral bipolar transistor is used as an active device in the microwave communication and high-speed mixed signal circuit, it is often required to have higher voltage endurance (breakdown voltage) and larger current handling capacity (current gain).
On one hand, in the prior art, the design of a multi-doped drift region in a collector region, the design of the thickness of a buried oxide layer and the design of a double buried oxide layer structure are mainly adopted to reduce the effective doping concentration of the collector region and improve the electric field distribution to improve the breakdown voltage of a device; on the other hand, in the prior art, the effective doping concentration of an emitter region is increased and the effective doping concentration of a base region is reduced by mainly adopting a positive substrate bias design and a buried oxide layer medium optimization design, so that the current gain of the device is improved. However, this causes an increase in the effective doping concentration of the collector region, which is not favorable for improving the breakdown voltage. Therefore, the prior art cannot realize that the high-frequency lateral bipolar transistor has high breakdown voltage and high current gain characteristics at the same time, and cannot realize free switching of the same high-frequency lateral bipolar transistor in high-voltage and high-gain modes, so that two high-frequency lateral bipolar transistors are required to be designed to work in the high-voltage and high-gain modes respectively.
Therefore, how to design a high-frequency transverse bipolar transistor circuit with high voltage and high gain modes has important theoretical and practical significance in effectively reducing the hardware cost of the circuit and improving the system integration level and the operation reliability.
Disclosure of Invention
The invention discloses a high-frequency transverse bipolar transistor circuit with high voltage and high gain modes.
A high frequency lateral bipolar transistor circuit having a high voltage and high gain mode, characterized by:
comprising a transistor (21) and a mode control terminal (22).
The transistor (21) comprises a Si substrate (2108), SiO2The buried oxide layer (2107), the SiGe base region (2103), the Si emitter region (2104), the Si collector region (2105) and the polysilicon layer (2101). Wherein the SiGe base region (2103), the Si emitter region (2104) and the Si collector region (2105) have the same width and thickness and are positioned on SiO2And the Si emitter region (2104) and the Si collector region (2105) are respectively positioned at the left side and the right side of the SiGe base region (2103) above the buried oxide layer (2107). The polysilicon layer (2101) is positioned right above the SiGe base region (2103), and both sides of the polysilicon layer are connected with SiO2The electrode isolation layers (2102) are in contact. A base electrode (2109) is positioned right above the polysilicon layer (2101), and an emitter electrode (2110) is positioned on the SiO2Above the buried oxide layer (2107), and with the Si emitter region (2104), SiO2The electrode isolation layer (2102) is in contact with the collector electrode (2111) which is located at SiO2A Si collector region (2105) and SiO above the buried oxide layer (2107)2The electrode isolation layers (2102) are in contact. A substrate electrode (2112) is below the SiGe base region (2103) and the Si collector region (2105) and is in contact with the Si substrate (2108). SiO 22A trench isolation layer (2106) is located on the SiO2The buried oxide layer (2107) is above and in contact with the emitter electrode (2110) and the collector electrode (2111), respectively.
The mode control terminal (22) is connected to a substrate electrode (2112).
Go toStep, the thickness of the polysilicon layer (2101) in the transistor (21) is between 5nm and 10nm, and the width is between 15nm and 35 nm; the SiO2The thickness of the electrode isolation layer (2102) is between 5nm and 10 nm; the thickness of the SiGe base region (2103), the thickness of the Si emitter region (2104) and the thickness of the Si collector region (2105) are all between 20nm and 50 nm; the widths of the SiGe base region (2103), the Si emitter region (2104) and the Si collector region (2105) are all between 30nm and 50 nm; the SiO2The thickness of the groove isolation layer (2106) is between 25nm and 50 nm; the SiO2The thickness of the buried oxide layer (2107) is between 20nm and 40 nm; the Si substrate (2108) has a thickness of between 20nm and 50 nm.
Further, it is characterized in that:
in the transistor (21), the Ge component of the base region is in a trapezoidal distribution structure from the emitter junction side to the collector junction side, and the expression of the Ge content is as follows:
wherein, WBIs the base width, y represents the Ge component content in the base region, x represents the distance from one side of the emitter junction in the base region, and x1Representing the position of the trapezoidal turning point in the base region, y1Representing the trapezoidal turning point x in the base region1The corresponding Ge component content of the position, the base region Ge component content is 0.15-0.3, x1The position of (a) is between 5nm and 30 nm.
Further, the mode control terminal (22) controls a voltage signal on the substrate electrode (2112). When the mode control signal is between-0.5V and-3.5V, the high-frequency transverse bipolar transistor circuit is in a high-voltage mode; when the mode control signal is between +0.5V and +5V, the high-frequency transverse bipolar transistor circuit is in a high-gain mode; however, when the mode signal is not within the above signal range, the high voltage mode or the high gain mode cannot be achieved, and thus the mode control signal is critical for a high frequency lateral bipolar transistor circuit having the high voltage and the high gain mode.
Compared with the conventional high-frequency transverse bipolar transistor, the high-frequency transverse bipolar transistor circuit with the high-voltage and high-gain modes has the advantages that the breakdown voltage and the current gain are improved, and the application of the device in microwave communication and high-speed mixed signal circuits is expanded.
Drawings
Further objects and advantages of the invention will be understood by reference to the following description taken in conjunction with the accompanying drawings. In these drawings:
FIG. 1 illustrates a schematic longitudinal cross-sectional view of a conventional high frequency lateral bipolar transistor;
FIG. 2 illustrates a distribution diagram of Ge composition of a base region of a conventional high frequency lateral bipolar transistor;
FIG. 3 illustrates a schematic longitudinal cross-section of an embodiment of the invention;
FIG. 4 illustrates a base region Ge composition distribution plot in accordance with an embodiment of the present invention;
FIG. 5 illustrates a frequency characteristic of an embodiment of the present invention in a first mode (high voltage mode);
FIG. 6 illustrates the breakdown voltage BV for the device in the first mode (high voltage mode) according to an embodiment of the present inventionCBOImprovement of (1);
FIG. 7 illustrates the breakdown voltage BV for the device in the first mode (high voltage mode) according to an embodiment of the present inventionCEOImprovement of (1);
FIG. 8 illustrates a frequency characteristic of an embodiment of the present invention in a second mode (high gain);
fig. 9 illustrates the improvement in device current gain in the second mode (high gain) of an embodiment of the present invention.
Detailed Description
The embodiment of the invention specifically expresses the content of the invention by taking an NPN type high-frequency transverse bipolar transistor as an example. The field to which the invention relates is not limited thereto.
The implementation example is as follows:
the embodiment of the invention discloses a high-frequency transverse bipolar transistor circuit with high voltage and high gain modes, which is provided with a transistor and a mode control end at the same time.
Fig. 3 illustrates a longitudinal cross-sectional schematic view of an embodiment of the present invention. Including a transistor (21) and a mode control terminal (22). WhereinThe polysilicon layer (2101) in the transistor (21) has a thickness of 5nm, a width of 26nm and a doping concentration of 5 × 1019cm-3;SiO2An electrode isolation layer (2102) having a thickness of 5 nm; the SiGe base region (2103) has a thickness of 20nm, a width of 30nm and a doping concentration of 1 × 1019cm-3(ii) a The thickness of the Si emission region (2104) and the thickness of the Si collector region (2105) are both 20nm, the width of the Si emission region (2104) and the width of the Si collector region (2105) are both 30nm, the doping concentration of the Si emission region (2104) and the doping concentration of the Si collector region (2105) are equal, and the thicknesses are both 2 multiplied by 1020cm-3;SiO2A trench isolation layer (2106) having a thickness of 25 nm; SiO 22A buried oxide layer (2107) having a thickness of 20 nm; the Si substrate (2108) has a thickness of 20nm and a doping concentration of 1 × 1017cm-3(ii) a The mode control terminal (22) is connected to the substrate electrode (2112), and in this embodiment, when the mode control signal is-2.8V, the high-frequency lateral bipolar transistor circuit is in the first mode (high-voltage mode), and when the mode control signal is +2.3V, the high-frequency lateral bipolar transistor circuit is in the second mode (high-gain mode).
Fig. 4 illustrates a base region Ge composition profile according to an embodiment of the present invention. When the Ge component of the base region is distributed in a ladder shape, the minority carrier accelerating electric field is introduced due to the gradual change of the Ge component, so that the transition time of the base region is reduced, and the current gain and the cut-off frequency of the base region have higher values. In the SiGe base region (2103), Ge components in the base region are in a trapezoidal distribution structure from the emitter junction side to the collector junction side, and the expression of Ge content is as follows:
wherein, WBIs the base width, y represents the Ge component content in the base region, x represents the distance from one side of the emitter junction in the base region, and x1Representing the position of the trapezoidal turning point in the base region, y1Representing the trapezoidal turning point x in the base region1The corresponding Ge composition content at the location. In the embodiment of the invention, the content of the Ge component in the base region is 0.2, x1=15nm,y1=0.27。
FIG. 5 illustrates an embodiment of the present invention in a first mode (high pressure mode)) Frequency characteristic curve of (1). It can be seen that the peak characteristic frequency (f) of the embodiment of the present inventionT) Up to 228.50GHz and collector current ICWhen the frequency is changed within the range of 0.2 mA-4 mA, the characteristic frequency of the embodiment of the invention is up to more than 200 GHz.
FIG. 6 illustrates the breakdown voltage BV for the device in the first mode (high voltage mode) according to an embodiment of the present inventionCBOThe improvement of (1). It can be seen that the Breakdown Voltage (BV) of the present embodimentCBO) 7.90V, an improvement of 2.7V over the conventional high frequency lateral bipolar transistor, an improvement of 52.0%.
FIG. 7 illustrates the breakdown voltage BV for the device in the first mode (high voltage mode) according to an embodiment of the present inventionCEOThe improvement of (1). It can be seen that the Breakdown Voltage (BV) of the present embodimentCEO) 2.15V, which is improved by 0.5V and 30.3% compared with the conventional high-frequency transverse bipolar transistor.
Fig. 8 illustrates a frequency characteristic curve in the second mode (high gain mode) of the embodiment of the present invention. It can be seen that the peak characteristic frequency (f) of the embodiment of the present inventionT) Up to 250.73GHz and collector current ICWhen the frequency is changed within the range of 0.1 mA-4 mA, the characteristic frequencies of the embodiment of the invention are all higher than 200 GHz.
Fig. 9 illustrates the improvement in device current gain in the second mode (high gain mode) of embodiments of the present invention. It can be seen that the peak current gain (β) of the embodiment of the present invention is 156.50, which is an improvement of 61.02 and up to 63.91% over the conventional high frequency lateral bipolar transistor.
And a collector current ICAt 1X 10-6When the range of mA-0.05 mA is changed, the current gain range of the conventional high-frequency transverse bipolar transistor is only 45.9-95.48, and the current gain range of the embodiment is 102-156.50.
The above results all show the superiority of the embodiments of the present invention, which are of great theoretical and practical significance for designing and manufacturing a high frequency lateral bipolar transistor circuit having a high voltage and high gain mode.
Claims (4)
1. A high frequency lateral bipolar transistor circuit having a high voltage and high gain mode, characterized by:
comprises a transistor (21) and a mode control terminal (22);
the transistor (21) comprises a Si substrate (2108), SiO2The buried oxide layer (2107), the SiGe base region (2103), the Si emitter region (2104), the Si collector region (2105) and the polysilicon layer (2101); wherein the SiGe base region (2103), the Si emitter region (2104) and the Si collector region (2105) have the same width and thickness and are positioned on SiO2The Si emitter region (2104) and the Si collector region (2105) are respectively positioned at the left side and the right side of the SiGe base region (2103) above the buried oxide layer (2107); the polysilicon layer (2101) is positioned right above the SiGe base region (2103), and both sides of the polysilicon layer are connected with SiO2The electrode isolation layers (2102) are in contact; a base electrode (2109) is positioned right above the polysilicon layer (2101), and an emitter electrode (2110) is positioned on the SiO2Above the buried oxide layer (2107), and with the Si emitter region (2104), SiO2The electrode isolation layer (2102) is in contact with the collector electrode (2111) which is located at SiO2A Si collector region (2105) and SiO above the buried oxide layer (2107)2The electrode isolation layers (2102) are in contact; the substrate electrode (2112) is in contact with the Si substrate (2108); SiO 22A trench isolation layer (2106) is located on the SiO2An emitter electrode (2110) and a collector electrode (2111) are respectively contacted above the buried oxide layer (2107);
the mode control terminal (22) is connected to a substrate electrode (2112).
2. A high frequency lateral bipolar transistor circuit having a high voltage and high gain mode according to claim 1, wherein:
the thickness of the polysilicon layer (2101) in the transistor (21) is between 5nm and 10nm, and the width is between 15nm and 35 nm; the SiO2The thickness of the electrode isolation layer (2102) is between 5nm and 10 nm; the thickness of the SiGe base region (2103), the thickness of the Si emitter region (2104) and the thickness of the Si collector region (2105) are all between 20nm and 50 nm; the widths of the SiGe base region (2103), the Si emitter region (2104) and the Si collector region (2105) are all between 30nm and 50 nm; the SiO2The thickness of the groove isolation layer (2106) is between 25nm and 50 nm;the SiO2The thickness of the buried oxide layer (2107) is between 20nm and 40 nm; the Si substrate (2108) has a thickness of between 20nm and 50 nm.
3. A high frequency lateral bipolar transistor circuit having a high voltage and high gain mode according to claim 1, wherein:
in the transistor (21), the Ge component of the base region is in a trapezoidal distribution structure from the emitter junction side to the collector junction side, and the expression of the Ge content is as follows:
wherein, WBIs the base width, y represents the Ge component content in the base region, x represents the distance from one side of the emitter junction in the base region, and x1Representing the position of the trapezoidal turning point in the base region, y1Representing the trapezoidal turning point x in the base region1The corresponding Ge component content of the position, the base region Ge component content is 0.15-0.3, x1The position of (a) is between 5nm and 30 nm.
4. A high frequency lateral bipolar transistor circuit having a high voltage and high gain mode according to claim 1, wherein:
the mode control terminal (22) controls a voltage signal on the substrate electrode (2112); when the mode control signal is between-0.5V and-3.5V, the high-frequency transverse bipolar transistor circuit is in a high-voltage mode; when the mode control signal is between +0.5V and +5V, the high-frequency transverse bipolar transistor circuit is in a high-gain mode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202110934402.9A CN113838926B (en) | 2021-08-16 | 2021-08-16 | High-frequency lateral bipolar transistor circuit with high voltage and high gain modes |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202110934402.9A CN113838926B (en) | 2021-08-16 | 2021-08-16 | High-frequency lateral bipolar transistor circuit with high voltage and high gain modes |
Publications (2)
Publication Number | Publication Date |
---|---|
CN113838926A true CN113838926A (en) | 2021-12-24 |
CN113838926B CN113838926B (en) | 2023-09-12 |
Family
ID=78960580
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202110934402.9A Active CN113838926B (en) | 2021-08-16 | 2021-08-16 | High-frequency lateral bipolar transistor circuit with high voltage and high gain modes |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN113838926B (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103137666A (en) * | 2011-11-23 | 2013-06-05 | 上海华虹Nec电子有限公司 | Vertical PNP bipolar junction transistor and production method thereof |
CN104091825A (en) * | 2014-07-13 | 2014-10-08 | 北京工业大学 | Super junction collector region SiGe heterojunction bipolar transistor |
CN107342319A (en) * | 2017-06-21 | 2017-11-10 | 燕山大学 | A kind of composite strain Si/SiGe heterojunction bipolar transistors and preparation method thereof |
CN110556420A (en) * | 2019-08-23 | 2019-12-10 | 北京工业大学 | Transverse SiGe heterojunction bipolar transistor with adjustable doping concentration |
-
2021
- 2021-08-16 CN CN202110934402.9A patent/CN113838926B/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103137666A (en) * | 2011-11-23 | 2013-06-05 | 上海华虹Nec电子有限公司 | Vertical PNP bipolar junction transistor and production method thereof |
CN104091825A (en) * | 2014-07-13 | 2014-10-08 | 北京工业大学 | Super junction collector region SiGe heterojunction bipolar transistor |
CN107342319A (en) * | 2017-06-21 | 2017-11-10 | 燕山大学 | A kind of composite strain Si/SiGe heterojunction bipolar transistors and preparation method thereof |
CN110556420A (en) * | 2019-08-23 | 2019-12-10 | 北京工业大学 | Transverse SiGe heterojunction bipolar transistor with adjustable doping concentration |
Also Published As
Publication number | Publication date |
---|---|
CN113838926B (en) | 2023-09-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9040956B2 (en) | Unipolar heterojunction depletion-layer transistor | |
US20220246550A1 (en) | Transient Stabilized SOI FETs | |
US20220406936A1 (en) | Semiconductor device | |
CN102201442A (en) | Heterojunction field effect transistor based on channel array structure | |
US6734509B2 (en) | Semiconductor integrated circuit | |
Donaghy et al. | Design of 50-nm vertical MOSFET incorporating a dielectric pocket | |
US7667499B2 (en) | MuGFET circuit for increasing output resistance | |
CN113838926B (en) | High-frequency lateral bipolar transistor circuit with high voltage and high gain modes | |
CN104599974A (en) | Semiconductor structure and forming method thereof | |
CN110556420B (en) | Transverse SiGe heterojunction bipolar transistor with adjustable doping concentration | |
US7397109B2 (en) | Method for integration of three bipolar transistors in a semiconductor body, multilayer component, and semiconductor arrangement | |
CN116598361A (en) | LDMOS device with super-junction split gate | |
CN112420846B (en) | Transverse super-junction thin-layer SOI-LDMOS device with surface and body double channels | |
CN102412302A (en) | Tunneling field-effect transistor for inhibiting bipolar effect and preparation method thereof | |
CN112466955B (en) | Thin-layer SOI-LDMOS device with in-vivo conductive channel | |
Karbalaei et al. | Influence of source stack and heterogeneous gate dielectric on band to band tunneling rate of tunnel FET | |
CN108010962B (en) | SOI SiGe heterojunction bipolar transistor with high characteristic frequency-breakdown voltage figure of merit | |
CN104282754B (en) | High integration L-shaped grid-control Schottky barrier tunneling transistor | |
CN110797408A (en) | Dynamic threshold tunneling field effect double-gate device | |
US8492796B2 (en) | MuGFET switch | |
CN113097310B (en) | Fin-type EAFin-LDMOS device with electron accumulation effect | |
CN104112774A (en) | Transverse double diffusion metal oxide semiconductor field effect transistor | |
KR102353462B1 (en) | Ternary inverter device | |
WO2022052045A1 (en) | Negative-capacitance junction-less nanowire field effect transistor and manufacturing method therefor | |
CN113838927B (en) | Charge plasma SiGe heterojunction bipolar transistor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |