CN113838925A - Semiconductor device and preparation method thereof - Google Patents
Semiconductor device and preparation method thereof Download PDFInfo
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- CN113838925A CN113838925A CN202111112800.9A CN202111112800A CN113838925A CN 113838925 A CN113838925 A CN 113838925A CN 202111112800 A CN202111112800 A CN 202111112800A CN 113838925 A CN113838925 A CN 113838925A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 238000002955 isolation Methods 0.000 claims abstract description 70
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 150000002500 ions Chemical class 0.000 claims abstract description 35
- 238000005468 ion implantation Methods 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 239000002019 doping agent Substances 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 230000005684 electric field Effects 0.000 abstract description 9
- 108091006146 Channels Proteins 0.000 description 11
- 239000000243 solution Substances 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000002028 premature Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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Abstract
The invention discloses a semiconductor device and a preparation method thereof, and the semiconductor device comprises a substrate and a grid electrode positioned on the substrate, wherein the substrate comprises an active region configured along a first direction and isolation regions positioned at two sides of the active region in a second direction, the grid electrode extends to the isolation regions at two sides of the active region along the second direction, the grid electrode is provided with first type doping ions, and a second type doping region is arranged at a position corresponding to the junction of the active region and the isolation regions. The doping type of the second type doping area is opposite to the type of the first type doping ions in the grid electrode, so that an electric field at the edge of the active area can be reduced, namely a channel edge area corresponding to the edge of the active area is less prone to being inverted or the inversion time is later, the channel edge area can be prevented from being started in advance, namely the voltage threshold of the channel edge area is improved, and the double-hump phenomenon of an Id-Vg curve is improved.
Description
Technical Field
The present invention relates generally to electronic devices and, more particularly, to a semiconductor device and a method of manufacturing the same.
Background
In some existing semiconductor devices, the following transistors are often required: a Low Voltage Metal Oxide Semiconductor (LVMOS) transistor and a High Voltage MOS transistor (HVMOS). Shallow Trench Isolation (STI) is an important component in integrated circuits, and is formed in a substrate to isolate electrical connections between mos (metal Oxide semiconductor) transistors.
In the manufacturing process of the integrated circuit, the double hump phenomenon of a drain current-grid voltage curve is easily caused.
Disclosure of Invention
The invention aims to provide a semiconductor device and a preparation method thereof, aiming at improving the double hump phenomenon of an Id-Vg curve of an MOS (metal oxide semiconductor) so as to remove the limitation of the MOS on an STI (shallow trench isolation) angle without adding an additional mask plate and process steps.
In one aspect, the present invention provides a semiconductor device comprising:
the semiconductor device comprises a substrate, a first electrode, a second electrode and a third electrode, wherein the substrate comprises an active region arranged along a first direction and isolation regions positioned on two sides of the active region in a second direction perpendicular to the first direction;
the grid electrode is positioned on the substrate and extends to the isolation regions on two sides of the active region along the second direction, the grid electrode is provided with first type doping ions, the grid electrode is provided with a second type doping region at the junction corresponding to the active region and the isolation regions, and the doping type of the second type doping region is opposite to that of the first type doping ions in the grid electrode.
Further preferably, the gate includes polysilicon, the first type doped ions are N type doped ions, and the second type doped region is a P type doped region.
Further preferably, the doping type of the active region is P-type, and a source and a drain of N-type doping are respectively provided at two ends of the active region of the substrate in the first direction.
Further preferably, the gate includes polysilicon, the first type doped ions are P type doped ions, and the second type doped region is an N type doped region.
Further preferably, the method further comprises the following steps:
and the side wall is connected with two sides of the grid in the first direction, the side wall is provided with the second type doping area at the junction corresponding to the active area and the isolation area, and the second type doping area extends in the first direction.
In another aspect, the present invention provides a semiconductor device comprising:
providing a substrate, wherein the substrate comprises an active region configured along a first direction and isolation regions positioned on two sides of the active region in a second direction perpendicular to the first direction;
forming a grid above the substrate, wherein the grid extends to the isolation regions on two sides of the active region along the second direction, the grid is provided with first type doping ions, the grid is provided with a second type doping region at the junction corresponding to the active region and the isolation region, and the doping type of the second type doping region is opposite to that of the first type doping ions in the grid.
Further preferably, the step of forming a gate over the substrate includes:
forming a gate extending along the second direction, the gate extending to the isolation region on both sides of the active region;
performing the first type of ion implantation into the gate;
and performing ion implantation of the second type at the junction of the active region and the isolation region corresponding to the grid to form the second type doping region.
Further preferably, the step of performing the first type of ion implantation into the gate electrode includes:
performing N-type ion implantation on the grid;
the step of performing the ion implantation of the second type at the junction of the gate corresponding to the active region and the isolation region includes: and performing P-type ion implantation at the junction of the gate corresponding to the active region and the isolation region.
Further preferably, the step of performing the first type of ion implantation into the gate electrode includes:
performing P-type ion implantation on the grid;
the step of performing the ion implantation of the second type at the junction of the gate corresponding to the active region and the isolation region includes: and performing N-type ion implantation at the junction of the gate corresponding to the active region and the isolation region.
Further preferably, the method further comprises the following steps:
forming side walls connected with the two sides of the grid in the first direction;
and performing ion implantation of the second type on the side wall at the junction corresponding to the active region and the isolation region, so that the second type doped region extends to the side wall in the first direction.
The invention has the beneficial effects that: a semiconductor device and a method for manufacturing the same are provided, which includes a substrate including an active region arranged along a first direction and isolation regions at both sides of the active region in a second direction, and a gate electrode on the substrate. The grid extends to the isolation regions at two sides of the active region along a second direction, the grid is provided with first type doping ions and a second type doping region corresponding to the junction of the active region and the isolation region, and the doping type of the second type doping region is opposite to that of the first type doping ions in the grid. According to the invention, the second type doping area of the opposite type is formed in the grid electrode with the first type doping ions, and the formed area is positioned at the boundary of the grid electrode and the active area (namely the edge of the active area), so that the electric field at the edge of the active area can be reduced (under the condition that the same voltage is applied to the grid electrode, the electric field generated at the edge of the active area is smaller than that generated at other positions), namely, the channel edge area corresponding to the edge of the active area is less prone to or later in the opposite type, and therefore, the channel edge area can be prevented from being opened in advance, namely, the voltage threshold value of the channel edge area is improved, and the double hump phenomenon of an Id-Vg curve is improved.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
Fig. 1 is a schematic structural view of a semiconductor device provided in a first embodiment of the present invention;
fig. 2 is a schematic cross-sectional view of the semiconductor device of fig. 1 at a-a1 according to a first embodiment of the present invention;
fig. 3 is a schematic structural view of a semiconductor device provided in a second embodiment of the present invention;
fig. 4 is a schematic flow chart of a method for manufacturing a semiconductor device according to a third embodiment of the present invention;
fig. 5a to 5d are schematic structural diagrams in the process of manufacturing a semiconductor device according to a third embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that, although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention.
It will be understood that when an element is referred to as being "on," "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. Other words used to describe the relationship between components should be interpreted in a similar manner.
As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. The layer may extend over the entire underlying or overlying structure or may have an extent less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers above, and/or below it. The layer may comprise a plurality of layers. For example, the interconnect layers may include one or more conductive layers and contact layers (in which contacts, interconnect lines, and one or more dielectric layers are formed).
As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate such that the array structure extends in a vertical direction relative to the substrate; "vertical" refers to a direction perpendicular to the substrate.
It should be noted that the drawings provided in the embodiments of the present invention are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in the actual implementation, the type, quantity and proportion of the components in the actual implementation can be changed freely, and the layout of the components may be more complicated.
In the fabrication of these semiconductor devices, to avoid the double hump phenomenon of the drain current-gate voltage (Id-Vg) curve, HVMOS requires the STI to be at an angle <76 degrees with respect to the substrate upper surface, while LVMOS or transistors at lower voltages than LVMOS require the STI angle to be as close to 90 degrees as possible. One important reason for the double hump phenomenon of the drain current-gate voltage curve is that, during the manufacturing process of the integrated circuit, due to the high temperature effect during the subsequent thermal treatment processes such as thermal oxidation, annealing and the like, boron doped in the well region (substrate) can diffuse into the Shallow Trench Isolation (STI) structure, thereby causing boron loss (boronloss) in the well region. When the boron loss is serious, the edge of the device is turned on early, so that the Id-Vgcurvedoublehump phenomenon appears on the Id-Vg curve. On the other hand, the corner between the STI and the substrate active region is an inclined plane, which causes the thickness of the gate oxide layer at the edge of the active region to be thinner, and further causes the device at the edge of the active region to be opened early, thereby causing the double hump phenomenon of the Id-Vg curve.
One solution in the prior art is to improve the double hump phenomenon by adopting a double STI process to simultaneously meet the angle requirements of the HVMOS and the LVMOS, but the double STI process needs to adopt multiple etching processes, which results in high cost.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a semiconductor device according to a first embodiment of the present invention. The semiconductor device 10 includes a substrate 11 and a gate electrode 12 on the substrate 11. The substrate 11 includes an active region 111 disposed along a first direction (X) and Isolation regions 112 located at two sides of the active region 111 in a second direction (Y) perpendicular to the first direction (X), a Shallow Trench Isolation (STI) structure 1121 is formed in the Isolation regions 112 of the substrate 11, and the active region 111 has a source 1111 and a drain 1112 at two ends of the first direction (X), respectively. The semiconductor device 10 further includes a gate insulating layer (not shown) between the substrate 11 and the gate electrode 12, the gate insulating layer being located above the active region 111.
The gate 12 extends to the isolation region 112 on both sides of the active region 111 along the second direction (Y), the gate 12 has a first type dopant ion, and the gate 12 has a second type dopant region 121 at the intersection corresponding to the active region 111 and the isolation region 112, the doping type of the second type dopant region 121 is opposite to the type of the first type dopant ion in the gate 12. The semiconductor device 10 may be an HVMOS or an LVMOS.
Specifically, in an embodiment, the doping type of the active region 111 is P-type, and the active region 111 has a source 1111 and a drain 1112 doped N-type at two ends of the first direction (X), respectively. The gate 12 comprises polysilicon, the first type doped ions are N type doped ions, and the second type doped region 121 is a P type doped region. When a voltage (positive voltage) is applied to the gate 12, an electric field is formed between the gate 12 and the substrate 11, the electric field causes electrons in the active region 111 in the substrate 11 to gather on the upper surface of the substrate 11, and when the electrons accumulate to a certain amount, the substrate 11 inverts to form an N-type conduction channel on the upper surface of the active region 111, so that conduction is conducted between the source 1111 and the drain 1112. The voltage for turning on the source 1111 and the drain 1112 is a threshold voltage or an on voltage.
In another embodiment, the doping type of the active region 111 is N-type, and the active region 111 has a source 1111 and a drain 1112 doped P-type at two ends of the first direction (X), respectively. The gate 12 comprises polysilicon, the first type doped ions are P type doped ions, and the second type doped region 121 is an N type doped region. When a voltage (negative voltage) is applied to the gate 12, an electric field is formed between the gate 12 and the substrate 11, the electric field causes holes in the active region 111 in the substrate 11 to gather on the upper surface of the substrate 11, and when the holes accumulate to a certain amount, the substrate 11 inverts to form a P-type conductive channel on the upper surface of the active region 111, so that conduction is performed between the source 1111 and the drain 1112. Here, the voltage for turning on the source 1111 and the drain 1112 is a threshold voltage.
Referring to fig. 2, fig. 2 is a schematic cross-sectional view of the semiconductor device of fig. 1 at a-a1, wherein the Z direction is perpendicular to both the X and Y directions according to a first embodiment of the present invention. The gate insulating layer 13 is located between the substrate 11 and the gate 12 and located in the active region 111, and the isolation region 112 is formed with a shallow trench isolation structure 1121. In example application, the shallow trench isolation structure formed by the etching process has a large top dimension and a small bottom dimension, that is, the shallow trench isolation structure is represented as an inclined plane, and an included angle between the shallow trench isolation structure and the upper surface of the substrate 11 is θ. The larger θ, the more the surface B of the shallow trench isolation structure is bent at the included angle, which results in a thinner gate insulating layer 13, and thus results in premature turn-on of the device at the boundary between the active region 111 and the isolation region 112 (i.e. at the edge of the active region 111). The edge of the active region 111 is subjected to a subsequent thermal diffusion process resulting in a loss of doping of the substrate (boron loss) which also results in premature turn-on of the edge devices (channel edge regions) of the active region 111. The channel edge region is turned on too early (indicating that the voltage threshold value is low), which causes a double hump phenomenon on the Id-Vg curve, indicating that leakage current increases in the voltage threshold region and also causes errors when the model is built.
It is understood that fig. 1 refers to the boundary between the active region 111 and the isolation region 112, and fig. 2 refers to the boundary C-C1 between the active region 111 and the upper surface of the isolation region 112. The gate 12 has a second type doped region 121 at the boundary between the active region 111 and the isolation region 112, and a portion of the second type doped region 121 is located above the active region 111, and another portion is located above the isolation region 112, i.e. a portion of the second type doped region 121 is in contact with the gate insulating layer 13, and another portion is in contact with the upper surface of the shallow trench isolation structure of the substrate 11.
Since the doping type of the second type doping region 121 is a P type doping region, the first type doping ions in the gate 12 are N type doping ions, and when the doping type of the second type doping region 121 is an N type doping region, the first type doping ions in the gate 12 are P type doping ions, that is, the doping type of the second type doping region 121 is opposite to the type of the first type doping ions in the gate 12. Therefore, in the present embodiment, the electric field at the edge of the active region 111 can be reduced (when the same voltage is applied to the gate, the electric field generated at the edge of the active region is smaller than that at other positions), that is, the channel edge region corresponding to the edge of the active region 111 is less likely to invert or invert later, so that the channel edge region can be inhibited from being turned on earlier, that is, the voltage threshold of the channel edge region can be increased, and the double hump phenomenon of the Id-Vg curve can be improved. It is understood that for a P-type channel, since the voltage threshold is a negative voltage, increasing the voltage threshold corresponds to decreasing the value of the threshold voltage.
In the embodiment, the other part of the second-type doped region 121 is located above the isolation region 112 to better improve the double-hump phenomenon, i.e. to ensure the effect of the second-type doped region 121 on improving the double-hump phenomenon.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a semiconductor device according to a second embodiment of the present invention. For ease of understanding, the same structures of the present embodiment as those of the first embodiment are given the same reference numerals. The semiconductor device 20 is different from the semiconductor device 10 provided in the first embodiment in that the semiconductor device 20 further includes a sidewall 14 connected to two sides of the gate 12 in the first direction (X), and the sidewall 14 has the second-type doped region 121 at a boundary corresponding to the active region 111 and the isolation region 112, that is, the second-type doped region 121 extends to the sidewall 14 at two sides of the gate 12 in the first direction (X).
In this embodiment, the second type doping region 121 extends to the sidewall 14 in the Y direction, so that the coverage area of the second type doping region 121 is larger, and the edge region of the active region 111 can be completely covered, thereby ensuring that the second type doping region 121 can improve the threshold voltage (turn-on voltage) at the edge of the active region 111.
Referring to fig. 4, fig. 4 is a schematic flow chart illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention. Referring to fig. 5a to 5d, fig. 5a to 5d are schematic structural diagrams in a manufacturing process of a semiconductor device according to a third embodiment of the present invention. Taking the above-described semiconductor device 20 as an example, the preparation of the semiconductor device 20 includes the following steps S1-S5.
Please refer to step S1 in fig. 1 and fig. 5 a.
Step S1: a substrate 11 is provided, said substrate 11 comprising an active region 111 arranged along a first direction (X), and isolation regions 112 located at both sides of said active region 111 in a second direction (Y) perpendicular to said first direction (X).
The substrate 11 may be a semiconductor substrate, and may be, for example, a Silicon (Si), Germanium (Ge), SiGe substrate, Silicon On Insulator (SOI), Germanium On Insulator (GOI), or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, and may also be a stacked structure, such as Si/SiGe or the like.
Specifically, the substrate 11 is etched to form a trench, and then the trench is filled with an insulating material to form a shallow trench isolation structure 1121 located in the isolation region 112 in the substrate 11, the shallow trench isolation structure 1121 may be arranged at an interval to define an active region 111 extending along the first direction (X), and a mask plate may be used to perform the second type ion implantation in the active region 111. In the present embodiment, the isolation region 112 is located at two sides of the active region 111, and in some embodiments, the isolation region 112 may further surround the periphery of the active region 111 to isolate the plurality of active regions 111.
In this embodiment, after forming the active region 111, a first type ion implantation is performed on two ends of the active region 111 in the first direction (X) to form a doped source 1111 and a doped drain 1112.
Please refer to steps S2-S3 in fig. 1 and fig. 5 b.
Step S2: forming a gate 12 extending along the second direction (Y), the gate 12 extending to the isolation region 112 on both sides of the active region 111.
In this embodiment, a gate oxide layer may be formed on the upper surface of the substrate 11 of the active region 111, and then polysilicon may be formed on the gate oxide layer as the gate 12, and the gate 12 extends to the isolation regions 112 on both sides of the active region 111 along the second direction (Y).
Step S3: the first type of ion implantation is performed into the gate electrode 12.
In this embodiment, a blanket ion implantation process may be used to perform a blanket first type ion implantation on the polysilicon layer.
Please refer to step S4 and fig. 5c in fig. 1.
Step S4: forming side walls 14 connected to both sides of the gate electrode 12 in the first direction (X).
The spacers 14 may be formed on both sides of the gate 12 in the first direction (X) by deposition and etching processes to protect the gate 12, and also to reduce Hot Carrier Injection (HCI) effect.
Please refer to step S5 and fig. 5d in fig. 1.
Step S5: and performing ion implantation of the second type at the boundary between the gate 12 and the sidewall 14 corresponding to the active region 111 and the isolation region 112 to form the second type doped region 121.
In this embodiment, a second type ion implantation is performed on the gate 12 and the sidewall 14 in the boundary region between the active region 111 and the isolation region 112 to form the second type doped region 121, and the second type doped region 121 extends to the sidewall 14 on both sides in the first direction (X). In some embodiments, if the sidewall spacers 14 are not formed, only the gate 12 is subjected to the second ion implantation in the boundary region between the active region 111 and the isolation region 112, so as to form a second-type doped region 121 (see fig. 1) extending in the first direction (X). Since the doping type of the second-type doped region 121 is opposite to that of the first-type ions, the channel edge region can be prevented from being turned on in advance, so as to improve the double hump phenomenon of the Id-Vg curve.
Specifically, in one embodiment, P-type ion implantation may be performed on the active region 111, an N-doped source 1111 and a drain 1112 are formed in two ends of the active region 111, a full N-type ion implantation is performed on the gate 12, and a second P-type ion implantation is performed at a boundary between the gate 12 and the isolation region 112 corresponding to the active region 111.
In another embodiment, N-type ion implantation may be performed on the active region 111, a P-doped source 1111 and a drain 1112 are formed at two ends of the active region 111, a full P-type ion implantation is performed on the gate 12, and N-type ion implantation is performed at the boundary between the gate 12 and the corresponding active region 111 and the isolation region 112.
In the method for manufacturing a semiconductor device provided by the embodiment of the invention, in the process of forming the MOS, the first type ion implantation is performed on the gate 12 comprehensively, and then the second type ion implantation is performed on the boundary region between the active region 111 and the isolation region 112 corresponding to the gate 12 to form the second type doping region 121.
The above description of the embodiments is only for helping understanding the technical solution of the present invention and its core idea; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A semiconductor device, comprising:
the semiconductor device comprises a substrate, a first electrode, a second electrode and a third electrode, wherein the substrate comprises an active region arranged along a first direction and isolation regions positioned on two sides of the active region in a second direction perpendicular to the first direction;
the grid electrode is positioned on the substrate and extends to the isolation regions on two sides of the active region along the second direction, the grid electrode is provided with first type doping ions, the grid electrode is provided with a second type doping region at the junction corresponding to the active region and the isolation regions, and the doping type of the second type doping region is opposite to that of the first type doping ions in the grid electrode.
2. The semiconductor device of claim 1, wherein the gate comprises polysilicon and the first type dopant ions are N type dopant ions and the second type dopant region is a P type dopant region.
3. The semiconductor device according to claim 2, wherein the doping type of the active region is P-type, and the substrate has a source and a drain doped N-type at two ends of the active region in the first direction.
4. The semiconductor device of claim 1, wherein the gate comprises polysilicon and the first type dopant ions are P type dopant ions and the second type dopant region is an N type dopant region.
5. The semiconductor device according to claim 1, further comprising:
and the side wall is connected with two sides of the grid in the first direction, the side wall is provided with the second type doping area at the junction corresponding to the active area and the isolation area, and the second type doping area extends in the first direction.
6. A method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises an active region configured along a first direction and isolation regions positioned on two sides of the active region in a second direction perpendicular to the first direction;
forming a grid above the substrate, wherein the grid extends to the isolation regions on two sides of the active region along the second direction, the grid is provided with first type doping ions, the grid is provided with a second type doping region at the junction corresponding to the active region and the isolation region, and the doping type of the second type doping region is opposite to that of the first type doping ions in the grid.
7. The method of manufacturing a semiconductor device according to claim 6, wherein the step of forming a gate over the substrate includes:
forming a gate extending along the second direction, the gate extending to the isolation region on both sides of the active region;
performing the first type of ion implantation into the gate;
and performing ion implantation of the second type at the junction of the active region and the isolation region corresponding to the grid to form the second type doping region.
8. The method according to claim 7, wherein the step of implanting the first type of ions into the gate electrode comprises:
performing N-type ion implantation on the grid;
the step of performing the ion implantation of the second type at the junction of the gate corresponding to the active region and the isolation region includes: and performing P-type ion implantation at the junction of the gate corresponding to the active region and the isolation region.
9. The method according to claim 7, wherein the step of implanting the first type of ions into the gate electrode comprises:
performing P-type ion implantation on the grid;
the step of performing the ion implantation of the second type at the junction of the gate corresponding to the active region and the isolation region includes: and performing N-type ion implantation at the junction of the gate corresponding to the active region and the isolation region.
10. The method for manufacturing a semiconductor device according to claim 6, further comprising:
forming side walls connected with the two sides of the grid in the first direction;
and performing ion implantation of the second type on the side wall at the junction corresponding to the active region and the isolation region, so that the second type doped region extends to the side wall in the first direction.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1093096A (en) * | 1996-09-19 | 1998-04-10 | Toshiba Corp | Semiconductor device and its manufacture |
| CN101236986A (en) * | 2007-02-02 | 2008-08-06 | 三星电子株式会社 | High voltage transistors and its production method |
| US20100237439A1 (en) * | 2009-03-18 | 2010-09-23 | Ming-Cheng Lee | High-voltage metal-dielectric-semiconductor device and method of the same |
| US20130092987A1 (en) * | 2011-10-13 | 2013-04-18 | Stmicroelectronics (Rousset) Sas | Mos transistor with no hump effect |
| US10141398B1 (en) * | 2017-12-18 | 2018-11-27 | United Microelectronics Corp. | High voltage MOS structure and its manufacturing method |
| CN111092112A (en) * | 2018-10-23 | 2020-05-01 | 合肥晶合集成电路有限公司 | MOS field effect transistor and manufacturing method thereof |
| CN111599808A (en) * | 2020-05-27 | 2020-08-28 | 合肥晶合集成电路有限公司 | Semiconductor device and method for manufacturing the same |
| CN111933696A (en) * | 2020-10-14 | 2020-11-13 | 南京晶驱集成电路有限公司 | Method for manufacturing semiconductor device |
-
2021
- 2021-09-23 CN CN202111112800.9A patent/CN113838925B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1093096A (en) * | 1996-09-19 | 1998-04-10 | Toshiba Corp | Semiconductor device and its manufacture |
| CN101236986A (en) * | 2007-02-02 | 2008-08-06 | 三星电子株式会社 | High voltage transistors and its production method |
| US20100237439A1 (en) * | 2009-03-18 | 2010-09-23 | Ming-Cheng Lee | High-voltage metal-dielectric-semiconductor device and method of the same |
| US20130092987A1 (en) * | 2011-10-13 | 2013-04-18 | Stmicroelectronics (Rousset) Sas | Mos transistor with no hump effect |
| US10141398B1 (en) * | 2017-12-18 | 2018-11-27 | United Microelectronics Corp. | High voltage MOS structure and its manufacturing method |
| CN111092112A (en) * | 2018-10-23 | 2020-05-01 | 合肥晶合集成电路有限公司 | MOS field effect transistor and manufacturing method thereof |
| CN111599808A (en) * | 2020-05-27 | 2020-08-28 | 合肥晶合集成电路有限公司 | Semiconductor device and method for manufacturing the same |
| CN111933696A (en) * | 2020-10-14 | 2020-11-13 | 南京晶驱集成电路有限公司 | Method for manufacturing semiconductor device |
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