CN113838873A - Top Com array structure - Google Patents
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- CN113838873A CN113838873A CN202111242816.1A CN202111242816A CN113838873A CN 113838873 A CN113838873 A CN 113838873A CN 202111242816 A CN202111242816 A CN 202111242816A CN 113838873 A CN113838873 A CN 113838873A
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- 238000004519 manufacturing process Methods 0.000 claims abstract description 21
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- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 19
- 230000008569 process Effects 0.000 claims abstract description 17
- 230000000903 blocking effect Effects 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 14
- 238000009413 insulation Methods 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 12
- 239000010936 titanium Substances 0.000 claims description 11
- 229910004205 SiNX Inorganic materials 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 229910052750 molybdenum Inorganic materials 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
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- 229910052759 nickel Inorganic materials 0.000 claims description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
- G06F3/0445—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
- G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
- G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention discloses a Top Com array structure, which comprises a glass substrate, wherein a grid electrode GE layer is arranged on the glass substrate, an inorganic insulating GI layer is deposited on the grid electrode GE layer, an active SE layer is arranged on the inorganic insulating GI layer, an etching blocking ES layer is arranged on the active SE layer, a source drain electrode SD layer is arranged on the etching blocking ES layer, an inorganic insulating PV layer is deposited on the source drain electrode SD layer, an organic insulating OC layer is coated on the inorganic insulating PV layer, OC holes are formed in the organic insulating OC layer, PV holes are etched in the inorganic insulating PV layer, a pixel electrode PE layer is deposited on the organic insulating OC layer, an inorganic CH layer is deposited on the pixel electrode PE layer, and a common electrode BC layer is deposited on the inorganic CH layer. Based on the prior Top-Com design principle and without changing the process technology, the invention effectively uses a photomask to dry-etch ES holes on the ES layer and PV holes on the PV layer, so that the original 9 masks are reduced to 8, thereby achieving the purposes of reducing the production cost and improving the product benefit.
Description
Technical Field
The invention belongs to the technical field of touch panels, and particularly relates to a Top Com array structure.
Background
Currently, amorphous metal oxide semiconductors are rapidly developing. The amorphous InGaZnO (IGZO) is an ideal material for preparing the TFT by virtue of a simple preparation process and excellent photoelectric properties, and the TFT prepared by the amorphous InGaZnO (IGZO) has the characteristics of high mobility, high on-off ratio and the like and has the potential of replacing a-Si. Compared with the a-Si TFT, the IGZO-TFT has the carrier mobility of 10-30cm2And V.S, the charge-discharge efficiency and the response speed of the TFT to the pixel electrode are greatly improved. More importantly, the IGZO process has good compatibility with the existing a-Si production line, and has lower investment cost compared with the Low Temperature Polysilicon (LTPS) which has more complex production process and higher equipment investment.
With the rapid development of the current display technology, the In-cell panel technology that embeds the touch panel function into the liquid crystal pixel has been widely applied to various smart phones and tablet computers. The touch panel technology mainly integrates the touch panel and the liquid crystal panel, so that the liquid crystal panel with the display function originally has the touch input function, and the touch panel technology has the greatest advantages that the thickness of the whole display screen can be effectively reduced, the reduction of the thickness can not only reduce the weight of the whole mobile phone, but also can utilize the vacated larger space for enlarging a battery or other parts and the like.
The mainstream of the current market design is mainly the Mid-com In cell technology, the design scheme needs 10 light masks to complete the Array process, mainly the touch metal Layer connected with the transparent common electrode is designed on the organic flat Layer, and only two layers of VA (inorganic Layer) and CM (touch metal Layer) are added In the process of Array. In order to simplify the process flow, the prior mass production also adopts a Top-Com design array structure of 9 photomasks, and the proposal simultaneously forms TP Line and Data Line by an SD process and reduces two processes of a CM layer and a VA layer to simplify the process flow. In order to reduce the production cost and increase the product efficiency, how to further optimize the process model on the Top-Com structure of the existing design becomes the key of the scheme improvement. To this end, we propose a Top Com array structure to solve the above mentioned problems in the background art.
Disclosure of Invention
The present invention is directed to a Top Com array structure to solve the above problems.
In order to achieve the purpose, the invention provides the following technical scheme: the Top Com array structure comprises a glass substrate, wherein a grid electrode GE layer is arranged on the glass substrate, an inorganic insulating GI layer is deposited on the grid electrode GE layer, an active SE layer is arranged on the inorganic insulating GI layer, an etching blocking ES layer is arranged on the active SE layer, a source drain electrode SD layer is arranged on the etching blocking ES layer, an inorganic insulating PV layer is deposited on the source drain electrode SD layer, an organic insulating OC layer is coated on the inorganic insulating PV layer, OC holes are formed in the organic insulating OC layer, PV holes are etched in the inorganic insulating PV layer, a pixel electrode PE layer is deposited on the organic insulating OC layer, an inorganic CH layer is deposited on the pixel electrode PE layer, and a common electrode BC layer is deposited on the inorganic CH layer.
The glass substrate is pixel glass on the TFT side, and active devices such as TFTs and the like are sequentially formed on the glass substrate.
The grid GE layer is a non-transparent grid GE layer, has low resistivity, can select metals and alloys with good conductivity such as aluminum/molybdenum/titanium/nickel/copper/and the like, and takes Mo/Al/Mo or Ti/Ai/Ti as an example;
the inorganic insulating GI layer is an insulating layer with a larger dielectric constant, and the design scheme can select SiOx or SiNx;
the active SE layer is a TFT device semiconductor layer, such as a-Si, MOx, LTPS and the like, and IGZO can be selected according to the design scheme;
the etching barrier ES layer is provided with an insulating layer with a larger dielectric constant, and the active SE layer of the channel region is protected from being etched by the source drain electrode SD layer through gas or liquid;
the source drain electrode SD layer takes Mo/Al/Mo or Ti/Ai/Ti as an example;
the inorganic insulation PV layer is provided with an insulation layer with a larger dielectric constant, and SiOx or SiNx can be selected according to the design scheme;
the organic insulating OC layer is mainly made of organic materials, covers the insulating layer, is used for flattening the surface of the TFT device, and develops OC holes through exposure;
the PE layer of the pixel electrode is transparent conductive ITO;
the inorganic CH layer is an insulating layer with a larger dielectric constant, and SiOx and SiNx can be selected according to the design scheme;
the common electrode BC layer is made of transparent conductive ITO.
A manufacturing process of a Top Com array structure specifically comprises the following steps:
s1, manufacturing a gate GE layer on the glass substrate of the substrate;
s2, depositing an inorganic insulating GI layer on the grid electrode GE layer;
s3, manufacturing an active SE layer on the inorganic insulating GI layer;
s4, manufacturing an etching barrier ES layer on the active SE layer;
s5, manufacturing a source drain electrode SD layer on the etching barrier ES layer by layer;
s6, depositing an inorganic insulation PV layer on the source drain electrode SD layer;
s7, coating an organic insulating OC layer on the inorganic insulating PV layer, and forming OC holes;
s8, etching the PV hole by adopting the mask exposure and development of the same ES layer;
s9, depositing a pixel electrode PE layer on the organic insulation OC layer;
s10, depositing an inorganic CH layer on the PE layer of the pixel electrode;
s11, depositing a common electrode BC layer on the inorganic CH layer.
Compared with the prior art, the invention has the beneficial effects that: the invention provides a Top Com array structure, which is based on the existing Top-Com design principle and under the condition of not changing the process technology, by effectively using a Mask (i.e. an ES layer and an inorganic insulation PV layer are etched to form a common Mask), ES holes are etched on an ES layer in a dry mode, PV holes are etched on a PV layer in a dry mode, 9 original masks are reduced to 8, and therefore the purposes of reducing the production cost and improving the product benefit are achieved.
Drawings
FIG. 1 is a schematic structural diagram of step S1 according to the present invention;
FIG. 2 is a schematic structural diagram of step S2 according to the present invention;
FIG. 3 is a schematic structural diagram of step S3 according to the present invention;
FIG. 4 is a schematic structural diagram of step S4 according to the present invention;
FIG. 5 is a schematic structural diagram of step S5 according to the present invention;
FIG. 6 is a schematic structural diagram of step S6 according to the present invention;
FIG. 7 is a schematic structural diagram of step S7 according to the present invention;
FIG. 8 is a schematic structural diagram of step S8 according to the present invention;
FIG. 9 is a schematic structural diagram of step S9 according to the present invention;
FIG. 10 is a schematic structural diagram of step S10 according to the present invention;
FIG. 11 is a schematic structural diagram of step S11 according to the present invention;
FIG. 12 is a schematic diagram of an array structure designed for mass production of Top-com.
In the figure: 1. a glass substrate; 2. a gate GE layer; 3. an inorganic insulating GI layer; 4. an active SE layer; 5. etching the barrier ES layer; 6. a source drain electrode SD layer; 7. an inorganic insulating PV layer; 8. an organic insulating OC layer; 9. a pixel electrode PE layer; 10. an inorganic CH layer; 11. a common electrode BC layer; 12. an OC hole; 13. a PV aperture.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1: the invention provides a Top Com array structure as shown in fig. 1-11, comprising a glass substrate 1, a grid electrode GE layer 2 is arranged on the glass substrate 1, an inorganic insulating GI layer 3 is deposited on the grid electrode GE layer 2, an active SE layer 4 is arranged on the inorganic insulating GI layer 3, an etching barrier ES layer 5 is arranged on the active SE layer 4, a source drain electrode SD layer 6 is arranged on the etching barrier ES layer 5, an inorganic insulating PV layer 7 is deposited on the source drain electrode SD layer 6, an organic insulating OC layer 8 is coated on the inorganic insulating PV layer 7, and an OC hole 12 is opened on the organic insulating OC layer 8, a PV hole 13 is etched on the inorganic insulating PV layer 7, a pixel electrode PE layer 9 is deposited on the organic insulation OC layer 8, an inorganic CH layer 10 is deposited on the pixel electrode PE layer 9, and a common electrode BC layer 11 is deposited on the inorganic CH layer 10.
The glass substrate 1 is a TFT-side mother glass on which active devices such as TFTs are sequentially formed.
The grid GE layer 2 is a non-transparent grid GE layer, has low resistivity, can select metals and alloys with excellent conductivity such as aluminum/molybdenum/titanium/nickel/copper/and the like, and takes Mo/Al/Mo or Ti/Ai/Ti as an example;
the inorganic insulating GI layer 3 is an insulating layer with a larger dielectric constant, and SiOx or SiNx can be selected according to the design scheme;
the active SE layer 4 is a TFT device semiconductor layer, such as a-Si, MOx, LTPS and the like, and IGZO can be selected according to the design scheme;
the etching barrier ES layer 5 is an insulating layer with a large dielectric constant, and the active SE layer 4 in the channel region is protected from being etched by etching gas or liquid of the source drain SD layer 6;
the source drain electrode SD layer 6 takes Mo/Al/Mo or Ti/Ai/Ti as an example;
the inorganic insulating PV layer 7 has an insulating layer with a larger dielectric constant, and SiOx or SiNx can be selected according to the design scheme;
the organic insulating OC layer 8 is mainly made of organic materials, covers the insulating layer, is used for flattening the surface of the TFT device, and develops an OC hole 12 through exposure;
the pixel electrode PE layer 9 is transparent conductive ITO;
the inorganic CH layer 10 is an insulating layer with a large dielectric constant, and SiOx and SiNx can be selected according to the design scheme;
the material of the common electrode BC layer 11 is transparent conductive ITO.
A manufacturing process of a Top Com array structure specifically comprises the following steps:
s1, manufacturing a gate GE layer 2 on the glass substrate 1 of the substrate;
s2, depositing an inorganic insulating GI layer 3 on the gate GE layer 2;
s3, fabricating an active SE layer 4 on the inorganic insulating GI layer 3;
s4, manufacturing an etching barrier ES layer 5 on the active SE layer 4;
s5, manufacturing a source drain electrode SD layer 6 on the etching barrier ES layer 5;
s6, depositing an inorganic insulation PV layer 7 on the source drain electrode SD layer 6;
s7, coating an organic insulating OC layer 8 on the inorganic insulating PV layer 7, and forming OC holes 12;
s8, etching the PV hole 13 by using the mask of the same ES layer;
s9, depositing a pixel electrode PE layer 9 on the organic insulation OC layer 8;
s10, depositing an inorganic CH layer 10 on the PE layer 9 of the pixel electrode;
s11, a common electrode BC layer 11 is deposited on the inorganic CH layer 10.
The conventional In-Cell technology is a method of embedding a touch panel function into a liquid crystal pixel, thereby realizing an integrated design of a touch panel component and a liquid crystal panel. The current market design mainstream mainly uses the Mid-Com In cell technology, the design scheme needs 10 photomasks to complete the array process, for simplifying the process flow, as shown In fig. 12, the existing mass production also adopts a Top-Com design array structure of 9 photomasks, the scheme simultaneously forms TP Line and Data Line through the SD process, and two processes of a CM layer and a VA layer are reduced to simplify the process flow.
In summary, compared with the prior art, the invention effectively uses a Mask (the etching blocks the ES layer 5 and the inorganic insulating PV layer 7 to share the Mask) to dry-etch the ES layer to form the ES hole and dry-etch the PV layer to form the PV hole 13 by using the Mask (the etching blocks the ES layer 5 and the inorganic insulating PV layer 7 to share the Mask) on the basis of the prior Top-Com design principle and without changing the process technology, so that the prior 9 Mask Top-Com design reduces 1 Mask compared with the mainstream 10 Mask Mid-Com design.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments or portions thereof without departing from the spirit and scope of the invention.
Claims (9)
1. A Top Com array structure, includes glass substrate (1), its characterized in that: a grid GE layer (2) is arranged on the glass substrate (1), an inorganic insulating GI layer (3) is deposited on the grid GE layer (2), an active SE layer (4) is arranged on the inorganic insulating GI layer (3), an etching barrier ES layer (5) is arranged on the active SE layer (4), a source drain electrode SD layer (6) is arranged on the etching blocking ES layer (5), an inorganic insulating PV layer (7) is deposited on the source drain electrode SD layer (6), an organic insulating OC layer (8) is coated on the inorganic insulating PV layer (7), and an OC hole (12) is arranged on the organic insulation OC layer (8), a PV hole (13) is etched on the inorganic insulation PV layer (7), a pixel electrode PE layer (9) is deposited on the organic insulation OC layer (8), an inorganic CH layer (10) is deposited on the pixel electrode PE layer (9), and a common electrode BC layer (11) is deposited on the inorganic CH layer (10).
2. The Top Com array structure of claim 1, wherein: the glass substrate (1) is pixel glass on the TFT side, and TFT active devices are sequentially formed on the glass substrate.
3. The Top Com array structure of claim 1, wherein: the grid GE layer (2) is made of aluminum, molybdenum, titanium, nickel, copper or alloy.
4. The Top Com array structure of claim 1, wherein: the inorganic insulating GI layer (3) is made of SiOx or SiNx.
5. The Top Com array structure of claim 1, wherein: the active SE layer (4) is a TFT device semiconductor layer and is made of a-Si, MOx, LTPS or IGZO.
6. The Top Com array structure of claim 1, wherein: the inorganic insulating PV layer (7) is made of SiOx or SiNx.
7. The Top Com array structure of claim 1, wherein: the material of the inorganic CH layer (10) is SiOx or SiNx.
8. The Top Com array structure of claim 1, wherein: the common electrode BC layer (11) is made of transparent conductive ITO.
9. A process for fabricating the Top Com array structure of any of claims 1-8, wherein: the method specifically comprises the following steps:
s1, manufacturing a gate GE layer (2) on the glass substrate (1) of the substrate;
s2, depositing an inorganic insulating GI layer (3) on the gate GE layer (2);
s3, manufacturing an active SE layer (4) on the inorganic insulating GI layer (3);
s4, manufacturing an etching barrier ES layer (5) on the active SE layer (4);
s5, manufacturing a source drain electrode SD layer (6) on the etching barrier ES layer (5);
s6, depositing an inorganic insulation PV layer (7) on the source drain electrode SD layer (6);
s7, coating an organic insulating OC layer (8) on the inorganic insulating PV layer (7), and forming OC holes (12);
s8, etching a PV hole (13) by adopting the mask exposure and development of the same ES layer;
s9, depositing a pixel electrode PE layer (9) on the organic insulation OC layer (8);
s10, depositing an inorganic CH layer (10) on the PE layer (9) of the pixel electrode;
s11, depositing a common electrode BC layer (11) on the inorganic CH layer (10).
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114327143A (en) * | 2021-12-30 | 2022-04-12 | 福建华佳彩有限公司 | Method for improving dark spots of active pen technology |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114327143A (en) * | 2021-12-30 | 2022-04-12 | 福建华佳彩有限公司 | Method for improving dark spots of active pen technology |
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