CN113838808A - Side exhaust substrate and manufacturing method thereof - Google Patents

Side exhaust substrate and manufacturing method thereof Download PDF

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Publication number
CN113838808A
CN113838808A CN202110926634.XA CN202110926634A CN113838808A CN 113838808 A CN113838808 A CN 113838808A CN 202110926634 A CN202110926634 A CN 202110926634A CN 113838808 A CN113838808 A CN 113838808A
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China
Prior art keywords
layer
copper
circuit
insulating layer
copper column
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CN202110926634.XA
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Chinese (zh)
Inventor
陈先明
冯磊
谭洪卫
黄本霞
洪业杰
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Zhuhai Yueya Semiconductor Co ltd
Zhuhai Access Semiconductor Co Ltd
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Zhuhai Yueya Semiconductor Co ltd
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Priority to CN202110926634.XA priority Critical patent/CN113838808A/en
Publication of CN113838808A publication Critical patent/CN113838808A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention discloses a side exhaust substrate which comprises a first insulating layer and a second insulating layer on the first insulating layer, wherein an exhaust channel is arranged in the second insulating layer, and the exhaust channel comprises an air inlet penetrating through the second insulating layer and a first exhaust hole which is positioned on the side edge of the second insulating layer and is transversely communicated with the exhaust channel. A method of manufacturing a side vented substrate is also disclosed.

Description

Side exhaust substrate and manufacturing method thereof
Technical Field
The invention relates to an electronic device packaging structure, in particular to a side exhaust substrate and a manufacturing method thereof.
Background
With the development of semiconductor packaging technology, multi-device high-density integrated packaging is becoming a current and future trend. Accordingly, the packaging method and the packaging structure have diversified developments. Wherein, after being mounted, parts of the chips and other components need to be protected by applying a metal or other material shade so as to avoid being interfered by external radiation or prevent external electronic components from being influenced by internal electronic components. However, during the process of applying the mask and packaging, reflow soldering is usually required, and air inside the mask is heated to generate convection during reflow soldering, which easily causes mask deviation, and may cause unstable mask, poor shielding effect, electrical short circuit, and the like; furthermore, during the packaging process, the mask and the substrate form a relatively closed space, and the internal air expands due to heat in the relatively closed cavity, which may cause deformation and failure of internal components, and even cause the package to explode.
In the prior art, there are two main technical schemes: the first technique is that no vent hole is arranged, and in the process of applying the mask, the air inside a closed cavity formed by the mask and the substrate is heated to expand, so that the mask is easy to deviate and even explode; the second technical solution is to preset vent holes, usually NPTH (non-plated through hole) is selected as a vent hole on the substrate, the vent holes penetrate through the upper surface and the lower surface of the substrate, and are usually formed by mechanical drilling, laser drilling, or punching. Because the exhaust holes in the prior art are through holes and penetrate through the upper surface and the lower surface of the substrate, when the packaging body is used at a subsequent terminal, solder paste or packaging filler easily permeates from the exhaust holes in the process of welding or packaging the other surface of the substrate, and the problems of short circuit and the like are caused.
Disclosure of Invention
Embodiments of the present invention are directed to providing a side vent substrate and a method of manufacturing the same to solve the above-mentioned problems. In the processing process of the substrate, a sacrificial circuit and a sacrificial copper column are preset, and the sacrificial circuit and the sacrificial copper column are etched after the substrate is prepared, so that an exhaust channel with an outlet at the side edge of the substrate is formed; when applying the encapsulation lid and encapsulating, the cavity air that encapsulation lid and base plate formed receives the thermal expansion, can exhaust through exhaust passage, avoids the encapsulation lid to lead to the skew of encapsulation lid because of the air thermal expansion to guarantee the protection and the shielding effect of encapsulation body, and exhaust passage's exhaust hole is at the base plate side, and when follow-up welding or the encapsulation of another side to the encapsulation body, can avoid tin cream or encapsulation filler to arouse the short circuit from exhaust passage infiltration. Meanwhile, the exhaust channel can also be used for sucking and sealing to form a vacuum environment or injecting other gases such as inert gases so as to meet the special environmental requirements of components.
The invention relates to a side exhaust substrate, which comprises a first insulating layer and a second insulating layer on the first insulating layer, wherein an exhaust channel is arranged in the second insulating layer, and the exhaust channel comprises an air inlet penetrating through the second insulating layer and a first exhaust hole which is positioned on the side edge of the second insulating layer and transversely communicates with the exhaust channel.
In some embodiments, the exhaust channel is between a lower surface of the second insulating layer and an upper surface of the first insulating layer.
In some embodiments, a hermetic shield is disposed on the second insulating layer, the air intake holes of the exhaust channel being covered within the shield.
In some embodiments, the exhaust channel further comprises a second exhaust hole that extends through the second insulating layer and is not covered by the mask.
In some embodiments, a first circuit layer is disposed in a lower surface of the first insulating layer, a first copper pillar layer is disposed on the first circuit layer, a second circuit layer is disposed in a lower surface of the second insulating layer, a second copper pillar layer is disposed on the second circuit layer, a third circuit layer is disposed on the second insulating layer, the first circuit layer and the second circuit layer are in conductive connection through the first copper pillar layer, and the second circuit layer and the third circuit layer are in conductive connection through the second copper pillar layer.
A second aspect of the present invention provides a method for manufacturing a side vent substrate, including the steps of:
(a) preparing a temporary bearing plate;
(b) forming a first circuit layer on at least one side of the temporary bearing plate;
(c) forming a first copper column layer on the first circuit layer, laminating a first insulating layer on the first copper column layer, and thinning the first insulating layer to expose the first copper column layer;
(d) forming a second circuit layer on the first insulating layer, so that the first circuit layer and the second circuit layer are in conductive connection through the first copper column layer, and the second circuit layer comprises a sacrificial circuit;
(e) forming a second copper column layer on the second circuit layer, wherein the second copper column layer comprises a sacrificial copper column, the sacrificial copper column is formed on the sacrificial circuit, a second insulating layer is laminated on the second copper column layer, and the second insulating layer is thinned to expose the second copper column layer;
(f) forming a third circuit layer on the second insulating layer, so that the second circuit layer and the third circuit layer are in conductive connection through the second copper column layer;
(g) removing the temporary bearing plate;
(h) and etching the sacrificial copper column and the sacrificial line to form an exhaust channel.
Preferably, the manufacturing method further includes:
(i) and h, mounting a component on the surface of the third circuit layer, routing, and applying a packaging cover to cover the component and the air inlet hole of the exhaust channel, so that the exhaust hole of the exhaust channel is positioned outside the packaging cover.
Preferably, the temporary carrier plate comprises a copper-clad plate with at least one surface covered with a double-layer copper foil, wherein the copper-clad plate comprises a core layer, a first copper layer on the surface of the core layer and a second copper layer on the first copper layer, and the first copper layer and the second copper layer are adhered together through physical pressing. Preferably, the core layer comprises a prepreg, the first copper layer has a thickness of 18 μm and the second copper layer has a thickness of 3 μm.
Preferably, step (g) comprises removing the temporary carrier plate by physically separating the first and second copper layers and etching the second copper layer.
In some embodiments, step (b) comprises:
(b1) forming a first metal seed layer on at least one side of the temporary bearing plate;
(b2) applying a first photoresist layer on the first metal seed layer, and exposing and developing to form a first characteristic pattern;
(b3) electroplating to form a first circuit layer in the first characteristic pattern;
(b4) removing the first photoresist layer.
In some embodiments, step (c) comprises:
(c1) applying a second photoresist layer on the first circuit layer, and exposing and developing to form a second characteristic pattern;
(c2) electroplating to form a first copper column layer in the second characteristic pattern;
(c3) removing the second photoresist layer;
(c4) applying a first insulating layer on the first copper pillar layer and thinning the first insulating layer to expose the first copper pillar layer.
In some embodiments, step (d) comprises:
(d1) forming a second metal seed layer on the first insulating layer;
(d2) applying a third photoresist layer on the second metal seed layer, and exposing and developing to form a third characteristic pattern;
(d3) electroplating to form a second circuit layer in the third feature pattern, wherein the second circuit layer comprises a conducting circuit and a sacrificial circuit, so that the first circuit layer and the conducting circuit are in conducting connection through the first copper column layer;
(d4) removing the third photoresist layer.
In some embodiments, step (e) comprises:
(e1) applying a fourth photoresist layer on the second circuit layer, and exposing and developing to form a fourth characteristic pattern;
(e2) electroplating to form a second copper column layer in the fourth feature pattern, wherein the second copper column layer comprises a sacrificial copper column and a conductive copper column, so that the sacrificial copper column is connected with the sacrificial line, and the conductive copper column is connected with the conductive line;
(e3) removing the fourth photoresist layer, and etching the second metal seed layer;
(e4) and forming a second insulating layer on the second copper column layer, and thinning the second insulating layer to expose the second copper column layer.
Preferably, the metal seed layer comprises titanium, copper, titanium tungsten alloy, or a combination thereof.
In some embodiments, step (f) comprises:
(f1) forming a third metal seed layer on the second insulating layer;
(f2) applying a fifth photoresist layer on the third metal seed layer, and exposing and developing to form a fifth characteristic pattern;
(f3) electroplating to form a third circuit layer in the fifth characteristic pattern;
(f4) and removing the fifth photoresist layer and etching the third metal seed layer.
Preferably, the metal seed layer comprises titanium, copper, titanium tungsten alloy, or a combination thereof.
In some embodiments, the manufacturing method further comprises forming an etch barrier layer on at least one side of the temporary carrier plate before step (b).
Preferably, the etch stop layer comprises nickel, titanium, or a combination thereof; more preferably, the etch stop layer is selected from nickel.
Drawings
For a better understanding of the invention and to show embodiments thereof, reference is made to the accompanying drawings, purely by way of example.
With specific reference to the drawings, it must be emphasized that the specific illustrations are exemplary and are merely intended to illustratively discuss a preferred embodiment of the invention, and are presented in order to provide what is believed to be the most useful and readily understood illustration of the principles and conceptual aspects of the invention. In this regard, no attempt is made to show structural details of the invention in more detail than is necessary for a fundamental understanding of the invention; those skilled in the art will recognize how the several forms of the present invention may be embodied in practice with reference to the description of the figures. In the drawings:
FIG. 1 is a schematic cross-sectional view of a side vented substrate according to one embodiment of the present invention;
fig. 2(a) to 2(s) are schematic cross-sectional views of intermediate structures of respective steps of a method for manufacturing a side-vent substrate according to an embodiment of the present invention.
Detailed Description
Referring to fig. 1, a cross-sectional view of a side vent substrate 100 is shown. The side exhaust substrate 100 includes a first insulating layer 101 and a second insulating layer 102 located on the first insulating layer 101, an exhaust channel 104 is disposed in the second insulating layer 102, an air inlet of the exhaust channel 104 penetrates the second insulating layer 102 from the exhaust channel 104, and a first air outlet of the exhaust channel 104 is located at a side of the second insulating layer 102. The first insulating layer 101 and the second insulating layer 102 may include the same material or may include different materials; an insulating resin or a glass fiber reinforced resin may be included.
A hermetic mask, such as a sealing cover, in which the intake holes of the exhaust passages 104 should be covered, may be disposed on the second insulating layer 102 of the substrate 100. The exhaust passage 104 may further include a second exhaust hole that penetrates the second insulating layer 102 upward from the exhaust passage 104 and is not covered by the mask.
The first exhaust hole of exhaust passage 104 is located the side of second insulating layer 102, when applying the shade and encapsulating like the encapsulation lid, the air can be heated and expanded in the cavity that encapsulation lid and base plate 100 formed, expanded air can be discharged through exhaust passage 104, avoid the encapsulation lid to lead to the skew of encapsulation lid because of the air is heated and expanded, thereby guarantee the protection and the shielding effect of packaging body, and exhaust passage's exhaust hole is at the base plate side, during the follow-up encapsulation of welding or another side to the packaging body, can avoid tin cream or encapsulation filler to arouse the short circuit from exhaust passage infiltration. Preferably, the exhaust passage 104 may be between an upper surface of the first insulation layer 101 and a lower surface of the second insulation layer 102.
As shown in fig. 1, a first circuit layer 1015 is disposed in a lower surface of the first insulating layer 101, and a first copper pillar layer 1017 is disposed on the first circuit layer 1015; the end of the first copper pillar layer 1017 may be flush with the first insulating layer 101 or higher than the first insulating layer 101; the first copper pillar layer 1017 includes at least one conductive copper pillar, and preferably, the first copper pillar layer 1017 includes a plurality of conductive copper pillars as IO channels, and the cross-sectional dimensions thereof may be the same or different. The first copper pillar layer 1017 has uniform vertical dimensions, and has more advantages for heat dissipation and signal transmission stability of the embedded packaging structure.
A second circuit layer 1023 is arranged in the lower surface of the second insulating layer 102, and a second copper pillar layer 1025 is arranged on the second circuit layer 1023; the end of the second copper pillar layer 1025 can be flush with the second insulating layer 102 or higher than the second insulating layer 102; the second copper pillar layer 1025 comprises at least one conductive copper pillar, and preferably, the second copper pillar layer 1025 comprises a plurality of conductive copper pillars as IO channels, which may have the same or different cross-sectional dimensions. The second copper pillar layer 1025 has uniform top and bottom dimensions, and is more advantageous for heat dissipation and signal transmission stability of the embedded package structure.
A third circuit layer 1028 is disposed on the second insulating layer 102, the first circuit layer 1015 and the second circuit layer 1023 are conductively connected through the first copper pillar layer 1017, and the second circuit layer 1023 and the third circuit layer 1028 are conductively connected through the second copper pillar layer 1025.
Referring to fig. 2(a) to 2(s), there are shown schematic cross-sectional views of intermediate structures of the respective steps of the method for manufacturing a side-vent substrate according to one embodiment of the present invention.
The manufacturing method comprises the following steps: a temporary carrier plate is prepared and an etch barrier 1012 is applied on at least one side of the temporary carrier plate-step (a), as shown in fig. 2 (a). The temporary carrying plate comprises a core layer 1011a, which can be a prepreg, wherein the core layer 1011a is sequentially provided with a first copper layer 1011b on the surface of the core layer 1011a and a second copper layer 1011c on the surface of the first copper layer 1011 b; the first copper layer 1011b and the second copper layer 1011c are formed by physically pressing copper foils, and the first copper layer 1011b and the second copper layer 1011c can be physically separated, so that the temporary bearing plate can be conveniently removed in the subsequent process; the thicknesses of the first copper layer 1011b and the second copper layer 1011c may be adjusted as required, and preferably, the thickness of the first copper layer 1011b is 18 μm and the thickness of the second copper layer 1011c is 3 μm. Generally, the etching barrier layer 1012, the first photoresist layer 1012 and the exposure and development may be applied to both sides of the temporary carrier plate to form the first feature pattern, and in the following, the single unit on both sides of the temporary carrier plate is illustrated in this embodiment, but it is not limited that the following operations must be performed on both sides of the temporary carrier plate at the same time. In the subsequent process of removing the temporary carrier, when the second copper foil layer 1011b is etched after the board separation, the etching stop layer 1012 can protect the circuit layer and the copper pillar layer of the substrate, thereby avoiding over-etching. Etch stop layer 1012 may comprise nickel, titanium, or combinations thereof, for example, an 8-15 μm nickel layer; the thickness of the etching barrier layer 1012 can be adjusted according to actual needs, and preferably, the thickness of the etching barrier layer 1012 is 3 to 10 μm.
Next, a first metal seed layer 1013 is formed on the etch stop layer 1012, step (b), as shown in fig. 2 (b). Generally, a first metal seed layer 1013 may be formed on the etching barrier layer 1012 by electroless plating or sputtering, the first metal seed layer 1013 may include titanium, copper, titanium tungsten alloy or a combination thereof, and the thickness of the first metal seed layer 1013 is in a range of 1-3 μm; preferably, the first metal seed layer 1013 is made by sputtering titanium and copper.
Then, a first photoresist layer 1014 is applied on the first metal seed layer 1013, exposed and developed to form a first feature pattern, step (c), as shown in fig. 2 (c). Generally, the first photoresist layer 1014 can be applied on the first metal seed layer 1013 by means of pasting or coating; the thickness of the first photoresist layer 1014 can be adjusted as desired.
Next, a first line layer 1015 is formed by electroplating in the first feature pattern, and the first photoresist layer 1014 is removed, step (d), as shown in FIG. 2 (d). Generally, the thickness of the first circuit layer 1015 can be adjusted as desired, and generally the thickness of the first circuit layer 1015 is not higher than the thickness of the first photoresist layer 1014. The first photoresist layer 1014 may be removed by stripping.
Then, a second photoresist layer 1016 is applied on the first line layer 1015, exposed and developed to form a second feature pattern, step (e), as shown in fig. 2 (e). Typically, the second photoresist layer 1016 may be applied on the first line layer 1015 by means of pasting or coating; the thickness of the second photoresist layer 1016 may be adjusted as desired.
Next, a first copper pillar layer 1017 is formed by electroplating in the second feature pattern, the second photoresist layer 1016 is removed, a first insulating layer 101 is applied on the first copper pillar layer 1017, and the first insulating layer 101 is thinned to expose the first copper pillar layer 1017 — step (f), as shown in fig. 2 (f). Generally, after the first copper column layer 1017 is formed, brown oxidation treatment can be performed on the surface of the first copper column layer 1017, so that the bonding force between the first copper column layer 1017 and the first insulating layer 101 coated outside the first copper column layer 1017 is increased; the shape of the first copper pillar layer 1017 may be set according to actual needs, for example, it may be square, circular, and the like, and is not limited specifically. The first copper pillar layer 1017 may include at least one conductive copper pillar, and the first copper pillar layer 1017 may include conductive copper pillars having different sizes; the thickness of the first copper pillar layer 1017 can be adjusted according to actual needs, and usually, the thickness of the first copper pillar layer 1017 is not higher than the thickness of the second photoresist layer 1016; the first copper pillar layer 1017 has uniform vertical dimensions, and has more advantages for heat dissipation and signal transmission stability of the embedded packaging structure. The second photoresist layer 1016 may be removed by stripping. In general, the first insulating layer 101 may be formed on the first copper pillar layer 1017 by means of lamination or vacuum heat pressing. Generally, the first insulating layer 101 may be thinned entirely by way of plate grinding or plasma etching to expose the end portions of the first copper pillar layer 1017; the first insulating layer 101 may also be locally thinned by laser or drilling to expose the end of the first copper pillar layer 1017; preferably, the first insulating layer 101 is thinned entirely by way of plate grinding or plasma etching.
Then, a second metal seed layer 1021 is formed on the first insulating layer 101, a third photoresist layer 1022 is applied on the second metal seed layer 1021, and a third feature pattern is formed by exposure and development, step (g), as shown in fig. 2 (g). Generally, the second metal seed layer 1021 may be formed on the first insulating layer 101 by electroless plating or sputtering, and the second metal seed layer 1021 may include titanium, copper, titanium tungsten alloy, or a combination thereof; preferably, titanium and copper are sputtered to make the second metal seed layer 1021. The third photoresist layer 1022 may be applied by film pasting or coating, and the thickness of the third photoresist layer 1022 may be adjusted according to actual requirements.
Next, a second circuit layer 1023 is formed in the third feature pattern by electroplating, the second circuit layer 1023 includes a conductive trace 1023a and a sacrificial trace 1023b, so that the first circuit layer 1015 and the conductive trace 1023a are conductively connected through the first copper pillar layer 1017, and the third photoresist layer 1022 is removed (h), as shown in fig. 2 (h). Generally, the thickness of the second circuit layer 1023 can be adjusted according to actual needs, and the thickness of the second circuit layer 1023 is usually not higher than the thickness of the third photoresist layer 1022; the sacrificial wiring 1023b is used for the subsequent preparation of the exhaust passage, and the thickness of the sacrificial wiring 1023b can be adjusted according to the expected size of the exhaust passage. The third photoresist layer 1022 may be removed by stripping.
Then, a fourth photoresist layer 1024 is applied on the second circuit layer 1023, exposed and developed to form a fourth feature pattern, and a second copper pillar layer 1025 is electroplated in the fourth feature pattern, the second copper pillar layer 1025 includes a sacrificial copper pillar 1025b and a conductive copper pillar 1025a, the sacrificial copper pillar 1025b is formed on the sacrificial circuit 1023b, and the conductive copper pillar 1025a is connected with the conductive circuit 1023a (i), as shown in fig. 2 (i). Generally, after the conductive copper pillar 1025a is formed, the surface of the conductive copper pillar 1025a can be subjected to brown oxidation treatment, so that the bonding force between the conductive copper pillar 1025a and the second insulating layer 102 coated outside the conductive copper pillar 1025a is increased; the shape of the second copper pillar layer 1025 may be set according to actual needs, for example, it may be square, circular, etc., and is not limited specifically. The second copper pillar layer 1025 may include at least one conductive copper pillar 1025a and at least one sacrificial copper pillar 1025b, the second copper pillar layer 1025 may include conductive copper pillars 1025a of different sizes; the thickness of the second copper pillar layer 1025 can be adjusted according to actual needs, and generally, the thickness of the second copper pillar layer 1025 is not higher than that of the fourth photoresist layer 1024; the conductive copper pillar 1025a has uniform vertical dimensions, and is more advantageous for heat dissipation and signal transmission stability of the embedded package structure. The sacrificial copper posts 1025b are connected to the sacrificial lines 1023b to facilitate subsequent fabrication of the exhaust channel, and the thickness of the sacrificial copper posts 1025b can be adjusted according to the expected size of the exhaust channel. The fourth photoresist layer 1024 may be applied on the second circuit layer by means of pasting or coating.
Next, the fourth photoresist layer 1024 is removed, and the second metal seed layer 1021 is etched (step (j)), as shown in FIG. 2 (j). Typically, the fourth photoresist layer 1024 may be removed by stripping.
Then, a second insulating layer 102 is formed over the second copper pillar layer 1025, and the second insulating layer 102 is thinned to expose the second copper pillar layer — step (k), as shown in fig. 2 (k). Generally, the second insulating layer 102 may be formed on the second copper pillar layer 1025 by lamination or vacuum hot pressing, and the second insulating layer 102 may be a pure resin or a resin containing glass fiber as a reinforcing material. Typically, the second insulating layer 102 may be thinned entirely by lapping or plasma etching to expose the ends of the second copper pillar layer 1025; the second insulating layer 102 may also be locally thinned by laser or drilling to expose the ends of the second copper pillar layer 1025; preferably, the second insulating layer 102 is thinned entirely by way of plate grinding or plasma etching.
Next, a third metal seed layer 1026 is formed on the second insulating layer 102, a fifth photoresist layer 1027 is applied on the third metal seed layer 1026, and a fifth feature pattern is formed by exposure and development, step (l), as shown in fig. 2 (l). Generally, a third metal seed layer 1026 may be formed on the second insulating layer 102 by electroless plating or sputtering, and the third metal seed layer 1026 may include titanium, copper, a titanium-tungsten alloy, or a combination thereof; preferably, titanium and copper are sputtered to produce the third metal seed layer 1026. The fifth photoresist layer 1027 may be applied by film or coating.
Then, a third circuit layer 1028 is electroplated in the fifth feature pattern, the fifth photoresist layer 1027 is removed, and the third metal seed layer 1026 is etched, step (m), as shown in fig. 2 (m). Generally, the thickness of the third circuit layer 1028 may be adjusted according to actual needs, and the thickness of the third circuit layer 1028 is lower than the thickness of the fifth photoresist layer 1027; the third circuit layer 1028 and the conductive line 1023a are conductively connected by a conductive copper pillar 1025 a. The fifth photoresist layer 1027 may be removed by stripping. It should be noted that, in the embodiment, only three layers are taken as an example, and in practical application, more layers can be continuously manufactured according to the above layer adding method to meet the requirements of different product structures.
Next, a sixth photoresist layer 1029 is applied to the third circuit layer 1028 and cured by exposure, and the first copper layer 1011b and the second copper layer 1011c are separated, step (n), as shown in fig. 2 (n). Usually, the sixth photoresist layer 1029 is applied to protect the third circuit layer 1028 when the temporary carrier is removed; the sixth photoresist layer 1029 may be applied by film or coating.
Then, the second copper layer 1011c, the etch stop layer 1012 and the first metal seed layer 1013 are etched, and the sixth photoresist layer 1029 is removed (step (o)), as shown in fig. 2 (o). Typically, the etch stop layer may be etched away by a specific chemical, for example, etching away the etch stop layer with an etching nickel chemical. The sixth photoresist layer 1029 may be removed by stripping.
Next, a seventh photoresist layer 1030 is applied on the third circuit layer 1028, exposed and developed to expose the ends of the sacrificial copper posts 1025b, step (p), as shown in FIG. 2 (p).
Then, the sacrificial copper pillar 1025b, the sacrificial line 1023b, and the second metal seed layer 1021 at the bottom of the sacrificial line 1023b are etched to form the exhaust channel 104, and the seventh photoresist layer 1030 is removed to obtain the substrate 100, step (q), as shown in FIG. 2 (q). Etching the sacrificial copper pillar 1025b, the sacrificial line 1023b and the second metal seed layer 1021 at the bottom of the sacrificial line 1023b to form an exhaust channel 104 at the positions of the sacrificial copper pillar 1025b and the sacrificial line 1023 b; the air intake holes of the air exhaust channels 104 are located on the upper surface of the second insulation layer 102, and the air exhaust holes are located on the side edges of the second insulation layer 102 and the upper surface of the second insulation layer 102.
Next, the device 105 is surface mounted on the third circuit layer 1028, wire bonding is performed, and the package cover 106 is applied to cover the device 105 and the air inlet holes of the exhaust channel 104, so that the air outlet holes of the exhaust channel 104 are located outside the package cover 106 — step (r), as shown in fig. 2 (r). The exhaust path of the exhaust channel is as shown by the arrow in the figure, and during the process of applying the encapsulation cover 106, the air in the cavity formed by the encapsulation cover 106 and the substrate 100 expands due to heat, and the air can be exhausted through the exhaust channel 104, so as to prevent the encapsulation cover 106 from bursting open.
Alternatively, the exhaust channel 104 may be used to suck the gas in the package cover 106, and after the suction, a vacuum may be formed in the package cover 106 by sealing the exhaust hole, so as to satisfy the application environment where the component 105 needs to be in vacuum. As another alternative, the exhaust passage 104 may also be used as a passage for injecting other gases such as inert gas. In this case, an inert gas, for example, may be injected into the encapsulation cover 106 from an exhaust hole outside the encapsulation cover 106 through the exhaust passage 104 to satisfy an application environment where the component 105 needs to be protected by the inert gas, for example.
Finally, dicing is performed along the dicing streets to form the package structure 200 — step(s), as shown in fig. 2(s). The cutting path is shown by a dotted line in the figure.
Those skilled in the art will recognize that the present invention is not limited to what has been particularly shown and described hereinabove and hereinbelow. Rather, the scope of the present invention is defined by the appended claims, including both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description.
In the claims, the terms "comprise" and variations such as "comprises," "comprising," and the like, mean that the recited elements are included, but generally not the exclusion of other elements.

Claims (17)

1. A side exhaust substrate comprises a first insulating layer and a second insulating layer on the first insulating layer, wherein an exhaust channel is arranged in the second insulating layer, and the exhaust channel comprises an air inlet penetrating through the second insulating layer and a first exhaust hole which is positioned on the side edge of the second insulating layer and transversely conducts the exhaust channel.
2. The side vent substrate of claim 1, wherein the vent channel is between a lower surface of the second insulating layer and an upper surface of the first insulating layer.
3. The exhaust side substrate according to claim 1, wherein a hermetic shield is provided on the second insulating layer, the intake hole of the exhaust channel being covered in the shield.
4. The side vent substrate of claim 1, wherein the vent channel further comprises a second vent hole that extends through the second insulating layer and is not covered by the mask.
5. The side vent substrate according to claim 1, wherein a first wiring layer is provided in a lower surface of the first insulating layer, a first copper pillar layer is provided on the first wiring layer, a second wiring layer is provided in a lower surface of the second insulating layer, a second copper pillar layer is provided on the second wiring layer, a third wiring layer is provided on the second insulating layer, the first wiring layer and the second wiring layer are conductively connected by the first copper pillar layer, and the second wiring layer and the third wiring layer are conductively connected by the second copper pillar layer.
6. A method for manufacturing a side exhaust substrate comprises the following steps:
(a) preparing a temporary bearing plate;
(b) forming a first circuit layer on at least one side of the temporary bearing plate;
(c) forming a first copper column layer on the first circuit layer, laminating a first insulating layer on the first copper column layer, and thinning the first insulating layer to expose the first copper column layer;
(d) forming a second circuit layer on the first insulating layer, so that the first circuit layer and the second circuit layer are in conductive connection through the first copper column layer, and the second circuit layer comprises a sacrificial circuit;
(e) forming a second copper column layer on the second circuit layer, wherein the second copper column layer comprises a sacrificial copper column, the sacrificial copper column is formed on the sacrificial circuit, a second insulating layer is laminated on the second copper column layer, and the second insulating layer is thinned to expose the second copper column layer;
(f) forming a third circuit layer on the second insulating layer, so that the second circuit layer and the third circuit layer are in conductive connection through the second copper column layer;
(g) removing the temporary bearing plate;
(h) and etching the sacrificial copper column and the sacrificial line to form an exhaust channel.
7. The manufacturing method according to claim 6, further comprising:
(i) and h, mounting a component on the surface of the third circuit layer, routing, and applying a packaging cover to cover the component and the air inlet hole of the exhaust channel, so that the exhaust hole of the exhaust channel is positioned outside the packaging cover.
8. The manufacturing method according to claim 6, wherein the temporary carrier board comprises a copper-clad board with at least one side covered with a double-layer copper foil, wherein the copper-clad board comprises a core layer, a first copper layer on the surface of the core layer, and a second copper layer on the first copper layer, wherein the first copper layer and the second copper layer are adhered together by physical pressing.
9. The manufacturing method according to claim 6, wherein the step (b) includes:
(b1) forming a first metal seed layer on at least one side of the temporary bearing plate;
(b2) applying a first photoresist layer on the first metal seed layer, and exposing and developing to form a first characteristic pattern;
(b3) electroplating to form a first circuit layer in the first characteristic pattern;
(b4) removing the first photoresist layer.
10. The manufacturing method according to claim 6, wherein the step (c) comprises:
(c1) applying a second photoresist layer on the first circuit layer, and exposing and developing to form a second characteristic pattern;
(c2) electroplating to form a first copper column layer in the second characteristic pattern;
(c3) removing the second photoresist layer;
(c4) applying a first insulating layer on the first copper pillar layer and thinning the first insulating layer to expose the first copper pillar layer.
11. The manufacturing method according to claim 6, wherein the step (d) includes:
(d1) forming a second metal seed layer on the first insulating layer;
(d2) applying a third photoresist layer on the second metal seed layer, and exposing and developing to form a third characteristic pattern;
(d3) electroplating to form a second circuit layer in the third feature pattern, wherein the second circuit layer comprises a conducting circuit and a sacrificial circuit, so that the first circuit layer and the conducting circuit are in conducting connection through the first copper column layer;
(d4) removing the third photoresist layer.
12. The method of manufacturing of claim 11, wherein step (e) comprises:
(e1) applying a fourth photoresist layer on the second circuit layer, and exposing and developing to form a fourth characteristic pattern;
(e2) electroplating to form a second copper column layer in the fourth feature pattern, wherein the second copper column layer comprises a sacrificial copper column and a conductive copper column, so that the sacrificial copper column is connected with the sacrificial line, and the conductive copper column is connected with the conductive line;
(e3) removing the fourth photoresist layer, and etching the second metal seed layer;
(e4) and forming a second insulating layer on the second copper column layer, and thinning the second insulating layer to expose the second copper column layer.
13. The manufacturing method according to claim 6, wherein the step (f) includes:
(f1) forming a third metal seed layer on the second insulating layer;
(f2) applying a fifth photoresist layer on the third metal seed layer, and exposing and developing to form a fifth characteristic pattern;
(f3) electroplating to form a third circuit layer in the fifth characteristic pattern;
(f4) and removing the fifth photoresist layer and etching the third metal seed layer.
14. The method of manufacturing of claim 9, 11 or 13, wherein the metal seed layer comprises titanium, copper, titanium tungsten alloy or a combination thereof.
15. The manufacturing method according to claim 8, wherein step (g) comprises removing the temporary carrier plate by physically separating the first and second copper layers and etching the second copper layer.
16. The manufacturing method according to claim 6, further comprising forming an etch barrier layer on at least one side of the temporary carrier plate before step (b).
17. The method of manufacturing of claim 16, wherein the etch stop layer comprises nickel, titanium, or a combination thereof.
CN202110926634.XA 2021-08-12 2021-08-12 Side exhaust substrate and manufacturing method thereof Pending CN113838808A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110926634.XA CN113838808A (en) 2021-08-12 2021-08-12 Side exhaust substrate and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110926634.XA CN113838808A (en) 2021-08-12 2021-08-12 Side exhaust substrate and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN113838808A true CN113838808A (en) 2021-12-24

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110926634.XA Pending CN113838808A (en) 2021-08-12 2021-08-12 Side exhaust substrate and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN113838808A (en)

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