CN113824659B - Signal processing circuit and method in digital domain - Google Patents
Signal processing circuit and method in digital domain Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
- H04L2025/03439—Fixed structures
- H04L2025/03522—Frequency domain
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L2025/03592—Adaptation methods
- H04L2025/03598—Algorithms
- H04L2025/03611—Iterative algorithms
- H04L2025/03636—Algorithms using least mean square [LMS]
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Abstract
The present disclosure relates to signal processing circuits and methods in the digital domain. A signal processing method in digital domain includes: adding a random number sequence signal to a time domain input signal to generate a time domain processed input signal; performing Fourier transform on the time-domain processed input signal to generate a frequency-domain processed input signal; calculating the frequency domain processed input signal according to equalizer parameters to generate a frequency domain output signal; performing an inverse Fourier transform on the frequency domain output signal to generate a time domain output signal; generating a decision output signal and a time domain error signal according to the time domain output signal; and generating a specific parameter signal according to the time domain error signal and the frequency domain processed input signal to determine the equalizer parameters of the equalizer.
Description
Technical Field
The present invention relates to a digital signal processing architecture, and more particularly, to a digital domain signal processing circuit and method.
Background
Generally, in a system for high-speed data transmission (e.g., an ethernet 2.5G/5G/10G system), a Frequency domain block-wise least mean square (FBLMS) system architecture is generally adopted, and in a practical system, fixed point (fixed point) finite word length (finite word length) operation is used. However, in a practical system employing a frequency domain block-type least mean square algorithm of fixed point number operation, quantization noise is introduced into the operation of a fourier transform circuit, and if the number of bits employed by the fourier transform circuit is small, the output is very prone to noise. Since the fourier transform circuit is the most occupied circuit area and energy consuming part of a system, it is practically impossible to suppress the effect of quantization noise by increasing the number of bits used. When the number of bits in the fourier transform circuit is small for saving circuit area or for saving energy, if the word length is insufficient, a specific noise pattern (colored noise pattern) is generated between the operation of the fourier transform circuit and the operation of the inverse fourier transform circuit, which affects the operation of the decision feedback equalizer and thus the feedback control of the equalizer, and in the worst case, the equalizer coefficient is shifted and the whole system is unstable and cannot converge.
Disclosure of Invention
It is therefore one of the objectives of the present invention to provide a signal processing circuit in the digital domain, which solves the problems of the conventional architecture.
According to an embodiment of the invention, a signal processing circuit in the digital domain is disclosed. The signal processing circuit includes a processing unit, a first Fourier transform circuit, an equalizer, a first inverse Fourier transform circuit, a decision circuit and a feedback circuit. The processing unit is used for receiving a time domain input signal and adding a random number sequence signal to the time domain input signal to generate a time domain processed input signal. The first Fourier transform circuit is coupled to the processing unit and is used for receiving the time domain processed input signal and performing a first Fourier transform on the time domain processed input signal to generate a frequency domain processed input signal. The equalizer is used for receiving the frequency domain processed input signal, and calculating the frequency domain processed input signal according to an equalizer parameter to generate a frequency domain output signal. The first inverse Fourier transform circuit is coupled to the equalizer and is used for receiving the frequency domain output signal and performing a first inverse Fourier transform on the frequency domain output signal to generate a time domain output signal. The decision circuit is coupled to the first inverse Fourier transform circuit and is used for generating a decision output signal according to the time domain output signal and generating a time domain error signal according to the decision output signal and the time domain output signal. The feedback circuit is coupled to the decision circuit and the equalizer, and is used for generating a specific parameter signal according to the time domain error signal and the frequency domain processed input signal to determine the equalizer parameter of the equalizer.
According to the embodiment of the invention, only a signal processing circuit in the digital domain is disclosed. The signal processing circuit comprises a random number sequence generating circuit, a first adding unit, a first Fourier transforming circuit, a first equalizer, a first inverse Fourier transforming circuit, a second adding unit, a second Fourier transforming circuit, a second equalizer, a second inverse Fourier transforming circuit and a decision circuit. The random number sequence generating circuit is used for generating a first near-end random number sequence signal and a first far-end random number sequence signal, wherein the first near-end random number sequence signal corresponds to a first transmission wire, the first far-end random number sequence signal corresponds to a first receiving wire, and the first transmission wire and the first receiving wire are a pair of transmission/receiving wires. The first adding unit is used for receiving a digital domain transmission signal corresponding to the first near-end random number sequence signal and the first transmission wire, adding the first near-end random number sequence signal and the digital domain transmission signal corresponding to the first transmission wire, and generating a first time domain processed transmission signal. The first Fourier transform circuit is coupled to the first adder and is used for converting the first time domain processed transmission signal into a first frequency domain processed transmission signal. The first equalizer is coupled to the first Fourier transform circuit and is used for performing a first equalization compensation on the first frequency domain processed transmission signal to generate a first equalized transmission signal. The first inverse Fourier transform circuit is coupled to the first equalizer and is used for generating a time domain equalized transmission result signal according to the first equalized transmission signal. The second adding unit is coupled to a digital domain receiving signal corresponding to the first receiving wire outputted by an analog-digital converter and coupled to the first inverse Fourier transform circuit, and is used for adding the time domain equalized transmission result signal and the first far-end random number sequence signal to the digital domain receiving signal so as to generate a first time domain processed receiving signal. The second Fourier transform circuit is coupled to the second adder and is used for converting the first time domain processed received signal into a first frequency domain processed received signal. The second equalizer is coupled to the second fourier transform circuit and is used for performing a second equalization compensation on the first frequency domain processed received signal to generate a first equalized received signal. The second inverse Fourier transform circuit is coupled to the second equalizer and is used for generating a time domain output signal according to the first equalized received signal. The decision circuit is coupled to the second inverse Fourier transform circuit and is used for generating a decision output signal according to the time domain output signal and generating a time domain error signal according to the decision output signal and the time domain output signal so as to feedback and determine an equalizer parameter of the second equalizer.
According to another embodiment of the present invention, a method for signal processing in the digital domain is disclosed. The method comprises the following steps: receiving a time domain input signal, adding a random sequence signal to the time domain input signal to generate a time domain processed input signal; receiving the time domain processed input signal, and performing a first fourier transform on the time domain processed input signal to generate a frequency domain processed input signal; receiving the frequency domain processed input signal, and operating the frequency domain processed input signal according to an equalizer parameter to generate a frequency domain output signal; receiving the frequency domain output signal to perform a first inverse Fourier transform on the frequency domain output signal to generate a time domain output signal; generating a decision output signal according to the time domain output signal, and generating a time domain error signal according to the decision output signal and the time domain output signal; and generating a specific parameter signal according to the time domain error signal and a conjugate signal of the frequency domain processed input signal to determine the equalizer parameter of the equalizer.
Drawings
FIG. 1 is a schematic block diagram of a signal processing circuit in the digital domain according to one embodiment of the present invention.
FIG. 2 is a schematic circuit diagram of the signal processing circuit shown in FIG. 1.
Fig. 3 is a schematic diagram of a virtual noise sequence generation circuit.
FIG. 4 is a schematic diagram of a signal processing circuit shown in FIG. 1.
FIG. 5 is a schematic diagram of a signal processing circuit shown in FIG. 1.
FIG. 6 is a schematic block diagram of a portion of a data transmission device architecture for applying the operation of the processing unit shown in FIG. 1 to the portion of the data transmission device architecture in accordance with an embodiment of the present invention.
Detailed Description
In a high-speed data transmission system, such as an Ethernet (2.5G/5G/10G) system, a frequency domain block least mean square (FBLMS) system architecture is adopted to avoid excessively long channel response (channel response). The system is stabilized by adding an artificially generated noise to the original digital input signal prior to the input of the Fourier transform circuit, such as by using a random number sequence (spectrally white noise, but not limited to) of data signals, such that the spectral power/energy of the data signals of the random number sequence is higher than the spectral power/energy of the measured specific noise pattern, to mask the energy of the specific noise pattern, and to prevent the occurrence of the condition of accumulating the energy of the specific noise pattern at a specific frequency in the output of the Fourier transform circuit. In addition, the masking (mask) of the bit data (e.g., one or more least significant bits (Least Significant Bit, LSB)) of the original digital input signal may be used in practice to equivalently achieve the effect of adding artificially generated noise to the original digital input signal. In addition, the present invention can also be applied to a high-speed transmission communication system having a plurality of channels, such as the aforementioned Ethernet (Ethernet) 2.5G/5G/10G system (but not limited thereto).
Referring to fig. 1, fig. 1 is a schematic block diagram of a signal processing circuit 100 in the digital domain according to an embodiment of the invention, where the signal processing circuit 100 is, for example, a digital signal processor (Digital Signal Processor, DSP) of a receiver, and as shown in fig. 1, the signal processing circuit 100 includes a processing unit 105, a fourier transform circuit 110, an equalizer 115, an inverse fourier transform circuit 120, a decision circuit 125, and a feedback circuit 130. The processing unit 105 is configured to receive a time domain input signal Xn (a digital signal) and add a random number sequence signal to the time domain input signal Xn to generate a time domain processed input signal Xn'. The fourier transform circuit 110 is coupled to the processing unit 105 and is configured to receive the processed input signal Xn ', and perform a fourier transform (e.g., a fast fourier transform operation) on the processed input signal Xn' to convert the processed signal to a frequency domain, so as to generate a processed input signal Xnf. The equalizer 115 is coupled to the fourier transform circuit 110 and is configured to receive the frequency domain processed input signal Xnf, and perform an equalizing operation on the frequency domain processed input signal Xnf according to the equalizer parameter Weq to generate a frequency domain output signal Ynf. Equalizer 115 is implemented, for example, by a finite impulse response (Finite Impulse Response, FIR) equalizer and has a specific number of bits. The inverse fourier transform circuit 120 is coupled to the equalizer 115 and receives the frequency domain output signal Ynf to perform an inverse fourier transform (e.g., an inverse fast fourier transform operation) on the frequency domain output signal Ynf to transform the frequency domain signal into a time domain, thereby generating a time domain output signal Yn. The decision circuit 125 is coupled to the inverse fourier transform circuit 120 for generating a decision output signal Do according to the time domain output signal Yn, and generating a time domain error signal En according to the decision output signal Do and the time domain output signal Yn. In practice, a decision device (sler) is used to generate the decision output signal Do, and then the time domain output signal Yn is subtracted from the decision output signal Do to obtain the time domain error signal En. The feedback circuit 130 is coupled to the decision circuit 125 and the equalizer 115, and is configured to generate a specific parameter signal Wnf according to the time domain error signal En and a conjugate signal of the frequency domain processed input signal Xnf to determine the equalizer parameter Weq of the equalizer 115. The feedback circuit 130 receives the frequency domain processed input signal Xnf outputted from the fourier transform circuit 110, performs a conjugate operation on the frequency domain processed input signal Xnf to obtain the conjugate signal, and generates the specific parameter signal Wnf according to the conjugate signal and the time domain error signal En to feedback and control the equalizer parameter Weq of the equalizer 115.
It should be noted that the intensity value (magnitide) of a power spectral density (Power Spectral Density, PSD) of the above-mentioned random number sequence signal added by the processing unit 105 is determined by referring to the specific noise energy contained in the frequency domain processed input signal Xnf outputted by the Fourier transform circuit 110. If the finite word length using the fixed point number is insufficient, the specific noise pattern is accumulated in the circuit element of the feedback circuit 130 in time in fig. 1, which affects the feedback control of the equalizer 115, and further causes the equalizer coefficient to drift, making the whole system unstable and unable to converge. Therefore, to solve this problem, the processing unit 105 is provided before the input of the fourier transform circuit 110, and the time domain input signal Xn is processed to mask or reduce the specific noise in the output signal of the fourier transform circuit 110 (i.e., the frequency domain processed input signal Xnf). In practice, the specific noise is indicative of noise present at least one specific channel frequency, and the strength value of the power spectral density of the added random number sequence signal is greater than the strength value of the power spectral density of noise at the at least one specific channel frequency. That is, a white noise (Xn) is added to the input signal equivalently, and the power spectral density of the white noise is particularly uniform in intensity value at all frequencies so that the effect of noise at least at a specific channel frequency can be covered or homogenized, thus stabilizing the whole system without occurrence of non-convergence. In addition, it should be noted that the spectral power of the noise at the at least one specific channel frequency is not different from channel to channel, but is determined by the number of bits used by a fourier transform circuit. Therefore, when the fourier transform circuit is determined, the circuit designer can measure the spectral power of the noise at the at least one specific channel frequency outputted by the fourier transform circuit to determine the spectral power intensity of the random number sequence signal to be applied by the processing unit 105, and no further measurement is required after shipment.
Referring to fig. 2 and 3, fig. 2 is a circuit diagram of the signal processing circuit 100 shown in fig. 1, and fig. 3 is a broken lineA schematic diagram of a Pseudo-Noise sequence (Pseudo-Noise sequences) generation circuit 1051. In practice, as shown in fig. 2, the feedback circuit 130 includes, for example, a fourier transform circuit 1305, a conjugate operation unit 1310, a multiplication unit 1315, an inverse fourier transform circuit 1320, a coefficient generation unit 1325 and a fourier transform circuit 1330. The fourier transform circuit 1305 is coupled to the decision circuit 125 and is configured to receive the time domain error signal En, perform a fourier transform (e.g., a fast fourier transform operation) on the time domain error signal En to transform the time domain signal into a frequency domain signal, so as to generate a frequency domain error signal Enf. The conjugate operation unit 1310 is coupled to the Fourier transform circuit 110 and is used for performing a conjugate operation on the frequency domain processed input signal Xnf to generate a conjugate signalThe multiplication unit 1315 is coupled to the conjugate unit 1310 and the Fourier transform circuit 1305 for adding the conjugate signal +.>Multiplied by the frequency domain error signal Enf to produce a gradient signal Gf. The inverse Fourier transform circuit 1320 is coupled to the multiplication unit 1315 for performing an inverse Fourier transform (e.g., an inverse fast Fourier transform operation) on the gradient signal Gf to convert the frequency domain signal into a time domain signal to generate a time domain gradient signal Gn. The coefficient generation unit 1325 is coupled to the inverse fourier transform circuit 1320, and is configured to generate and accumulate parameters according to the time domain gradient signal Gn and a specific step μ to generate an accumulated parameter signal Wn; for example, the amplifying unit 1326 of the coefficient generating unit 1325 multiplies the time domain gradient signal Gn by a specific step μ to generate an amplified time domain gradient signal, and then the adding unit 1327 adds the amplified time domain gradient signal generated at the current time point and the previous time point to generate the added parameter signal Wn. The Fourier transform circuit 1330 is coupled to the coefficient generation unit 1325 for receiving the accumulated parameter signal Wn and accumulating The parameter signal Wn performs a fourier transform (e.g., a fast fourier transform operation) to convert the time domain signal into the frequency domain to generate the specific parameter signal Wnf that is used to determine the equalizer parameter Weq of the equalizer 115.
In addition, the processing unit 105 includes, for example, a virtual noise sequence generating circuit 1051 and an adding unit 1052. The virtual noise sequence generating circuit 1051 is configured to generate a virtual noise sequence signal SPNS as the random number sequence signal, and the adding unit 1052 is coupled to the virtual noise sequence generating circuit 1051 and is configured to receive the time domain input signal Xn and the virtual noise sequence signal SPNS generated by the virtual noise sequence generating circuit 1051, and add the virtual noise sequence signal SPNS to the time domain input signal Xn to generate the time domain processed input signal Xn'. As shown in fig. 3, the virtual noise sequence generating circuit 1051 includes a virtual noise sequence generator 1055, a delay unit 1053 and a subtracting unit 1054. The virtual noise sequence generator 1055 is configured to generate a preliminary virtual noise sequence signal, and the delay unit 1053 is coupled to the virtual noise sequence generator 1055 and is configured to perform a specific delay (e.g., z shown in fig. 3) on the preliminary virtual noise sequence signal -1 Which means a delay of one unit time; however, this is not a limitation), a delayed pseudo noise sequence signal is generated, and subtracting unit 1054 is configured to receive the preliminary pseudo noise sequence signal and the delayed pseudo noise sequence signal, and subtract the delayed pseudo noise sequence signal from the preliminary pseudo noise sequence signal to generate the pseudo noise sequence signal SPNS (i.e., the random number sequence signal).
It should be noted that, in the embodiment of fig. 2, the intensity value of the power spectral density of the random number sequence signal added by the processing unit 105 is also referenced to the signal spectral power of the second specific noise energy contained in the frequency domain error signal Enf output by the fourier transform circuit 1305 in addition to the first specific noise energy contained in the frequency domain processed input signal Xnf output by the fourier transform circuit 110, and to the signal spectral power of the third specific noise energy contained in the specific parameter signal Wnf output by the fourier transform circuit 1330. For example, the signal spectrum power of the random number sequence signal is greater than or higher than the signal spectrum power of the first specific noise energy contained in the frequency domain processed input signal Xnf outputted by the fourier transform circuit 110, the signal spectrum power of the second specific noise energy contained in the frequency domain error signal Enf outputted by the fourier transform circuit 1305, and the signal spectrum power of the third specific noise energy contained in the specific parameter signal Wnf outputted by the fourier transform circuit 1330, so that the influence of noise on at least a certain specific channel frequency on the operation of all fourier transform circuits is covered or homogenized, and thus the whole system can be stabilized without non-convergence. Furthermore, the generated preliminary pseudo noise sequence signal shown in fig. 3 is the preliminary random number sequence signal, by delaying the preliminary random number sequence signal by a unit time, the preliminary random number sequence signal generated by the pseudo noise sequence generator 1055 is subtracted by the preliminary random number sequence signal delayed by a unit time, so as to equivalently generate a random number sequence signal with a second order random number as the output of the pseudo noise sequence generating circuit 1051, so that the random number sequence signal can be practically uncorrelated with the input signal Xn, and the system can achieve the stabilization of the second order random number; however, this is not a limitation of the present disclosure. In other embodiments, the preliminary random number sequence signal generated by the virtual noise sequence generator 1055 can also be directly used as the output of the virtual noise sequence generator 1051, so that the system can be practically uncorrelated with the input signal Xn, and the system achieves the first order random number stabilization. In addition, based on the same principle of operation, in other different embodiments, the n-order random number of the system can be stabilized by performing multiple different delays and subtraction on the generated random number sequence signal, where n is greater than or equal to 3.
Referring to fig. 4, fig. 4 is a schematic diagram of a different embodiment of the signal processing circuit 100 shown in fig. 1. As shown in fig. 4, the processing unit 105 is disposed between an adc 101 and the fourier transform circuit 110, and is used for processing a digital signal (i.e. the time domain input signal Xn) generated by the adc 101 converting an analog signal, the processing unit 105 includes, for example, a masking unit 1056, wherein the masking unit 1056 is used for masking the least significant bit of a signal bit resolution of the time domain input signal Xn, so that the information of the number of bits of the signal bit resolution of the masked input signal Xn' is lower than the information of the number of bits of a signal bit resolution of the time domain input signal Xn, to equivalently achieve the effect of adding a random number sequence signal to the time domain input signal Xn. For example, the resolution of the time domain input signal Xn corresponds to M bits, M being equal to 8 (but not limited to), and the processing unit 305 removes the less significant N Least Significant Bits (LSBs) (N being equal to 2 (but not limited to) of the resolution of the time domain input signal Xn and leaves the other bits (i.e., 6 bits of information) equivalent to adding a random number sequence signal (i.e., noise signal) to the time domain input signal Xn to generate the time domain processed input signal Xn'. In addition, the value of N is determined by referring to the first specific noise energy contained in the processed input signal Xnf of the frequency domain outputted by the fourier transform circuit 110, so as to homogenize the noise energy in the processed input signal Xnf of the frequency domain, so as to cover the first specific noise energy and stabilize the system. Alternatively, in one embodiment, the value of N is determined by referring to the first specific noise energy contained in the processed input signal Xnf in the frequency domain outputted by the fourier transform circuit 110, and also referring to the signal spectral power of the second specific noise energy contained in the error signal Enf in the frequency domain outputted by the fourier transform circuit 1305 and the signal spectral power of the third specific noise energy contained in the specific parameter signal Wnf outputted by the fourier transform circuit 1330, so as to homogenize the noise energy in the processed input signal Xnf in the frequency domain, the error signal Enf in the frequency domain and the specific parameter signal Wnf to mask the noise energy, thereby stabilizing the system.
Referring to fig. 5, fig. 5 is a schematic diagram of a different embodiment of the signal processing circuit 100 shown in fig. 1. As shown in fig. 5, the processing unit 105 is disposed between the adc 101 and the fourier transform circuit 110, and is used for processing a digital signal (i.e. the time domain input signal Xn) generated by the adc 101 converting an analog signal. The processing unit 105 includes, for example, a filter 1057, wherein the filter 1057 is configured to adjust the spectral power of the output random number sequence signal to generate an adjusted random number sequence signal, and output the adjusted random number sequence signal. Wherein the signal spectrum of the adjusted random number sequence signal increases with increasing signal frequency or an increase in the signal spectrum power of the random number sequence signal increases with increasing operating temperature of the signal processing circuit. For example, as shown in fig. 5, the higher the channel frequency is, the higher the power corresponding to the adjusted random number sequence signal is, so that the energy of the specific noise output from the fourier transform circuit or circuits can be covered uniformly at the higher frequency. For example, for a data transmission device applied to a high-speed wired network, for example, the signal processing circuit 100 described above may be disposed in a data transmission device connected to a link partner device (link partner device) through an ethernet 802.3 series standard, where the data transmission device has a training mode (data mode) and a data transmission mode (data mode), although the data transmission device may inform the link partner device of the obtained parameters for feedback control after the training mode performs data transmission training, so that the link partner device may communicate with the data transmission device based on the parameters for feedback control when switching to the data transmission mode, however, during high-speed data transmission in the data transmission mode, the operating temperature or the system environment temperature may increase, and the equalizer parameters of the channel may change greatly due to high-temperature severe insertion loss (insertion loss), such that the system may not converge. Therefore, in order to solve the problem that the high-temperature system cannot converge, the signal processing circuit 100 adjusts the random number sequence signal with uniform spectrum power at each channel frequency, so that the spectrum power of the adjusted random number sequence signal can be increased along with the increase of the frequency, thereby covering the noise energy caused by the high temperature during the high-frequency operation and avoiding the unstable system due to the accumulation effect of the noise energy at the specific channel frequency. That is, in order to avoid the effect of accumulating the noise energy on a specific high-frequency channel frequency, the adjusted random number sequence signal has a signal spectrum with a power larger than a power of the noise energy on the specific high-frequency channel frequency, and the adjusted random number sequence signal has a signal spectrum with a power variation between adjacent channel frequencies smaller than a power variation between the noise energy on the specific channel frequency and an adjacent channel frequency, so that the noise energy is relatively not excessively accumulated on the specific channel frequency, and the whole system can be stably converged. Furthermore, in one embodiment, the shape of the distribution of the power spectrum of the random number sequence signal to be added may also be determined according to the temperature difference to be supported, for example, if the temperature difference to be supported is larger (i.e. the difference of the high frequency power representing the current insertion loss is larger), the shape of the distribution of the power spectrum needs to be raised more at higher frequencies.
Referring to fig. 6, fig. 6 is a schematic circuit block diagram of a portion of an architecture for applying the operation of the processing unit shown in fig. 1 to a data transmission device 600 according to an embodiment of the present invention. As shown in fig. 6, the data transmission apparatus 600 includes an analog-to-digital converter 601, adding units 602A, 602B, 602C, 602D, 609A, 609B, 609C, 609D, 605, 610, fourier transform circuits 603FA, 603FB, 603FC, 603FD, 603NA, 603NB, 603NC, 603ND, equalizers 604FA, 604FB, 604FC, 604FD, 604NA, 604NB, 604NC, 604ND, inverse fourier transform circuits 606, 611, decision circuit 607, digital-to-analog converter 608, and random number sequence generating circuit 612. The data transmission device 600 for high-speed transmission of a wired network is connected to a link partner device through the ethernet 802.3 series standard, and the data transmission device 600 is a transceiver device and has a receiver (receiver) architecture and a transmitter (transmitter) architecture, and has a 4-pair twisted pair transmission mechanism structure (e.g., 2-pair wire reception, 2-pair wire transmission). Wherein the analog-to-digital converter 601, the adding unit 602, the fourier transform circuits 603FA, 603FB, 603FC, 603FD, the equalizer 604FA, 604FB, 604FC, 604FD, the adding unit 605, the inverse fourier transform circuit 606 and the decision circuit 607 are located on the receiving path of the receiver, and the digital-to-analog converter 608 is located on the transmitting path of the transmitter.
The signal tx_ch_a refers to a digital domain transmission signal corresponding to a first transmission line, which is converted by the dac 608 to generate an analog transmission signal, and the analog transmission signal is transmitted to a corresponding link partner device by an analog transmission circuit (not shown in fig. 6) of the data transmission device 600 through the first transmission line. The signal N_Ch_B, the signal N_Ch_C and the signal N_Ch_D refer to the transmission signals of different digital domains corresponding to the second, third and fourth transmission wires, respectively. The adding unit 609A adds the transmission signal tx_ch_a corresponding to the first transmission line and a first near-end random number sequence signal n_pn_a corresponding to the first transmission line to generate a first time domain processed transmission signal to the fourier transform circuit 603NA. The fourier transform circuit 603NA is coupled to the adding unit 609A and is configured to convert the first time domain processed transmit signal from the time domain to the frequency domain to generate a first frequency domain processed transmit signal to the equalizer 604NA. The equalizer 604NA is coupled to the fourier transform circuit 603NA, and is configured to perform equalization (e.g., near-end echo (echo) compensation) on the first frequency domain processed transmit signal according to the equalizer parameters to generate a first equalized transmit signal to the adding unit 610. Similarly, the adding unit 609B adds the transmission signal n_ch_b corresponding to the second transmission line and a second near-end random number sequence signal n_pn_b corresponding to the second transmission line to generate a second time domain processed transmission signal to the fourier transform circuit 603NB. The fourier transform circuit 603NB is coupled to the adding unit 609B and configured to convert the second time domain processed transmit signal from the time domain to the frequency domain to generate a second frequency domain processed transmit signal to the equalizer 604NB. The equalizer 604NB is coupled to the fourier transform circuit 603NB and is configured to perform equalization compensation (e.g., near-End cross talk (NEXT) compensation cancellation) on the second frequency domain processed transmit signal according to equalizer parameters to generate a second equalized transmit signal to the adding unit 610. Similarly, the operation principle of the adding units 609C and 609D is similar to that described above, and thus will not be described here again. Then, the adding unit 610 adds the first, second, third and fourth equalized transmission signals to generate an equalized transmission result signal to the inverse fourier transform circuit 611, and the inverse fourier transform circuit 611 is coupled to the adding unit 610 and is configured to convert the equalized transmission result signal from the frequency domain to the time domain to generate a time domain equalized transmission result signal to the adding unit 602A.
For the receiver path, the analog-to-digital converter 601 is configured to receive an analog received signal (an analog input signal) corresponding to a first receiving wire, and to convert the analog received signal from the analog domain to the digital domain to generate an input signal rx_ch_a (corresponding to the first receiving wire) in the digital domain. The signals F_Ch_B, F_Ch_C and F_Ch_D refer to the received signals of different digital domains corresponding to the second, third and fourth receiving wires, respectively; the received signals are received from the remote link partner device via a wire.
The adding unit 602A is coupled to the adc 601 and is configured to add the input signal rx_ch_a, an equalized transmission result signal corresponding to the transmission lines, and a first remote random number sequence signal f_pn_a to generate a first time domain processed received signal to the fourier transform circuit 603FA. The fourier transform circuit 603FA is coupled to the adding unit 602A and is configured to convert the first time domain processed received signal from the time domain to the frequency domain to generate a first frequency domain processed received signal to the equalizer 604FA. The equalizer 604FA is coupled to the fourier transform circuit 603FA, and is configured to perform equalization compensation on the first frequency domain processed received signal according to equalizer parameters to compensate for the channel response, thereby reducing the error rate of the communication system transmission, and generating a first equalized received signal to the adding unit 605. Similarly, the adding unit 602B is coupled to another adc (not shown in fig. 6) of the data transmission device 600 and is configured to add an input signal f_ch_a corresponding to the second receiving line and a second remote random number sequence signal f_pn_b to generate a second time domain processed receiving signal to the fourier transform circuit 603FB. The fourier transform circuit 603FB is coupled to the adding unit 602B and is configured to convert the second time domain processed received signal from the time domain to the frequency domain to generate a second frequency domain processed received signal to the equalizer 604FB. The equalizer 604FB is coupled to the fourier transform circuit 603FB, and is configured to perform equalization compensation on the second frequency domain processed received signal according to equalizer parameters to compensate for the channel response, thereby reducing the error rate of the communication system transmission to generate a second equalized received signal to the adding unit 605. Similarly, the operation principle of the adding units 602C and 602D is similar to that described above, and thus will not be repeated here. The adding unit 605 then adds the first, second, third and fourth equalized received signals to generate an equalized received signal to the inverse fourier transform circuit 606, the inverse fourier transform circuit 606 is coupled to the adding unit 605 and is configured to convert the equalized received signal in the frequency domain from the frequency domain to the time domain to generate a time domain output signal to the decision circuit 607, the decision circuit is coupled to the inverse fourier transform circuit 606 and is configured to generate a decision output signal Do according to the time domain output signal y_a (the received signal corresponding to the first receiving wire) and generate a time domain error signal En according to the decision output signal Do and the time domain output signal y_a, for example, a decision device is used to generate the decision output signal Do, then the time domain output signal y_a is subtracted from the decision output signal Do to obtain the time domain error signal En, and then the time domain error signal En is fed to a circuit (not shown in fig. 6) of the data transmission device 600 to control the feedback equalizer corresponding to the first receiving wire to generate a decision output signal y_a feedback equalizer (not shown in fig. 6) and is fed to the second equalizer 604 and the second equalizer (or the fourth equalizer is also shown in fig. 6) to the data transmission device 604, and the other equalizer is fed to the fourth equalizer 600, the equalizer is also shown in the data equalizer is fed to the fourth equalizer is shown in fig. 6.
It should be noted that the first near-end random number sequence signal n_pn_a, the second near-end random number sequence signal n_pn_b, the third near-end random number sequence signal n_pn_c, the fourth near-end random number sequence signal n_pn_d, the first far-end random number sequence signal f_pn_a, the second far-end random number sequence signal f_pn_b, the third far-end random number sequence signal f_pn_c, and the fourth far-end random number sequence signal f_pn_d are generated by the random number sequence generating circuit 612, respectively, and the data changes of the random number sequence signals are not related to each other. In practice, the random number sequence generating circuit 612 may first generate a preliminary random number sequence signal, then apply eight different unit delays to the preliminary random number sequence signal to generate eight different delayed random number sequence signals, and then subtract the eight different delayed random number sequence signals from the preliminary random number sequence signal to obtain the finally output random number sequence signals that are not related to each other. However, the present invention is not limited thereto, and in other embodiments, different methods may be used to generate a plurality of random number sequence signals that are not related to each other.
Furthermore, the embodiment shown in fig. 6 applies the first near-end random number sequence signal n_pn_a, the second near-end random number sequence signal n_pn_b, the third near-end random number sequence signal n_pn_c, and the fourth near-end random number sequence signal n_pn_d to the transmission output signals corresponding to different transmission wires to generate the processed transmission signals, and then transmits the processed transmission signals to the fourier transform circuits 603NA, 603NB, 603NC, and 603ND, so that the situation that the number of bits divided by the fourier transform circuits 603NA, 603NB, 603NC, and 603ND is insufficient to cause the system to be unable to converge can be avoided, and in addition, the situation that the number of bits divided by the fourier transform circuits 603NA, 603NB, 603NC, and 603ND is insufficient to cause the system to be converged by applying the first far-end random number sequence signal f_pn_a, the second far-end random number sequence signal f_pn_b, the third far-end random number sequence signal f_pn_c, and the fourth far-end random number sequence signal f_pn_d to the reception signals corresponding to different reception wires to generate the processed reception signals corresponding to the reception signals. Therefore, the signal spectrum power distribution of the random number sequence signals is used for respectively homogenizing the specific noise energy generated by accumulation due to insufficient bit number of the corresponding Fourier transform circuits, so that the noise energy in the output signals of the corresponding Fourier transform circuits is relatively distributed in different channel frequencies, and the phenomenon that the system cannot converge due to accumulation in a certain channel frequency is avoided. The signal spectrum power distribution of the random number sequence signals is determined by referring to the corresponding Fourier transform circuit because of the number of bits and/or the power spectrum distribution of the specific noise energy in the output signal of the corresponding Fourier transform circuit. In the above embodiment, when operating in the training mode, the present scheme stabilizes the system operation without divergence by generating a plurality of artificial noise, and once the data transmission mode is entered, i.e. after the feedback control equalizer coefficient is transmitted to a link-partner device, the random number sequence generation circuit 612 shown in fig. 6 can shut down the artificial noise (i.e. the random number sequence signals) without adding the artificial noise to the corresponding digital signals, so that the system performance is improved.
In addition, it should be noted that the concepts of the system architecture of FIG. 6 may also be applied to one or more pairs of transmit/receive wires. For example, if a system uses only one pair of transmit/receive wires for data transmission, the random number sequence generation circuit 612 only needs to generate the random number sequence signals f_pn_a and n_pn_a, and does not need to generate other random number sequence signals, and other circuit elements can be omitted according to the design change type. Similarly, if applied to two pairs of transmit/receive wires, the random number sequence generating circuit 612 only needs to generate the random number sequence signals F_PN_A, N_PN_A, F_PN_B and N_PN_B, but does not need to generate other random number sequence signals, and other circuit elements can be omitted according to the design change type.
In summary, the invention can prevent unstable system coefficient drift caused by insufficient word length by adding artificial noise (i.e. the above-mentioned random number sequence signal) to the digital domain received signal, thereby greatly reducing the number of fixed-point digits of the Fourier transform circuit and/or the inverse Fourier transform circuit, reducing the circuit area and reducing the power consumption. In addition, the artificial noise of the present invention is not too much burden on the system, either by using random number sequence signal or by using masking operation for the data bits of the digital signal. In addition, the artificial noise used in the invention can also change the distribution shape and intensity of the power spectrum of the artificial noise according to the design requirement, so that the system can avoid the performance reduction caused by the great change of the channel or avoid the disconnection of data transmission when the environment temperature rises.
The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
[ symbolic description ]
100 signal processing circuit
105 processing unit
110,603FA-603 FD,603 NA-603 ND 1305,1330 Fourier transform circuit
115,604FA-604 FD,604 NA-604 ND equalizer
120,606,611,1320 inverse Fourier transform circuit
125,607 decision circuit
130 feedback circuit
600 data transmission device
601 analog to digital converter
602A-602D, 605, 319A-319D, 610,1052,1327: adding unit
608 digital to analog converter
612 random number sequence generating circuit
1051 virtual noise sequence generating circuit
1053 delay unit
1054 subtracting unit
1056 Shielding unit
1057 Filter
1055 virtual noise sequence generator
1310 conjugate arithmetic unit
1315 multiplication unit
1325 coefficient generating unit
1326 amplifying unit
Claims (10)
1. A signal processing circuit in digital domain includes:
a processing unit for receiving a time domain input signal and adding a random number sequence signal to the time domain input signal to generate a time domain processed input signal;
the first Fourier transform circuit is coupled with the processing unit and used for receiving the time domain processed input signal and performing first Fourier transform on the time domain processed input signal to generate a frequency domain processed input signal;
An equalizer for receiving the processed input signal and operating the processed input signal according to an equalizer parameter to generate a frequency domain output signal;
a first inverse Fourier transform circuit coupled to the equalizer for receiving the frequency domain output signal and performing a first inverse Fourier transform on the frequency domain output signal to generate a time domain output signal;
a decision circuit coupled to the first inverse Fourier transform circuit for generating a decision output signal according to the time domain output signal and generating a time domain error signal according to the decision output signal and the time domain output signal; and
a feedback circuit coupled to the decision circuit and the equalizer for generating a specific parameter signal according to the time domain error signal and the frequency domain processed input signal to determine the equalizer parameters of the equalizer.
2. The signal processing circuit of claim 1, wherein the processing unit comprises:
a pseudo noise sequence generating circuit for generating a pseudo noise sequence signal as the random number sequence signal; and
An adding unit coupled to the virtual noise sequence generating circuit for receiving the time domain input signal and the virtual noise sequence signal and adding the virtual noise sequence signal to the time domain input signal to generate the time domain processed input signal.
3. The signal processing circuit of claim 2, wherein the dummy noise sequence generating circuit comprises:
a virtual noise sequence generator for generating a preliminary virtual noise sequence signal;
a delay unit coupled to the virtual noise sequence generator for performing a specific delay on the preliminary virtual noise sequence signal to generate a delayed virtual noise sequence signal;
a subtracting unit for subtracting the delayed virtual noise sequence signal from the preliminary virtual noise sequence signal to generate the virtual noise sequence signal as the random number sequence signal.
4. The signal processing circuit of claim 1, wherein a signal spectral power of the random number sequence signal added by the processing unit is determined with reference to a first specific noise energy included in the frequency domain processed input signal output by the first fourier transform circuit, and a signal spectral power of the random number sequence signal is higher than a signal spectral power of the first specific noise energy.
5. The signal processing circuit of claim 1, wherein the feedback circuit comprises:
a second Fourier transform circuit coupled to the decision circuit for receiving the time domain error signal and performing a second Fourier transform on the time domain error signal to generate a frequency domain error signal;
a conjugate operation unit coupled to the first Fourier transform circuit for performing a conjugate operation on the frequency domain processed input signal to generate a conjugate signal;
a multiplication unit coupled to the conjugate operation unit and the second Fourier transform circuit for multiplying the conjugate signal and the frequency domain error signal to generate a gradient signal;
a second inverse Fourier transform circuit coupled to the multiplication unit for performing a second inverse Fourier transform on the gradient signal to generate a time domain gradient signal;
a coefficient generating unit, coupled to the second inverse Fourier transform circuit, for generating and accumulating parameters according to the time domain gradient signal and a specific step length to generate an accumulated parameter signal; and
a third Fourier transform circuit coupled to the coefficient generation unit for receiving the accumulated parameter signal and performing a third Fourier transform on the time domain error signal to generate the specific parameter signal as the equalizer parameter of the equalizer.
6. The signal processing circuit of claim 1, wherein a resolution of the time domain input signal corresponds to M bits, and the processing unit removes N bits of less significant of the resolution of the time domain input signal and leaves other bits equivalent to adding the random number sequence signal to the time domain input signal to generate the time domain processed input signal.
7. The signal processing circuit of claim 1, wherein the random number sequence signal added by the processing unit has a signal spectrum power that increases with increasing signal frequency.
8. The signal processing circuit of claim 1, wherein the signal processing circuit has a training mode and a data transmission mode, the processing unit adding the random number sequence signal to the time domain input signal during the training mode to generate the time domain processed input signal, a signal spectral power distribution of the random number sequence signal being determined with reference to a frequency response of the equalizer in the data transmission mode.
9. A signal processing circuit in digital domain includes:
a random number sequence generating circuit for generating a first near-end random number sequence signal and a first far-end random number sequence signal, wherein the first near-end random number sequence signal corresponds to a first transmission wire, the first far-end random number sequence signal corresponds to a first receiving wire, and the first transmission wire and the first receiving wire are a pair of transmission/receiving wires;
A first adding unit for receiving the first near-end random number sequence signal and a digital domain transmission signal corresponding to the first transmission wire, adding the first near-end random number sequence signal and the digital domain transmission signal corresponding to the first transmission wire, and generating a first time domain processed transmission signal;
a first Fourier transform circuit coupled to the first adder for converting the first time domain processed transmission signal into a first frequency domain processed transmission signal;
the first equalizer is coupled to the first Fourier transform circuit and used for performing first equalization compensation on the first frequency domain processed transmission signal so as to generate a first equalized transmission signal;
a first inverse Fourier transform circuit coupled to the first equalizer for generating a time domain equalized transmission result signal according to the first equalized transmission signal;
a second adding unit, coupled to a digital domain receiving signal corresponding to the first receiving wire outputted from an analog-digital converter and coupled to the first inverse fourier transform circuit, for adding the time domain equalized transmission result signal and the first far-end random number sequence signal to the digital domain receiving signal to generate a first time domain processed receiving signal;
A second Fourier transform circuit coupled to the second adder for converting the first time domain processed received signal to generate a first frequency domain processed received signal;
a second equalizer coupled to the second fourier transform circuit for performing a second equalization compensation on the first frequency domain processed received signal to generate a first equalized received signal;
a second inverse Fourier transform circuit coupled to the second equalizer for generating a time domain output signal according to the first equalized received signal; and
a decision circuit coupled to the second inverse Fourier transform circuit for generating a decision output signal according to the time domain output signal.
10. A method of signal processing in the digital domain, comprising:
receiving a time domain input signal, adding a random sequence signal to the time domain input signal to generate a time domain processed input signal;
receiving the time domain processed input signal, and performing a first fourier transform on the time domain processed input signal to generate a frequency domain processed input signal;
receiving the frequency domain processed input signal, and operating the frequency domain processed input signal according to an equalizer parameter to generate a frequency domain output signal;
Receiving the frequency domain output signal to perform a first inverse Fourier transform on the frequency domain output signal to generate a time domain output signal;
generating a decision output signal according to the time domain output signal, and generating a time domain error signal according to the decision output signal and the time domain output signal; and
generating a specific parameter signal according to the time domain error signal and the frequency domain processed input signal to determine the equalizer parameters of the equalizer.
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