CN113824659A - Signal processing circuit and method in digital domain - Google Patents
Signal processing circuit and method in digital domain Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
- H04L2025/03439—Fixed structures
- H04L2025/03522—Frequency domain
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L2025/03592—Adaptation methods
- H04L2025/03598—Algorithms
- H04L2025/03611—Iterative algorithms
- H04L2025/03636—Algorithms using least mean square [LMS]
Abstract
The present disclosure relates to a signal processing circuit and method in the digital domain. A method for signal processing in digital domain includes: adding a random number sequence signal to a time domain input signal to generate a time domain processed input signal; performing Fourier transform on the time domain processed input signal to generate a frequency domain processed input signal; calculating the input signal after the frequency domain processing according to the equalizer parameter to generate a frequency domain output signal; performing inverse Fourier transform on the frequency domain output signal to generate a time domain output signal; generating a decision output signal and a time domain error signal according to the time domain output signal; and generating a specific parameter signal according to the time domain error signal and the frequency domain processed input signal to determine the equalizer parameter of the equalizer.
Description
Technical Field
The present invention relates to a digital signal processing architecture, and more particularly, to a signal processing circuit and method in digital domain.
Background
Generally, in a high-speed data transmission system (for example, an ethernet 2.5G/5G/10G system), a Frequency-domain Block-wise Least mean square (FBLMS) system architecture is usually adopted, and fixed-point (fixed-point) finite word length (fixed word length) operation is used in an actual system. However, in a practical system using a frequency domain block-based least mean square algorithm with fixed-point number operation, quantization noise is introduced into the operation of a fourier transform circuit, and if the number of bits used by the fourier transform circuit is small, the output of the fourier transform circuit is very likely to generate noise. Since the fourier transform circuit is the most occupied circuit area and power consuming part of a system, it is practically impossible to suppress the effect of quantization noise by increasing the number of bits used. When the number of bits of the fourier transform circuit is small for saving circuit area or for saving energy, if the word length is not long enough, a specific noise pattern (coded noise pattern) is generated between the operations of the fourier transform circuit and the inverse fourier transform circuit, which affects the operation of the decision feedback equalizer and further affects the feedback control of the equalizer, and the worst case is that the equalizer coefficient is shifted to make the whole system unstable and unable to converge.
Disclosure of Invention
Therefore, one objective of the present invention is to provide a signal processing circuit in the digital domain to solve the problem of the conventional architecture.
According to an embodiment of the present invention, a signal processing circuit in a digital domain is disclosed. The signal processing circuit includes a processing unit, a first Fourier transform circuit, an equalizer, a first inverse Fourier transform circuit, a decision circuit and a feedback circuit. The processing unit is used for receiving a time domain input signal and adding a random number sequence signal to the time domain input signal to generate a time domain processed input signal. The first Fourier transform circuit is coupled to the processing unit and used for receiving the time domain processed input signal and carrying out first Fourier transform on the time domain processed input signal to generate a frequency domain processed input signal. The equalizer is used for receiving the input signal after the frequency domain processing, and calculating the input signal after the frequency domain processing according to an equalizer parameter to generate a frequency domain output signal. The first inverse Fourier transform circuit is coupled to the equalizer and is used for receiving the frequency domain output signal so as to perform a first inverse Fourier transform on the frequency domain output signal to generate a time domain output signal. The decision circuit is coupled to the first inverse Fourier transform circuit and is used for generating a decision output signal according to the time domain output signal and generating a time domain error signal according to the decision output signal and the time domain output signal. The feedback circuit is coupled to the decision circuit and the equalizer, and is used for generating a specific parameter signal according to the time domain error signal and the frequency domain processed input signal to determine the equalizer parameter of the equalizer.
According to the embodiments of the present invention, only a signal processing circuit in the digital domain is disclosed. The signal processing circuit comprises a random number sequence generating circuit, a first adding unit, a first Fourier transform circuit, a first equalizer, a first inverse Fourier transform circuit, a second adding unit, a second Fourier transform circuit, a second equalizer, a second inverse Fourier transform circuit and a decision circuit. The random number sequence generating circuit is used for generating a first near-end random number sequence signal and a first far-end random number sequence signal, the first near-end random number sequence signal corresponds to a first transmission wire, the first far-end random number sequence signal corresponds to a first receiving wire, and the first transmission wire and the first receiving wire form a pair of transmission/receiving wires. The first adding unit is used for receiving the first near-end random number sequence signal and a digital domain transmission signal corresponding to the first transmission wire, and adding the first near-end random number sequence signal and the digital domain transmission signal corresponding to the first transmission wire to generate a first time domain processed transmission signal. The first Fourier transform circuit is coupled to the first adding unit and is used for converting the first time domain processed transmission signal into a first frequency domain processed transmission signal. The first equalizer is coupled to the first fourier transform circuit and configured to perform a first equalization compensation on the first frequency domain processed transmission signal to generate a first equalized transmission signal. The first inverse Fourier transform circuit is coupled to the first equalizer and is used for generating a time domain equalized transmission result signal according to the first equalized transmission signal. The second adding unit is coupled to a digital domain receiving signal corresponding to the first receiving wire output by an analog-digital converter and coupled to the first inverse Fourier transform circuit, and is used for adding the time domain equalized transmission result signal and the first remote random number sequence signal to the digital domain receiving signal to generate a first time domain processed receiving signal. The second fourier transform circuit is coupled to the second adding unit, and is configured to convert the first time domain processed received signal into a first frequency domain processed received signal. The second equalizer is coupled to the second fourier transform circuit and configured to perform a second equalization compensation on the first frequency domain processed received signal to generate a first equalized received signal. The second inverse Fourier transform circuit is coupled to the second equalizer and is used for generating a time domain output signal according to the first equalized received signal. The decision circuit is coupled to the second inverse fourier transform circuit and configured to generate a decision output signal according to the time domain output signal, and generate a time domain error signal according to the decision output signal and the time domain output signal to feedback and determine an equalizer parameter of the second equalizer.
According to another embodiment of the present invention, a method for signal processing in the digital domain is disclosed. The method comprises the following steps: receiving a time domain input signal, adding a random number sequence signal to the time domain input signal to generate a time domain processed input signal; receiving the time domain processed input signal, and performing a first Fourier transform on the time domain processed input signal to generate a frequency domain processed input signal; receiving the input signal after the frequency domain processing, and calculating the input signal after the frequency domain processing according to an equalizer parameter to generate a frequency domain output signal; receiving the frequency domain output signal, and performing a first inverse Fourier transform on the frequency domain output signal to generate a time domain output signal; generating a decision output signal according to the time domain output signal, and generating a time domain error signal according to the decision output signal and the time domain output signal; and generating a specific parameter signal according to the time domain error signal and a conjugate signal of the frequency domain processed input signal to determine the equalizer parameter of the equalizer.
Drawings
FIG. 1 is a schematic block diagram of a signal processing circuit in the digital domain according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of the signal processing circuit shown in FIG. 1.
Fig. 3 is a schematic diagram of a virtual noise sequence generation circuit.
FIG. 4 is a schematic diagram of a different embodiment of the signal processing circuit shown in FIG. 1.
FIG. 5 is a schematic diagram of a different embodiment of the signal processing circuit shown in FIG. 1.
FIG. 6 is a block diagram of a portion of the architecture of a data transmission device in which the operation of the processing unit shown in FIG. 1 is applied, in accordance with an embodiment of the present invention.
Detailed Description
In a high speed data transmission system, such as Ethernet (Ethernet)2.5G/5G/10G, to avoid long channel response (channel response), a frequency domain block least mean square (FBLMS) system architecture is adopted. The system is stabilized by adding an artificially generated noise to the original digital input signal before the input of the fourier transform circuit, for example, in practice, the noise may be a random number sequence (white noise in spectrum, but not limited), and the data signal of the random number sequence is used to make the spectral power/energy of the data signal of the random number sequence higher than the measured spectral power/energy of the specific noise pattern, so as to cover the energy of the specific noise pattern and avoid the condition of accumulating the energy of the specific noise pattern at a specific frequency in the output of the fourier transform circuit. In addition, in practice, the effect of adding an artificially generated noise to the original digital input signal can be equivalently achieved by masking (mask) the Bit data (e.g., one or more Least Significant Bits (LSBs)) of the original digital input signal. In addition, the present invention can also be applied to a high-speed transmission communication system having multiple channels, such as the aforementioned Ethernet (Ethernet)2.5G/5G/10G system (but not limited thereto).
Referring to fig. 1, fig. 1 is a schematic block diagram of a Signal processing circuit 100 in a Digital domain according to an embodiment of the present invention, where the Signal processing circuit 100 is, for example, a Digital Signal Processor (DSP) of a receiver, and as shown in fig. 1, the Signal processing circuit 100 includes a processing unit 105, a fourier transform circuit 110, an equalizer 115, an inverse fourier transform circuit 120, a decision circuit 125, and a feedback circuit 130. The processing unit 105 is used for receiving a time domain input signal Xn (a digital signal) and adding a random number sequence signal to the time domain input signal Xn to generate a time domain processed input signal Xn'. The fourier transform circuit 110 is coupled to the processing unit 105 and is configured to receive the time-domain processed input signal Xn ', perform a fourier transform (e.g., a fast fourier transform operation) on the time-domain processed input signal Xn' to transform the time-domain signal into the frequency domain, so as to generate a frequency-domain processed input signal Xnf. The equalizer 115 is coupled to the fourier transform circuit 110, and is configured to receive the frequency domain processed input signal Xnf, and perform an equalization operation on the frequency domain processed input signal Xnf according to its own equalizer parameter Weq to generate a frequency domain output signal Ynf. The equalizer 115 is implemented, for example, by a Finite Impulse Response (FIR) equalizer and has a specific number of bits. The inverse fourier transform circuit 120 is coupled to the equalizer 115 and is configured to receive the frequency domain output signal Ynf, and perform an inverse fourier transform (e.g., an inverse fast fourier transform operation) on the frequency domain output signal Ynf to transform the frequency domain signal into the time domain, so as to generate a time domain output signal Yn. The decision circuit 125 is coupled to the inverse fourier transform circuit 120 for generating a decision output signal Do according to the time domain output signal Yn and generating a time domain error signal En according to the decision output signal Do and the time domain output signal Yn. For example, a decision device (slicer) is used to generate the decision output signal Do, and then the decision output signal Do is subtracted by the time domain output signal Yn to obtain the time domain error signal En. The feedback circuit 130 is coupled to the decision circuit 125 and the equalizer 115, and is used for generating a specific parameter signal Wnf according to the time domain error signal En and a conjugate signal of the frequency domain processed input signal Xnf to determine the equalizer parameter Weq of the equalizer 115. The feedback circuit 130 receives the frequency domain processed input signal Xnf outputted from the fourier transform circuit 110, performs a conjugate operation on the frequency domain processed input signal Xnf to obtain the conjugate signal, and then generates the specific parameter signal Wnf according to the conjugate signal and the time domain error signal En to feedback control the equalizer parameter Weq of the equalizer 115.
It should be noted that the intensity value (magnitude) of a Power Spectral Density (PSD) of the aforementioned random number sequence signal added by the processing unit 105 is determined by referring to the first specific noise energy contained in the frequency domain processed input signal Xnf outputted by the fourier transform circuit 110. If the finite word length using fixed-point numbers is not sufficient, as shown in fig. 1, the specific noise pattern is accumulated in the circuit elements of the feedback circuit 130 in time, which affects the feedback control of the equalizer 115, and further causes the equalizer coefficient to drift, so that the whole system is unstable and cannot converge. Therefore, to solve this problem, the processing unit 105 is configured before the input of the fourier transform circuit 110, and the time domain input signal Xn is processed to mask or reduce the specific noise in the output signal of the fourier transform circuit 110 (i.e. the frequency domain processed input signal Xnf). In practice, the specific noise refers to the noise appearing on at least one specific channel frequency, and the intensity value of the power spectral density of the random number sequence signal is added to be greater than the intensity value of the power spectral density of the noise on the at least one specific channel frequency. That is, equivalently, a white noise (white noise) is added to the input signal Xn, the power spectral density of which is uniform in intensity across all frequencies so that the effect of noise on at least one particular channel frequency can be masked or equalized, thus stabilizing the overall system without misconvergence. It should be noted that the spectral power of the noise at the at least one specific channel frequency is not different due to channel variation, but is determined by the number of bits used by a fourier transform circuit. Therefore, after the fourier transform circuit is determined, the circuit designer can measure the spectral power of the noise at the at least one specific channel frequency outputted by the fourier transform circuit to determine the spectral power strength of the random number sequence signal to be applied by the processing unit 105, and the measurement is not needed after the factory.
Referring to fig. 2 and 3, fig. 2 is a circuit diagram of the signal processing circuit 100 shown in fig. 1, and fig. 3 is a schematic diagram of a Pseudo-Noise sequence (Pseudo-Noise sequences) generating circuit 1051. In practice, as shown in fig. 2, the feedback circuit 130 includes a fourier transform circuit 1305, a conjugate operation unit 1310, a multiplication unit 1315, an inverse fourier transform circuit 1320, a coefficient generation unit 1325 and a fourier transform circuit 1330, for example. The fourier transform circuit 1305 is coupled to the decision circuit 125, and is configured to receive the time domain error signal En, perform a fourier transform (e.g., a fast fourier transform operation) on the time domain error signal En to transform the time domain signal into the frequency domain signal, so as to generate a frequency domain error signal Enf. The conjugate operation unit 1310 is coupled to the fourier transform circuit 110, and is configured to perform a conjugate operation on the frequency domain processed input signal Xnf to generate a conjugate signal
A multiplication unit 1315 coupled to the conjugate operation unit 1310 and the fourier transform circuit 1305 for converting the conjugate signal
Multiplied by the frequency domain error signal Enf to generate a gradient signal Gf. The inverse fourier transform circuit 1320 is coupled to the multiplication unit 1315 for performing an inverse fourier transform (e.g., an inverse fast fourier transform operation) on the gradient signal Gf to transform the frequency domain signal into the time domain signal to generate a time domain gradient signal Gn. A coefficient generation unit 1325 coupled to the inverse fourier transform circuit 1320 for generating coefficientsGenerating and accumulating parameters according to the time domain gradient signal Gn and a specific step size mu to generate an accumulated parameter signal Wn; for example, the amplifying unit 1326 of the coefficient generating unit 1325 first multiplies the time domain gradient signal Gn by a specific step μ to generate an amplified time domain gradient signal, and then the adding unit 1327 adds up the amplified time domain gradient signals generated at different time points before and at the current time point to generate the added parameter signal Wn. The fourier transform circuit 1330 is coupled to the coefficient generating unit 1325 for receiving the accumulated parameter signal Wn, performing a fourier transform (e.g., a fast fourier transform operation) on the accumulated parameter signal Wn to transform the time domain signal into the frequency domain signal, so as to generate the specific parameter signal Wnf for determining the equalizer parameter Weq of the equalizer 115.
In addition, the processing unit 105 includes a virtual noise sequence generating circuit 1051 and an adding unit 1052, for example. The pseudo noise sequence generating circuit 1051 is used for generating a pseudo noise sequence signal SPNS as the random number sequence signal, and the adding unit 1052 is coupled to the pseudo noise sequence generating circuit 1051 for receiving the time domain input signal Xn and the pseudo noise sequence signal SPNS generated by the pseudo noise sequence generating circuit 1051, and adding the pseudo noise sequence signal SPNS to the time domain input signal Xn to generate the time domain processed input signal Xn'. As shown in fig. 3, the pseudo noise sequence generating circuit 1051 includes a pseudo noise sequence generator 1055, a delay unit 1053 and a subtraction unit 1054. A pseudo noise sequence generator 1055 for generating a preliminary pseudo noise sequence signal, and a delay unit 1053 coupled to the pseudo noise sequence generator 1055 for delaying the preliminary pseudo noise sequence signal by a predetermined delay (e.g. z shown in FIG. 3)-1Represents a delay of one unit time; but not limited to) to generate a delayed virtual noise sequence signal, and a subtraction unit 1054 for receiving the preliminary virtual noise sequence signal and the delayed virtual noise sequence signal, subtracting the delayed virtual noise sequence signal from the preliminary virtual noise sequence signal to generate the virtual noise sequence signalThe sequence signal SPNS (i.e., the random number sequence signal).
It should be noted that, in the embodiment of fig. 2, the intensity value of the power spectral density of the random number sequence signal added by the processing unit 105 refers to the signal spectral power of the second specific noise energy contained in the frequency domain error signal Enf output by the fourier transform circuit 1305, and refers to the signal spectral power of the third specific noise energy contained in the specific parameter signal Wnf output by the fourier transform circuit 1330, in addition to the first specific noise energy contained in the frequency domain processed input signal Xnf output by the fourier transform circuit 110. For example, the power of the spectrum of the random number sequence signal is greater than or higher than the power of the spectrum of the first specific noise contained in the frequency domain processed input signal Xnf outputted by the fourier transform circuit 110, the power of the spectrum of the random number sequence signal is greater than the power of the spectrum of the second specific noise contained in the frequency domain error signal Enf outputted by the fourier transform circuit 1305, and the power of the spectrum of the random number sequence signal is greater than the power of the spectrum of the third specific noise contained in the specific parameter signal Wnf outputted by the fourier transform circuit 1330, so as to cover or homogenize the influence of the noise on at least a specific channel frequency in the operation of all fourier transform circuits, thereby stabilizing the whole system without causing the non-convergence. Furthermore, the preliminary pseudo noise sequence signal generated in fig. 3 is the preliminary random number sequence signal, and after delaying the preliminary random number sequence signal by a unit time, the preliminary random number sequence signal delayed by a unit time is subtracted from the preliminary random number sequence signal generated by the pseudo noise sequence generator 1055 to equivalently generate a random number sequence signal with a second-order random number as the output of the pseudo noise sequence generation circuit 1051, so that the input signal Xn can be more uncorrelated in practice, and the system can achieve the stability of the second-order random number; however, this is not a limitation of the present disclosure. In other embodiments, the preliminary random number sequence signal generated by the pseudo noise sequence generator 1055 can also be directly used as the output of the pseudo noise sequence generation circuit 1051, so that it is practically irrelevant to the input signal Xn, and the system achieves the stability of a first-order random number. In addition, based on the same principle, in other embodiments, the stabilization of the n-order random number of the system can be achieved by performing a plurality of different delays and subtractions on the generated random number sequence signal, wherein n is greater than or equal to 3.
Referring to fig. 4, fig. 4 is a schematic diagram of a different embodiment of the signal processing circuit 100 shown in fig. 1. As shown in fig. 4, the processing unit 105 is disposed between an adc 101 and the fourier transform circuit 110, and is used for processing a digital signal (i.e. the time domain input signal Xn) generated by the adc 101 converting an analog signal, and the processing unit 105 includes, for example, a masking unit 1056, wherein the masking unit 1056 is used to mask the least significant bit of a signal bit resolution of the time domain input signal Xn, so that the information of the number of bits of the masked input signal Xn' is lower than the information of the number of bits of the signal bit resolution of the time domain input signal Xn, so as to achieve the effect of adding a random number sequence signal to the time domain input signal Xn. For example, the resolution of the time domain input signal Xn corresponds to M bits, M is equal to 8 (but not limited), and the processing unit 305 removes the least significant N bits (LSBs) (N is equal to 2, but not limited) of the resolution of the time domain input signal Xn that are less significant and leaves the other bits (i.e., 6 bits of information) to equivalently achieve the goal of adding a random number sequence signal (i.e., noise signal) to the time domain input signal Xn to generate the time domain processed input signal Xn'. In addition, the value of N is determined by referring to the first specific noise energy contained in the frequency domain processed input signal Xnf outputted from the fourier transform circuit 110, so as to homogenize the noise energy in the frequency domain processed input signal Xnf to cover the first specific noise energy, thereby stabilizing the system. Alternatively, in one embodiment, the value of N is determined by referring to the first specific noise energy contained in the frequency domain processed input signal Xnf output by the fourier transform circuit 110, and also by referring to the signal spectrum power of the second specific noise energy contained in the frequency domain error signal Enf output by the fourier transform circuit 1305 and the signal spectrum power of the third specific noise energy contained in the specific parameter signal Wnf output by the fourier transform circuit 1330, so as to homogenize the noise energy in the frequency domain processed input signal Xnf, the frequency domain error signal Enf and the specific parameter signal Wnf, thereby masking the noise energy and stabilizing the system.
Referring to fig. 5, fig. 5 is a schematic diagram of a different embodiment of the signal processing circuit 100 shown in fig. 1. As shown in fig. 5, the processing unit 105 is disposed between the adc 101 and the fourier transform circuit 110, and is used for processing a digital signal (i.e. the time domain input signal Xn) generated by the adc 101 converting an analog signal. The processing unit 105 includes a filter 1057, wherein the filter 1057 is used to adjust the spectrum power of the outputted random number sequence signal to generate an adjusted random number sequence signal, and output the adjusted random number sequence signal. Wherein the adjusted random-number-sequence signal has a signal spectrum that increases with increasing signal frequency, or the random-number-sequence signal has an increasing amount of the signal spectrum power that increases with increasing operating temperature of the signal processing circuit. For example, as shown in fig. 5, the higher the channel frequency is, the higher the power of the adjusted random number sequence signal is, so that the energy of the specific noise outputted by one or more fourier transform circuits can be uniformly covered at the higher frequency. For example, for a data transmission device applied to a high-speed wired network, the signal processing circuit 100, such as the above, may be disposed in a data transmission device connected to a link partner device (link partner device) through an ethernet 802.3 series standard, where the data transmission device has a training mode (training mode) and a data transmission mode (data mode), and although the data transmission device may inform the link partner device of parameters for feedback control obtained after data transmission training in the training mode, so that the link partner device may communicate with the data transmission device based on the parameters for feedback control when switching to the data transmission mode, when high-speed data transmission is performed in the data transmission mode, the operating temperature or the system environment temperature may increase, and a large change of the channel equalizer parameters may cause a large insertion loss (insertion loss) due to high temperature, so that the system does not have a large change Case of convergence of the method. Therefore, in order to solve the problem of non-convergence in a high temperature system, the signal processing circuit 100 adjusts the random number sequence signal having uniform spectrum power at each channel frequency, so that the spectrum power of the adjusted random number sequence signal increases with the increase of the frequency, thereby shielding the noise energy caused by high temperature during high frequency operation, and preventing the noise energy from generating an accumulation effect at a specific channel frequency to make the system unstable. That is, in order to avoid the noise energy from generating an accumulation effect on a specific high frequency channel frequency, a power of the signal spectrum of the adjusted random number sequence signal corresponding to the specific high frequency channel frequency is greater than a power of the noise energy on the specific channel frequency, and a power variation of the signal spectrum of the adjusted random number sequence signal between adjacent channel frequencies is smaller than a power variation of the noise energy between the specific channel frequency and the adjacent channel frequency, so that the noise energy is not excessively accumulated on the specific channel frequency, and the entire system can be stably converged. Furthermore, in one embodiment, the shape of the distribution of the power spectrum of the desired random number sequence signal to be added may also be determined according to the temperature difference to be supported, for example, if the temperature difference to be supported is larger (i.e. the difference of the high frequency power representing the current insertion loss is larger), the shape of the distribution of the power spectrum needs to be increased at higher frequencies.
Referring to fig. 6, fig. 6 is a circuit block diagram illustrating a portion of the architecture of a data transmission device 600 to which the operations of the processing unit shown in fig. 1 are applied according to an embodiment of the present invention. As shown in fig. 6, the data transmission apparatus 600 includes an adc 601, adding units 602A, 602B, 602C, 602D, 609A, 609B, 609C, 609D, 605, 610, fourier transform circuits 603FA, 603FB, 603FC, 603FD,603NA, 603NB, 603NC, 603ND, equalizer 604FA, 604FB, 604FC, 604FD,604NA, 604NB, 604NC, 604ND, inverse fourier transform circuits 606,611, decision circuit 607, digital-analog converter 608, and random number sequence generating circuit 612. The data transmission apparatus 600 applied to high-speed transmission in a cable network is connected to a link peer apparatus through the ethernet 802.3 series standard, and the data transmission apparatus 600 is a transceiver apparatus and has a receiver (receiver) architecture and a transmitter (transmitter) architecture, and has 4 twisted pair transmission mechanism structures (e.g. 2 pairs of wire receiving and 2 pairs of wire transmitting). Wherein the adc 601, the adder 602, the fourier transform circuits 603FA, 603FB, 603FC, 603FD, the equalizers 604FA, 604FB, 604FC, 604FD, the adder 605, the inverse fourier transform circuit 606 and the decision circuit 607 are located in the receiver's receive path, and the dac 608 is located in the transmitter's transmit path.
The TX _ Ch _ a signal is a digital domain transmission signal corresponding to a first transmission line, which is converted by the digital-to-analog converter 608 to generate an analog transmission signal, and then the analog transmission signal is transmitted from an analog transmission circuit (not shown in fig. 6) of the data transmission apparatus 600 to a corresponding link-peer apparatus through the first transmission line. The signal N _ Ch _ B, the signal N _ Ch _ C, and the signal N _ Ch _ D refer to the transmission signals of the digital domains corresponding to the second, third, and fourth transmission lines, respectively. The adding unit 609A adds the transmission signal TX _ Ch _ a corresponding to the first transmission line and a first near-end random number sequence signal N _ PN _ a corresponding to the first transmission line to generate a first time domain processed transmission signal to the fourier transform circuit 603 NA. The fourier transform circuit 603NA is coupled to the adding unit 609A and is configured to transform the first time domain processed transmit signal from time domain to frequency domain to generate a first frequency domain processed transmit signal to the equalizer 604 NA. The equalizer 604NA is coupled to the fourier transform circuit 603NA and configured to perform equalization compensation (e.g., echo (echo) compensation cancellation) on the first frequency domain processed transmit signal according to an equalizer parameter thereof to generate a first equalized transmit signal to the adding unit 610. Similarly, the adding unit 609B adds the transmitting signal N _ Ch _ B corresponding to the second transmitting wire and a second near-end random number sequence signal N _ PN _ B corresponding to the second transmitting wire to generate a second time domain processed transmitting signal to the fourier transform circuit 603 NB. The fourier transform circuit 603NB is coupled to the adder 609B and is configured to convert the second time domain processed transmit signal from time domain to frequency domain to generate a second frequency domain processed transmit signal to the equalizer 604 NB. The equalizer 604NB is coupled to the fourier transform circuit 603NB, and is configured to perform equalization compensation (e.g., Near-End Crosstalk (NEXT) compensation cancellation) on the second frequency domain processed transmission signal according to an equalizer parameter thereof to generate a second equalized transmission signal to the adding unit 610. Similarly, the operation principle of the adding units 609C and 609D is similar to that described above, and therefore, the description thereof is omitted. Then, the adding unit 610 adds the first, second, third and fourth equalized transmission signals to generate an equalized transmission result signal to the inverse fourier transform circuit 611, and the inverse fourier transform circuit 611 is coupled to the adding unit 610 and is configured to convert the equalized transmission result signal from the frequency domain to the time domain to generate a time domain equalized transmission result signal to the adding unit 602A.
For the receiver path, the adc 601 is used to receive an analog received signal (an analog input signal) corresponding to a first receiving wire to convert the analog received signal from the analog domain to the digital domain to generate a digital domain input signal RX _ Ch _ a (corresponding to the first receiving wire). The signal F _ Ch _ B, the signal F _ Ch _ C, and the signal F _ Ch _ D refer to the receiving signals of the different digital domains corresponding to the second, third, and fourth receiving wires, respectively; the received signals are received over wires from the remote link-end device.
The adder 602A is coupled to the adc 601 and configured to add the input signal RX _ Ch _ a, an equalized transmission result signal corresponding to the transmission lines, and a first remote random number sequence signal F _ PN _ a to generate a first time domain processed received signal to the fourier transform circuit 603 FA. The fourier transform circuit 603FA is coupled to the adding unit 602A, and is configured to convert the first time domain processed received signal from the time domain to the frequency domain to generate a first frequency domain processed received signal to the equalizer 604 FA. The equalizer 604FA is coupled to the fourier transform circuit 603FA, and is configured to perform equalization compensation on the first frequency domain processed received signal according to the equalizer parameter thereof to compensate for a channel response, so as to reduce an error rate of the communication system transmission, and to generate a first equalized received signal to the adding unit 605. Similarly, the adding unit 602B is coupled to another adc (not shown in fig. 6) of the data transmission apparatus 600 and configured to add an input signal F _ Ch _ a corresponding to the second receiving wire and a second remote random number sequence signal F _ PN _ B to generate a second time domain processed receiving signal to the fourier transform circuit 603 FB. The fourier transform circuit 603FB is coupled to the adding unit 602B and is configured to convert the second time domain processed received signal from the time domain to the frequency domain to generate a second frequency domain processed received signal to the equalizer 604 FB. The equalizer 604FB is coupled to the fourier transform circuit 603FB, and is configured to perform equalization compensation on the second frequency domain processed received signal according to the equalizer parameter thereof to compensate for a response of a channel, so as to reduce an error rate of the communication system transmission, and to generate a second equalized received signal to the adding unit 605. Similarly, the operation principle of the adding units 602C and 602D is similar to that described above, and therefore, the description thereof is omitted. The adding unit 605 then adds the first, second, third and fourth equalized received signals to generate an equalized received result signal to the inverse fourier transform circuit 606, the inverse fourier transform circuit 606 is coupled to the adding unit 605 and is used to convert the frequency domain equalized received result signal from the frequency domain to the time domain to generate a time domain output signal to the decision circuit 607, the decision circuit is coupled to the inverse fourier transform circuit 606 and is used to generate a decision output signal Do according to the time domain output signal Y _ a (the received signal corresponding to the first receiving wire) and a time domain error signal En according to the decision output signal Do and the time domain output signal Y _ a, for example, a decision device is used to generate the decision output signal Do, and then the decision output signal Do is subtracted from the time domain output signal Y _ a to obtain the time domain error signal En, the time domain error signal En is then fed into a feedback circuit (not shown in fig. 6) of the data transmission apparatus 600 to generate equalizer parameters of the equalizer 604FA corresponding to the first receiving wire through feedback control, and the time domain error signal En can also be fed into other feedback circuits (not shown in fig. 6) of the data transmission apparatus 600 to generate equalizer parameters of the equalizer 604FB, the equalizer 604FC and the equalizer 604FD corresponding to the second, third and fourth receiving wires, respectively.
It should be noted that the first near-end random number sequence signal N _ PN _ a, the second near-end random number sequence signal N _ PN _ B, the third near-end random number sequence signal N _ PN _ C, the fourth near-end random number sequence signal N _ PN _ D, the first far-end random number sequence signal F _ PN _ a, the second far-end random number sequence signal F _ PN _ B, the third far-end random number sequence signal F _ PN _ C, and the fourth far-end random number sequence signal F _ PN _ D are all generated by the random number sequence generating circuit 612, and the data variations of the random number sequence signals are all mutually uncorrelated. In practice, the random number sequence generating circuit 612 may first generate a preliminary random number sequence signal, then apply eight different unit delays to the preliminary random number sequence signal to generate eight different delayed random number sequence signals, and then subtract the eight different delayed random number sequence signals from the preliminary random number sequence signal to obtain the final output independent random number sequence signals. However, this is not a limitation, and in other embodiments, different generation methods may be used to generate a plurality of independent random number sequence signals.
Furthermore, in the embodiment shown in fig. 6, the first near random number sequence signal N _ PN _ a, the second near random number sequence signal N _ PN _ B, the third near random number sequence signal N _ PN _ C, and the fourth near random number sequence signal N _ PN _ D are applied to the transmission output signals corresponding to different transmission wires to generate the processed transmission signals, and then the processed transmission signals are transmitted to the fourier transform circuits 603NA, 603NB, 603NC, 603ND, so as to avoid the situation that the systems cannot be converged due to the insufficient number of bits used by the fourier transform circuits 603NA, 603NB, 603NC, 603ND, and in addition, the first far random number sequence signal F _ PN _ a, the second far random number sequence signal F _ PN _ B, the third far random number sequence signal F _ PN _ C, and F _ PN _ D are applied respectively, The fourth remote random number sequence signal F _ PN _ D is transmitted to the receiving signals corresponding to different receiving wires to generate the processed receiving signals, and then the processed receiving signals are transmitted to the fourier transform circuits 603FA, 603FB, 603FC, 603FD, so as to avoid the situation that the system can not be converged due to insufficient number of bits employed by the fourier transform circuits 603FA, 603FB, 603FC, 603 FD. Therefore, the signal spectrum power distribution of the random number sequence signals is used to homogenize the specific noise energy generated by the accumulation introduced by the corresponding fourier transform circuits due to insufficient number of bits, so that the noise energy in the output signals of the corresponding fourier transform circuits is relatively dispersed to different channel frequencies, and the system cannot be converged due to accumulation to a certain channel frequency. The signal spectrum power distribution of the random number sequence signals is determined by referring to the corresponding Fourier transform circuit because of the number of bits and/or by referring to the power spectrum distribution of specific noise energy in the output signal of the corresponding Fourier transform circuit. In the above embodiment, when operating in the training mode, the present invention stabilizes the system operation by generating a plurality of artificial noises without divergence, and once entering the data transmission mode, i.e. after transmitting the feedback control equalizer coefficients to a link-end device, the random number sequence generating circuit 612 shown in fig. 6 can turn off the artificial noises (i.e. the random number sequence signals) without adding the artificial noises to the corresponding digital signals, so as to improve the system performance.
It should be noted that the concept of the system architecture of fig. 6 may also be applied to an architecture of one or more pairs of transmit/receive wires. For example, if a system only uses a pair of transmit/receive wires for data transmission, the random number sequence generating circuit 612 only needs to generate the random number sequence signal F _ PN _ a and the random number sequence signal N _ PN _ a, but does not need to generate the other random number sequence signals, and other circuit elements may be omitted depending on the design variation. Similarly, if the two pairs of transmission/reception lines are used, the random number sequence generating circuit 612 only needs to generate the random number sequence signal F _ PN _ a, the random number sequence signal N _ PN _ a, the random number sequence signal F _ PN _ B, and the random number sequence signal N _ PN _ B, but does not need to generate the other random number sequence signals, and other circuit elements may be omitted according to design variations.
In summary, the present invention can avoid unstable system coefficient drift caused by insufficient word length by adding artificial noise (i.e. the above-mentioned random number sequence signal) to the received signal in the digital domain, and relatively greatly reduce the number of fixed-point digits in the fourier transform circuit and/or the inverse fourier transform circuit, thereby reducing circuit area and power consumption. In addition, the artificial noise employed by the present invention does not cause a large burden on the system whether the random number sequence signal is employed or the masking operation is performed on the data bits of the digital signal. In addition, the artificial noise used in the present invention can also change the distribution shape and intensity of the power spectrum of the artificial noise according to the design requirement, so that the system can avoid the performance degradation caused by the large change of the channel or avoid the disconnection of the data transmission when the ambient temperature rises.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention should be covered by the present invention.
[ notation ] to show
100 signal processing circuit
105 processing unit
110,603FA to 603FD,603NA to 603ND,1305,1330 Fourier transform circuit
115,604 FA-604 FD,604 NA-604 ND equalizer
120,606,611,1320 inverse Fourier transform circuit
125,607 decision circuit
130 feedback circuit
600 data transmission device
601 analog-to-digital converter
602A-602D, 605,609A-609D, 610,1052,1327 addition unit
608 digital-to-analog converter
612 random number sequence generating circuit
1051 virtual noise sequence generating circuit
1053 delay unit
1054 subtraction unit
1056 shielding unit
1057 filter
1055 virtual noise sequence generator
1310 conjugate arithmetic unit
1315 multiplication unit
1325 coefficient generation unit
1326 amplifying unit
Claims (10)
1. A signal processing circuit in digital domain comprises:
a processing unit for receiving a time domain input signal and adding a random number sequence signal to the time domain input signal to generate a time domain processed input signal;
a first Fourier transform circuit, coupled to the processing unit, for receiving the time domain processed input signal, and performing a first Fourier transform on the time domain processed input signal to generate a frequency domain processed input signal;
an equalizer for receiving the input signal after the frequency domain processing, and calculating the input signal after the frequency domain processing according to an equalizer parameter to generate a frequency domain output signal;
a first inverse Fourier transform circuit, coupled to the equalizer, for receiving the frequency domain output signal and performing a first inverse Fourier transform on the frequency domain output signal to generate a time domain output signal;
a decision circuit, coupled to the first inverse fourier transform circuit, for generating a decision output signal according to the time domain output signal, and generating a time domain error signal according to the decision output signal and the time domain output signal; and
a feedback circuit, coupled to the decision circuit and the equalizer, for generating a specific parameter signal according to the time domain error signal and the frequency domain processed input signal to determine the equalizer parameter of the equalizer.
2. The signal processing circuit of claim 1, wherein the processing unit comprises:
a pseudo noise sequence generating circuit for generating a pseudo noise sequence signal as the random number sequence signal; and
an adding unit, coupled to the virtual noise sequence generating circuit, for receiving the time domain input signal and the virtual noise sequence signal, and adding the virtual noise sequence signal to the time domain input signal to generate the time domain processed input signal.
3. The signal processing circuit of claim 2, wherein the virtual noise sequence generating circuit comprises:
a virtual noise sequence generator for generating a preliminary virtual noise sequence signal;
a delay unit, coupled to the virtual noise sequence generator, for performing a specific delay on the preliminary virtual noise sequence signal to generate a delayed virtual noise sequence signal;
a subtraction unit for subtracting the delayed pseudo noise sequence signal from the preliminary pseudo noise sequence signal to generate the pseudo noise sequence signal as the random number sequence signal.
4. The signal processing circuit according to claim 1, wherein a signal spectrum power of the random number sequence signal added by the processing unit is determined with reference to a first specific noise energy contained in the frequency domain processed input signal outputted by the first Fourier transform circuit, and a signal spectrum power of the random number sequence signal is higher than a signal spectrum power of the first specific noise energy.
5. The signal processing circuit of claim 1, wherein the feedback circuit comprises:
a second Fourier transform circuit, coupled to the decision circuit, for receiving the time domain error signal and performing a second Fourier transform on the time domain error signal to generate a frequency domain error signal;
a conjugate operation unit coupled to the first fourier transform circuit for performing a conjugate operation on the frequency domain processed input signal to generate a conjugate signal;
a multiplication unit, coupled to the conjugate operation unit and the second fourier transform circuit, for multiplying the conjugate signal by the frequency domain error signal to generate a gradient signal;
a second inverse Fourier transform circuit, coupled to the multiplication unit, for performing a second inverse Fourier transform on the gradient signal to generate a time domain gradient signal;
a coefficient generating unit, coupled to the second inverse fourier transform circuit, for generating and accumulating parameters according to the time domain gradient signal and a specific step length to generate an accumulated parameter signal; and
a third Fourier transform circuit, coupled to the coefficient generating unit, for receiving the accumulated parameter signal and performing a third Fourier transform on the time domain error signal to generate a specific parameter signal as the equalizer parameter of the equalizer.
6. The signal processing circuit of claim 1, wherein a resolution of the time domain input signal corresponds to M bits, and the processing unit removes N bits of the time domain input signal that are less important in the resolution and leaves the other bits to equivalently achieve adding the random number sequence signal to the time domain input signal to generate the time domain processed input signal.
7. The signal processing circuit of claim 1, wherein the random number sequence signal added by the processing unit has a signal spectrum power that increases with increasing signal frequency.
8. The signal processing circuit of claim 1, wherein the signal processing circuit has a training mode and a data transmission mode, the processing unit adds the random number sequence signal to the time domain input signal to generate the time domain processed input signal during the training mode, a signal spectrum power distribution of the random number sequence signal is determined with reference to a frequency response of the equalizer in the data transmission mode.
9. A signal processing circuit in digital domain comprises:
a random number sequence generating circuit for generating a first near-end random number sequence signal and a first far-end random number sequence signal, wherein the first near-end random number sequence signal corresponds to a first transmitting wire, the first far-end random number sequence signal corresponds to a first receiving wire, and the first transmitting wire and the first receiving wire are a pair of transmitting/receiving wires;
a first adding unit for receiving the first near-end random number sequence signal and a digital domain transmission signal corresponding to the first transmission wire, and adding the first near-end random number sequence signal and the digital domain transmission signal corresponding to the first transmission wire to generate a first time domain processed transmission signal;
a first Fourier transform circuit, coupled to the first adder, for converting the first time domain processed transmission signal into a first frequency domain processed transmission signal;
a first equalizer coupled to the first fourier transform circuit for performing a first equalization compensation on the first frequency domain processed transmission signal to generate a first equalized transmission signal;
a first inverse Fourier transform circuit, coupled to the first equalizer, for generating a time domain equalized transmission result signal according to the first equalized transmission signal;
a second adding unit, coupled to a digital domain receiving signal corresponding to the first receiving wire outputted by an analog-to-digital converter and coupled to the first inverse fourier transform circuit, for adding the time domain equalized transmission result signal and the first remote random number sequence signal to the digital domain receiving signal to generate a first time domain processed receiving signal;
a second fourier transform circuit, coupled to the second adding unit, for converting the first time domain processed received signal into a first frequency domain processed received signal;
a second equalizer coupled to the second fourier transform circuit for performing a second equalization compensation on the first frequency domain processed received signal to generate a first equalized received signal;
a second inverse Fourier transform circuit, coupled to the second equalizer, for generating a time domain output signal according to the first equalized received signal; and
a decision circuit, coupled to the second inverse fourier transform circuit, for generating a decision output signal according to the time domain output signal.
10. A method for signal processing in digital domain, comprising:
receiving a time domain input signal, adding a random number sequence signal to the time domain input signal to generate a time domain processed input signal;
receiving the time domain processed input signal, and performing a first Fourier transform on the time domain processed input signal to generate a frequency domain processed input signal;
receiving the input signal after the frequency domain processing, and calculating the input signal after the frequency domain processing according to an equalizer parameter to generate a frequency domain output signal;
receiving the frequency domain output signal, and performing a first inverse Fourier transform on the frequency domain output signal to generate a time domain output signal;
generating a decision output signal according to the time domain output signal, and generating a time domain error signal according to the decision output signal and the time domain output signal; and
generating a specific parameter signal according to the time domain error signal and the frequency domain processed input signal to determine the equalizer parameter of the equalizer.
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