CN113821396A - Processor running state monitoring and diagnosing method and device - Google Patents
Processor running state monitoring and diagnosing method and device Download PDFInfo
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- CN113821396A CN113821396A CN202010559583.7A CN202010559583A CN113821396A CN 113821396 A CN113821396 A CN 113821396A CN 202010559583 A CN202010559583 A CN 202010559583A CN 113821396 A CN113821396 A CN 113821396A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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Abstract
The invention provides a method for monitoring and diagnosing running state of a processor, which is characterized in that a main processor is heterogeneous with a coprocessor and comprises the following steps: reading two self-checking sequences generated by the coprocessor through the main processor and carrying out double self-checking polynomial built-in self-checking calculation according to the two self-checking sequences to obtain a first calculation result; carrying out error detection and error correction data verification on the two self-checking sequences generated by the coprocessor, and carrying out double self-checking polynomial built-in self-checking calculation through the main processor after the verification is passed to obtain a second calculation result; and comparing the first calculation result with the second calculation result, and if the first calculation result is inconsistent with the second calculation result and exceeds the preset times, judging that the operation of the main processor is abnormal. The invention adopts two heterogeneous processors, and the coprocessor has lower cost compared with the main processor, has little requirement on other functions of the coprocessor, does not influence the normal operation of the train and is easy to realize the monitoring and diagnosis of the main processor.
Description
Technical Field
The invention relates to the technical field of rail transit, in particular to a method and a device for monitoring and diagnosing the running state of a processor.
Background
The train network control platform is the brain of a train, has the functions of guaranteeing train data communication, data acquisition, safety control, vehicle-mounted information service and the like, and is an important system for guaranteeing the safe operation of the train. With the diversified development of rail transit train control and service services, the requirements of train communication networks on the credibility, reliability and other safety of control systems are continuously improved.
The processor of the main control part is the core part of the control system, and the significance of ensuring the reliability and the safety of the main control part is very important. The main control processor is used as a core part of the train control system, so that the reliable and safe operation of the train control system is ensured, and the safety and reliability of key data transmission of a train control network are also ensured.
Therefore, the invention provides a method and a device for monitoring and diagnosing the running state of a processor.
Disclosure of Invention
In order to solve the above problems, the present invention provides a method for monitoring and diagnosing processor running status, wherein a main processor is heterogeneous to a coprocessor, the method comprising the following steps:
the method comprises the following steps: reading two self-checking sequences generated by the coprocessor through the main processor and carrying out double self-checking polynomial built-in self-checking calculation according to the two self-checking sequences to obtain a first calculation result;
step two: performing error detection and error correction data verification on the two self-checking sequences generated by the coprocessor, and performing double self-checking polynomial built-in self-checking calculation through the main processor after the verification is passed to obtain a second calculation result;
step three: and comparing the first calculation result with the second calculation result, and if the first calculation result is inconsistent with the second calculation result and exceeds a preset number of times, judging that the main processor is abnormal in operation.
According to an embodiment of the present invention, the self-test computation of the dual self-test polynomial comprises the following steps:
based on a first self-checking algorithm, performing self-checking calculation on a first self-checking sequence of the two self-checking sequences to obtain a first data group;
and calculating a second self-checking sequence in the two self-checking sequences by combining the first data group based on a second self-checking algorithm to obtain an internal self-checking calculation result, wherein the internal self-checking calculation result comprises the first calculation result and the second calculation result.
According to one embodiment of the invention, the first self-test algorithm comprises the following formula:
wherein, Xn,n＝0-9Representing said first data set, Mod representing a rounding calculation, Dn1Represents the set of self-test sequences in the first self-test sequence.
According to an embodiment of the invention, the second self-test algorithm comprises the following formula:
wherein, Yn,n＝0-9Representing the result of said self-test calculation, Dn2Represents the set of self-test sequences in the second self-test sequence.
According to an embodiment of the present invention, both self-test sequences include a self-test period number, an inverse code of the self-test period number, a set of self-test sequences, and a check value.
According to one embodiment of the present invention, the error detection and correction data check comprises the following steps:
and checking the read self-checking period number, the inverse code of the self-checking period number and the self-checking sequence group in the two self-checking sequences generated by the coprocessor by using a generating polynomial in a cyclic redundancy check mode through check values.
According to one embodiment of the invention, the method comprises the steps of:
storing data in a running state monitoring diagnostic process through a dual-port memory connected with the main processor and the coprocessor;
four storage areas are divided in the dual-port memory, and are respectively two self-checking sequence storage areas generated by the coprocessor, a self-checking calculation result storage area in the machine, a data receiving and transmitting area and a reserved area which are calculated by the coprocessor and the main processor.
According to an embodiment of the present invention, before the step one, the method further comprises the following steps:
initializing the synchronous state and running state memories of the main processor and the coprocessor, and carrying out state synchronization on the main processor and the coprocessor.
According to an embodiment of the present invention, if the synchronization between the host processor and the coprocessor is unsuccessful, the operation is terminated after an exception flag is given.
According to another aspect of the present invention, there is provided a processor running state monitoring and diagnosis apparatus, a main processor being heterogeneous to a coprocessor, the apparatus comprising:
the calling module is used for reading the two self-checking sequences generated by the coprocessor through the main processor and carrying out double self-checking polynomial built-in self-checking calculation according to the two self-checking sequences to obtain a first calculation result;
the calculation module is used for carrying out error detection and error correction data verification on the two self-checking sequences generated by the coprocessor, and carrying out double self-checking polynomial built-in self-checking calculation through the main processor after the verification is passed to obtain a second calculation result;
and the comparison module is used for comparing the first calculation result with the second calculation result, and if the first calculation result is inconsistent with the second calculation result and exceeds a preset number of times, judging that the operation of the main processor is abnormal.
The method and the device for monitoring and diagnosing the running state of the processor adopt two heterogeneous processors, and the coprocessor has lower cost and low requirement on other functions of the coprocessor compared with a main processor, does not influence the normal running of a train and is easy to realize the monitoring and diagnosis of the main processor; the invention carries out built-in self-checking and adopts a cyclic redundancy check mode, is simple and efficient, is applied to the monitoring and diagnosis of the coprocessor of the train network control system on the main processor, and can improve the reliability and the safety of the main processor.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow diagram of a processor operating state monitoring diagnostic method according to one embodiment of the present invention;
FIG. 2 shows a flow chart of a built-in self-test computation of a dual self-test polynomial in accordance with an embodiment of the invention;
FIG. 3 illustrates a processor operating condition monitoring and diagnostic system architecture diagram according to one embodiment of the present invention;
FIG. 4 is a schematic diagram showing the division of a memory area of a dual port memory according to an embodiment of the invention;
FIG. 5 is a flow diagram of a processor operating condition monitoring diagnostic method according to another embodiment of the present invention; and
fig. 6 is a block diagram showing a configuration of a processor operation state monitoring and diagnosing apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in further detail below with reference to the accompanying drawings.
In the present invention, the main processor is heterogeneous to the coprocessor, as shown in fig. 3, the main processor and the coprocessor are connected to both ends of a dual port memory (DPRAM), and data interaction is performed between the main processor and the dual port memory, and between the coprocessor and the dual port memory through a local bus of a train.
In order to diagnose the running state of a train main control unit processor in real time, two heterogeneous CPUs are designed on a hardware architecture, a group of self-checking polynomials are generated by utilizing a built-in self-checking mode, the two heterogeneous processors (different software) respectively carry out calculation, and the final operation result is compared to realize the diagnosis and detection functions.
FIG. 1 is a flow chart of a processor operating state monitoring and diagnosing method according to an embodiment of the present invention.
As shown in fig. 1, in step S101, two self-test sequences generated by the coprocessor are read by the main processor, and a first calculation result obtained by performing a dual self-test polynomial internal self-test calculation according to the two self-test sequences is obtained.
Specifically, the main processor reads two self-checking sequences of the coprocessor from the dual-port memory and the coprocessor performs double self-checking polynomial self-checking calculation according to the two self-checking sequences to obtain a first calculation result.
As shown in fig. 1, in step S102, error detection and error correction data verification are performed on the two self-test sequences generated by the coprocessor, and after the verification is passed, the main processor performs dual self-test polynomial internal self-test calculation to obtain a second calculation result.
Specifically, firstly, the two self-checking sequences generated by the co-processing read by the main processor need to be checked for error detection and error correction, so that the influence on the subsequent monitoring and diagnosis result of the main processor caused by data transmission errors in the data transmission process is avoided. In one embodiment, the error detection and correction check is performed by a cyclic redundancy check.
Furthermore, both the self-check sequences include a self-check period number, an inverse code of the self-check period number, a self-check sequence set, and a check value.
In one embodiment, error detection and correction data checking comprises the steps of: and checking the self-checking period number, the inverse code of the self-checking period number and the self-checking sequence group in the two self-checking sequences generated by the read coprocessor by using a generating polynomial in a cyclic redundancy check mode through check values.
Fig. 2 shows a flow chart of the self-checking computation in the machine of the dual self-checking polynomial according to an embodiment of the invention.
In the application, in order to monitor and diagnose the running state of the main processor, two times of same internal self-checking calculations are required to be performed according to two self-checking sequences, the two times of same internal self-checking calculations are respectively completed in the main processor and the coprocessor, the coprocessor calculates a first calculation result, and the main processor calculates a second calculation result.
As shown in fig. 2, specifically, the self-test computation of the dual self-test polynomial includes the following steps:
in step S201, based on a first self-checking algorithm, a self-checking calculation is performed on a first self-checking sequence of the two self-checking sequences to obtain a first data set.
Specifically, the first self-test algorithm includes the following formula:
wherein, Xn,n＝0-9Representing a first data set, Mod representing a rounding calculation, Dn1Represents the set of self-test sequences in the first self-test sequence.
In step S202, based on a second self-checking algorithm, a second self-checking sequence of the two self-checking sequences is calculated by combining the first data group to obtain an internal self-checking calculation result, where the internal self-checking calculation result includes a first calculation result and a second calculation result.
Specifically, the second self-test algorithm comprises the following formula:
wherein, Yn,n＝0-9Indicating the result of the self-test calculation in the machine, Dn2Represents the set of self-test sequences in the second self-test sequence.
Specifically, the following tables 1 and 2 show the meaning of data in the first self-test sequence and the second self-test sequence, respectively:
TABLE 1 meanings of data in the first self-test sequence
TABLE 2 meanings of data in the second self-test sequence
In tables 1 and 2, the self-check sequence address offset is shown, and the self-check sequence is composed of a self-check period number, an inverse code of the self-check period number, a self-check sequence group (DATA0-DATA9), a check value (FCS check value), and reserved bytes.
When error detection and error correction DATA verification are performed, the verification range is self-checking period number, code reversal of self-checking period number, and self-checking sequence group (DATA0-DATA9), and generator polynomial X is adopted16+X12+X5+1, check.
As shown in fig. 1, in step S103, comparing the first calculation result with the second calculation result, and if the first calculation result is inconsistent with the second calculation result more than a preset number of times, determining that the operation of the main processor is abnormal.
Specifically, the main processor is heterogeneous with the coprocessor, the same double self-checking polynomial self-checking calculation is carried out through the same two self-checking sequences to obtain a second calculation result and a first calculation result, theoretically, the first calculation result is the same as the second calculation result, therefore, in the application, the main processor and the coprocessor carry out multiple calculations, the multiple calculated first calculation results are compared with the multiple second calculation results, if the multiple comparisons are completely the same, the main processor is indicated not to run abnormally, and abnormal marks are eliminated; if the inconsistency exceeds the preset times, the main processor is indicated to be abnormal in operation, and identification is needed.
In one embodiment, before step S101, the synchronization state and running state memories of the main processor and the coprocessor are initialized, and the state synchronization is performed on the main processor and the coprocessor. And if the state synchronization of the main processor and the coprocessor is unsuccessful, giving an operation exception identifier and ending.
Specifically, before monitoring and diagnosing the running state of the main processor, it is necessary to ensure that the main processor and the coprocessor are in a synchronous state, and if the states of the main processor and the coprocessor are not synchronous, running exception identification is performed.
The running state of the main processor is monitored and diagnosed by the coprocessor on the train, and the safety protection measures adopted meet the safety requirements of EN50159-2010 on a closed network. A coprocessor which is heterogeneous to a main processor is adopted on a hardware architecture, a group of self-checking polynomials are generated by utilizing a built-in self-checking method, the two heterogeneous processors respectively carry out calculation, and the final calculation result is compared to realize the monitoring and diagnosis functions. The reliability and the safety of the main processor are improved, so that the reliability and the safety of the whole system are improved.
Fig. 4 shows a memory area division schematic diagram of a dual port memory according to an embodiment of the invention.
As shown in FIG. 4, the overall data definition within the PU600 board is shown in FIG. 4. The memory area of the dual-port memory is divided into 4 parts, namely a reserved area, a data receiving and transmitting area (RS485 protocol/port transmission), a self-checking sequence number area and a BIT self-checking result area. Wherein, the reserved area 512Byte, the self-checking sequence number area 256Byte, and the BIT (built-in) self-checking result area 256 Byte.
Specifically, data in the diagnostic process is monitored by storing the operating state in a dual port memory connected to the main processor and the coprocessor. Four storage areas are divided in the dual-port memory, and are respectively two self-checking sequence storage areas generated by the coprocessor, a self-checking calculation result storage area in the machine, a data receiving and transmitting area and a reserved area which are calculated by the coprocessor and the main processor.
Further, the two self-checking sequence storage areas generated by the coprocessor, namely the first self-checking sequence and the second self-checking sequence in the self-checking sequence number area, respectively occupy 128 bytes, and the calculation results of the coprocessor and the main processor in the built-in self-checking calculation result storage area calculated by the coprocessor and the main processor, namely the BIT (built-in) self-checking result area, respectively occupy 128 bytes.
In one embodiment, the main processor reads two self-checking sequences from the coprocessor from the dual-port memory to perform double self-checking polynomial built-in self-checking calculation, writes an operation result into the DPRAM and compares the operation result with an operation result of the coprocessor in the DPRAM, gives an operation state of the main processor according to a comparison result, indicates that the main processor operates normally and continues processing in the next period if the comparison result is consistent, and indicates that the main processor operates abnormally and gives an abnormal state if the comparison result is inconsistent.
In the application, the data is stored through the dual-port memory, the efficiency and the accuracy of data transmission are ensured, the storage space of the dual-port memory is functionally divided, the efficiency is higher when data is called, received, sent and stored, and the efficiency of the main processor in the monitoring and diagnosing process is ensured.
FIG. 5 is a flow chart of a processor operating condition monitoring and diagnosing method according to another embodiment of the present invention.
As shown in fig. 5, after power-on, registers of the main processor and the coprocessor in the DPRAM are initialized, a synchronization state and a running state of the main processor and the coprocessor are initialized, then state synchronization of the main processor and the coprocessor is performed, and if synchronization is unsuccessful, an exception identifier is given and then the process is finished.
If the synchronization is successful, two self-checking sequences generated by the coprocessor are read from the dual-port memory after the preset time (35ms) is delayed, the built-in self-checking calculation result of the coprocessor, namely the first calculation result, is read, CRC (cyclic redundancy check) self-checking is carried out on the two read self-checking sequences in the main processor, the same built-in self-checking calculation is carried out, and a second calculation result is obtained and written into the dual-port memory.
Then, calculating and comparing the first calculation result and the second calculation result for multiple times (preset to be 3 times of comparison), and if the comparison results are inconsistent (exceed 3 times of inconsistency), setting a main processor operation exception identifier; and if the comparison result is consistent, clearing the running abnormity identifier of the main processor, delaying the preset time (15ms) and then entering the next monitoring diagnosis cycle.
Fig. 6 is a block diagram showing a configuration of a processor operation state monitoring and diagnosing apparatus according to an embodiment of the present invention.
As shown in fig. 6, the monitoring and diagnosing apparatus 600 includes a retrieving module 601, a calculating module 602, and a comparing module 603.
Specifically, the invoking module 601 is configured to read two self-checking sequences generated by the coprocessor through the main processor and perform a first calculation result obtained by performing a dual self-checking polynomial internal self-checking calculation according to the two self-checking sequences.
Specifically, the calculation module 602 is configured to perform error detection and error correction data verification on two self-test sequences generated by the coprocessor, and perform internal self-test calculation of a double self-test polynomial through the main processor after the verification is passed, so as to obtain a second calculation result.
Specifically, the comparing module 603 is configured to compare the first calculation result with the second calculation result, and determine that the main processor is abnormal when the first calculation result is inconsistent with the second calculation result more than a preset number of times.
In conclusion, the method and the device for monitoring and diagnosing the running state of the processor provided by the invention adopt two heterogeneous processors, and compared with a main processor, the coprocessor has lower cost and low requirement on other functions of the coprocessor, does not influence the normal running of a train and is easy to realize the monitoring and diagnosis on the main processor; the invention carries out built-in self-checking and adopts a cyclic redundancy check mode, is simple and efficient, is applied to the monitoring and diagnosis of the coprocessor of the train network control system on the main processor, and can improve the reliability and the safety of the main processor.
It is to be understood that the disclosed embodiments of the invention are not limited to the particular structures, process steps, or materials disclosed herein but are extended to equivalents thereof as would be understood by those ordinarily skilled in the relevant arts. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting.
Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "one embodiment" or "an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method for monitoring and diagnosing processor operating status, wherein a main processor is heterogeneous to a coprocessor, the method comprising the steps of:
the method comprises the following steps: reading two self-checking sequences generated by the coprocessor through the main processor and carrying out double self-checking polynomial built-in self-checking calculation according to the two self-checking sequences to obtain a first calculation result;
step two: performing error detection and error correction data verification on the two self-checking sequences generated by the coprocessor, and performing double self-checking polynomial built-in self-checking calculation through the main processor after the verification is passed to obtain a second calculation result;
step three: and comparing the first calculation result with the second calculation result, and if the first calculation result is inconsistent with the second calculation result and exceeds a preset number of times, judging that the main processor is abnormal in operation.
2. The method of claim 1, wherein the built-in self-test computation of the dual self-test polynomial comprises the steps of:
based on a first self-checking algorithm, performing self-checking calculation on a first self-checking sequence of the two self-checking sequences to obtain a first data group;
and calculating a second self-checking sequence in the two self-checking sequences by combining the first data group based on a second self-checking algorithm to obtain an internal self-checking calculation result, wherein the internal self-checking calculation result comprises the first calculation result and the second calculation result.
3. The method of claim 2, wherein the first self-test algorithm comprises the following formula:
wherein, Xn,n＝0-9Representing said first data set, Mod representing a rounding calculation, Dn1Represents the set of self-test sequences in the first self-test sequence.
4. A method according to claim 3, wherein the second self-test algorithm comprises the following equation:
wherein, Yn,n＝0-9Representing the result of said self-test calculation, Dn2Represents the set of self-test sequences in the second self-test sequence.
5. The method of claim 1, wherein both self-test sequences comprise a self-test period number, an inverse of the self-test period number, a set of self-test sequences, and a check value.
6. The method of claim 5 wherein said error detection and correction data check comprises the steps of:
and checking the read self-checking period number, the inverse code of the self-checking period number and the self-checking sequence group in the two self-checking sequences generated by the coprocessor by using a generating polynomial in a cyclic redundancy check mode through check values.
7. The method of claim 1, wherein the method comprises the steps of:
storing data in a running state monitoring diagnostic process through a dual-port memory connected with the main processor and the coprocessor;
four storage areas are divided in the dual-port memory, and are respectively two self-checking sequence storage areas generated by the coprocessor, a self-checking calculation result storage area in the machine, a data receiving and transmitting area and a reserved area which are calculated by the coprocessor and the main processor.
8. The method of claim 1, wherein prior to said first step, further comprising the steps of:
initializing the synchronous state and running state memories of the main processor and the coprocessor, and carrying out state synchronization on the main processor and the coprocessor.
9. The method of claim 8, wherein if the synchronization of the host processor and the coprocessor states is not successful, then ending with a running exception flag.
10. A processor operating state monitoring and diagnostic device, wherein a main processor is heterogeneous to a coprocessor, the device comprising:
the calling module is used for reading the two self-checking sequences generated by the coprocessor through the main processor and carrying out double self-checking polynomial built-in self-checking calculation according to the two self-checking sequences to obtain a first calculation result;
the calculation module is used for carrying out error detection and error correction data verification on the two self-checking sequences generated by the coprocessor, and carrying out double self-checking polynomial built-in self-checking calculation through the main processor after the verification is passed to obtain a second calculation result;
and the comparison module is used for comparing the first calculation result with the second calculation result, and if the first calculation result is inconsistent with the second calculation result and exceeds a preset number of times, judging that the operation of the main processor is abnormal.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114996021A (en) * | 2022-06-28 | 2022-09-02 | 慧之安信息技术股份有限公司 | Air defense auxiliary detection system based on edge calculation |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070300043A1 (en) * | 2006-06-27 | 2007-12-27 | Moyer William C | Method and apparatus for interfacing a processor and coprocessor |
| US20100174967A1 (en) * | 2009-01-07 | 2010-07-08 | Hitachi, Ltd. | Control apparatus and control method |
| US20120082307A1 (en) * | 2009-06-16 | 2012-04-05 | Morpho | Cryptography on a elliptical curve |
| CN107766188A (en) * | 2017-10-13 | 2018-03-06 | 交控科技股份有限公司 | Internal-memory detection method and device in train control system |
| CN108155619A (en) * | 2017-12-31 | 2018-06-12 | 长园深瑞继保自动化有限公司 | Protective relaying device multi-core CPU embedded system handles method and platform |
| CN109739703A (en) * | 2018-12-28 | 2019-05-10 | 北京中科寒武纪科技有限公司 | Adjust wrong method and Related product |
| CN110471790A (en) * | 2019-07-11 | 2019-11-19 | 北京交大微联科技有限公司 | The treating method and apparatus of computer equipment, product and its data task |
| CN110502380A (en) * | 2019-08-16 | 2019-11-26 | 兆讯恒达微电子技术(北京)有限公司 | A kind of method of hash algorithm coprocessor self-test |
| CN110502379A (en) * | 2019-08-16 | 2019-11-26 | 兆讯恒达微电子技术(北京)有限公司 | A kind of method of elliptic curve encryption algorithm coprocessor self-test |
| CN111142367A (en) * | 2018-11-02 | 2020-05-12 | 株洲中车时代电气股份有限公司 | Control system for railway safety application |
-
2020
- 2020-06-18 CN CN202010559583.7A patent/CN113821396A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070300043A1 (en) * | 2006-06-27 | 2007-12-27 | Moyer William C | Method and apparatus for interfacing a processor and coprocessor |
| US20100174967A1 (en) * | 2009-01-07 | 2010-07-08 | Hitachi, Ltd. | Control apparatus and control method |
| US20120082307A1 (en) * | 2009-06-16 | 2012-04-05 | Morpho | Cryptography on a elliptical curve |
| CN107766188A (en) * | 2017-10-13 | 2018-03-06 | 交控科技股份有限公司 | Internal-memory detection method and device in train control system |
| CN108155619A (en) * | 2017-12-31 | 2018-06-12 | 长园深瑞继保自动化有限公司 | Protective relaying device multi-core CPU embedded system handles method and platform |
| CN111142367A (en) * | 2018-11-02 | 2020-05-12 | 株洲中车时代电气股份有限公司 | Control system for railway safety application |
| CN109739703A (en) * | 2018-12-28 | 2019-05-10 | 北京中科寒武纪科技有限公司 | Adjust wrong method and Related product |
| CN110471790A (en) * | 2019-07-11 | 2019-11-19 | 北京交大微联科技有限公司 | The treating method and apparatus of computer equipment, product and its data task |
| CN110502380A (en) * | 2019-08-16 | 2019-11-26 | 兆讯恒达微电子技术(北京)有限公司 | A kind of method of hash algorithm coprocessor self-test |
| CN110502379A (en) * | 2019-08-16 | 2019-11-26 | 兆讯恒达微电子技术(北京)有限公司 | A kind of method of elliptic curve encryption algorithm coprocessor self-test |
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| CN114996021A (en) * | 2022-06-28 | 2022-09-02 | 慧之安信息技术股份有限公司 | Air defense auxiliary detection system based on edge calculation |
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