CN113821076A - Virtual simulation system and synchronization method based on virtual clock - Google Patents
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Abstract
The invention provides a virtual simulation system and a synchronization method based on a virtual clock, which comprises a plurality of virtual digital single machines and a time sequence synchronization center node; the virtual digital single machine is used for simulating the instruction execution of a hardware chip; the virtual digital single machine can calculate the running time of the virtual digital single machine under the virtual clock environment according to the simulated instruction machine period number; and the plurality of virtual digital single machines carry out time sequence synchronization through the time sequence synchronization center node. The invention can carry out grouping control according to different requirements, simultaneously solves the problem that running time sequences of different virtual digital single machines are not synchronous under a virtual clock, and greatly improves the reliability and the safety of the virtual simulation system.
Description
Technical Field
The invention relates to the field of virtual simulation system testing, in particular to a virtual simulation system based on a virtual clock and a synchronization method.
Background
In the virtual simulation system environment, a virtual digital single machine runs on a host machine, and simulated hardware chip instructions have different complexity, for example, the instruction set of a virtual digital single machine simulation DSP of the DSP comprises simple copying and moving instructions and complex floating point number calculation instructions, and the simulation of the instructions needs the virtual digital single machine to convert the instructions of the DSP into host machine codes and run on the host machine. Therefore, the number of simulated DSP instructions per unit time of the virtual digital single machine is determined by the machine performance of the host and the complexity of the instructions executed by the virtual digital single machine. The better the machine performance, the shorter the elapsed time; the more complex the execution of the instruction, the longer the time consumed.
The wall clock refers to the real time. The virtual clock refers to a virtual digital single machine, and the clock period number of the analog operation instruction is converted according to the analog chip frequency. For example, a DSP chip with a frequency of 200M theoretically runs 200K instructions for 1ms, and a virtual clock after conversion of 200K instructions is simulated for 1ms, but the wall time is not necessarily 1ms (related to the performance of the machine, and the complexity of the simulated instructions).
In summary, in the virtual simulation environment, the virtual digital single machines run on different host machines, and the number of instructions simulated by each virtual digital single machine is different within a certain wall time range, i.e., the virtual clocks are not synchronized, which brings about the problem that the simulation between the virtual digital single machines is not synchronized, which is fatal to the simulation system, and the simulation result is not consistent with the running result of the real device.
Therefore, in order to ensure the correctness of the operation of the virtual simulation system, a synchronization method is needed, so that each virtual digital single machine is synchronized on the virtual clock.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a virtual simulation system and a synchronization method based on a virtual clock.
The virtual simulation system based on the virtual clock comprises a plurality of different virtual digital single machines and a time sequence synchronous central node;
the virtual digital single machine is used for simulating the instruction execution of a hardware chip; the virtual digital single machine can calculate the running time of the virtual digital single machine under the virtual clock environment according to the simulated instruction machine period number;
and the plurality of virtual digital single machines carry out time sequence synchronization through the time sequence synchronization center node.
Preferably, the plurality of virtual digital masters are divided into a plurality of virtual digital master groups, and any one virtual digital master in each group can perform timing synchronization with other virtual digital masters in the group, or may form another group with other virtual digital masters, and perform timing synchronization with other digital masters in the group at a synchronization period of the group. .
Preferably, the virtual digital single machine sends the synchronization information to perform time sequence synchronization; the structure of the synchronization information includes a group synchronization code, a single machine synchronization code, and a synchronization period.
Preferably, the group synchronization code includes a group ID number and a synchronization discrimination code;
the group ID number is a 16-bit number and is a unique identifier in the virtual simulation system;
the synchronous discrimination code is obtained by performing OR operation on the single machine identification code in the same packet, and the length of the synchronous discrimination code is a power of 2.
Preferably, the standalone synchronization code comprises a standalone identification code and a synchronization identifier:
the single machine identification code is a single machine unique identifier in the same packet, and the data length is consistent with the length of the synchronous discrimination code;
after all the single machine identification codes in each group are subjected to OR operation, the single machine identification codes are used as synchronous distinguishing codes;
the synchronous mark is used for marking the synchronous state for the virtual digital single machine, and is divided into a synchronized state and an unsynchronized state.
Preferably, the synchronization period is obtained from a corresponding number of machine periods in the synchronization period in a virtual clock environment, and a conversion formula thereof is as follows: the machine cycle number n is the virtual clock cycle t, the operating frequency f of the chip.
Preferably, the timing synchronization is based on a synchronization feedback instruction, including a group ID number and a synchronization discrimination feedback code;
preferably, the time sequence synchronization center node is configured to receive the group synchronization code and the single-machine synchronization code sent by a single virtual digital machine, judge whether all the single virtual digital machines in the same group have been operated to a specified synchronization time point according to the group synchronization code and the single-machine synchronization code, and broadcast a synchronization feedback instruction of the group if all the single virtual digital machines in the same group have been operated to the specified synchronization time point.
The synchronization method of the virtual simulation system based on the virtual clock comprises the following steps:
step S1: initializing synchronous information of a virtual digital single machine, specifically, initializing a synchronous information list after the virtual digital single machine is electrified and operated in a virtual simulation system, configuring synchronous information, and setting a synchronous identifier in the synchronous information as 'unsynchronized';
step S2: performing synchronization processing through a virtual clock, specifically, calculating the number of simulated instruction machine cycles through a synchronization processing module of the virtual clock, traversing a synchronization information list, setting a synchronization identifier as unsynchronized when the calculated number of instruction cycles meets the synchronization cycle of a certain group, suspending the operation of a simulation instruction of a virtual digital single machine, sending a group synchronization code and a single machine synchronization code of the group to a time sequence synchronization center node, and waiting for the time sequence synchronization center node to send a synchronization feedback instruction;
step S3: and performing synchronization judgment, specifically, receiving a group synchronization code and a single machine synchronization code sent by the virtual digital single machines through a time sequence synchronization center node, performing or operating the received single machine synchronization code of the same group, judging whether the received single machine synchronization code is the same as the synchronization judgment code, and if the received single machine synchronization code is the same as the synchronization judgment code, operating all the virtual digital single machines of the group to a specified synchronization time point to complete synchronization, so that a synchronization feedback instruction is sent to each virtual digital single machine in a network broadcasting manner.
Step S4: and receiving a synchronous feedback instruction, specifically, receiving the synchronous feedback instruction by the virtual digital single machine through an independent process, judging whether the synchronous feedback instruction is a valid synchronous feedback instruction according to the group ID number, and updating the synchronous identifier in the synchronous information of the corresponding group to be synchronized if the group ID number of the synchronous feedback instruction is consistent with the group ID number in the synchronous information list.
Preferably, when the virtual digital stand-alone recognizes that the synchronization flag is updated to be synchronized, the emulation instruction of the virtual digital stand-alone is started again to run, and the synchronization flag is set to be not synchronized, and the steps S2 to S4 are repeatedly performed.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a method for synchronizing a virtual simulation system, which can perform grouping control according to different requirements, simultaneously solve the problem that running time sequences of different virtual digital single machines are not synchronous under a virtual clock, and greatly improve the reliability and safety of the virtual simulation system.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a schematic diagram of a virtual simulation system based on a virtual clock according to an embodiment of the present invention;
FIG. 2 is a diagram of a synchronization information format according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a format of a synchronous feedback command according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating an exemplary virtual digital desktop synchronization process according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating synchronization identification of a timing synchronization center node according to an embodiment of the present invention;
FIG. 6 is a flowchart of a synchronization method for a virtual simulation system based on a virtual clock according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that variations and modifications can be made by persons skilled in the art without departing from the spirit of the invention. All falling within the scope of the present invention.
In the embodiment of the invention, the virtual simulation system based on the virtual clock comprises a plurality of different virtual digital single machines and a time sequence synchronous central node;
the virtual digital single machine is used for simulating instruction execution of a hardware chip and simulating peripheral hardware simulation; the virtual digital single machine can calculate the running time of the virtual digital single machine under the virtual clock environment according to the simulated instruction machine period number.
And a plurality of the virtual digital single machines are synchronized in time sequence through a time sequence synchronization center node.
As shown in fig. 1, in the virtual simulation system, there are 4 virtual digital single machines, the numbers of which are 1-4, and the virtual digital single machine 1 and the virtual digital single machine 2 are divided into G1 groups, and the synchronization period is 1ms under the virtual clock. Virtual digital stand-alone 2, virtual digital stand-alone 3 and virtual digital stand-alone 4 are divided into G2 groups, and the synchronization period is 5ms under the virtual clock. Any one virtual digital single machine in each group can carry out timing synchronization with different periods with other virtual digital single machines in each group.
And the virtual digital single machine sends the synchronization information to carry out time sequence synchronization. The structure of the synchronization information includes a group synchronization code, a single synchronization code, and a synchronization period, as shown in fig. 2:
the group synchronization code comprises a group ID number and a synchronization discrimination code;
the group ID number is a 16-bit number and must be a unique identifier in the virtual simulation system;
the synchronous discrimination code is obtained by performing OR operation on a single machine identification code in the same packet, and the length of the synchronous discrimination code is generally a power of 2 such as 16 bits, 32 bits or 64 bits.
The single machine synchronous code comprises a single machine identification code and a synchronous identification:
the single machine identification code is the unique identification of the single machine in the same group, the unique identification cannot be repeated, and the data length is consistent with the length of the synchronous discrimination code. When the single machine identification code is converted into binary code, 1 can only appear once in the code, and the rest are all 0. After all the single machine identification codes in each group are subjected to OR operation, the single machine identification codes are used as synchronous distinguishing codes;
the synchronous mark is used for marking the synchronous state for the virtual digital single machine, and is divided into a synchronized state and an unsynchronized state.
The synchronization period is obtained from the corresponding machine period number in the synchronization period under the virtual clock environment, and the conversion formula is as follows: the machine cycle number n is the virtual clock cycle t, the operating frequency f of the chip.
The timing synchronization is based on a synchronization feedback instruction. The synchronization feedback command includes a group ID number and a synchronization decision feedback code, as shown in fig. 3.
The time sequence synchronization method is based on a time sequence synchronization center node, wherein the time sequence synchronization center node is responsible for receiving the group synchronization code and the single machine synchronization code sent by the virtual digital single machine, judging whether the synchronization information of the same group is received according to the group synchronization code and the single machine synchronization code, and broadcasting and sending the synchronization feedback instruction of the group if the synchronization information of the same group is received.
Fig. 6 is a flowchart of a synchronization method of a virtual simulation system based on a virtual clock in an embodiment of the present invention, and as shown in fig. 6, the synchronization method includes the following steps:
step S1: initializing synchronous information of a virtual digital single machine, specifically, initializing a synchronous information list after the virtual digital single machine is electrified and operated in a virtual simulation system, configuring synchronous information, and setting a synchronous identifier in the synchronous information as 'unsynchronized';
step S2: performing synchronization processing through a virtual clock, specifically, calculating the number of simulated instruction machine cycles through a synchronization processing module of the virtual clock, traversing a synchronization information list, setting a synchronization identifier as unsynchronized when the calculated number of instruction cycles meets the synchronization period of a certain group, suspending the operation of a simulation instruction of a virtual digital single machine, sending a group synchronization code and a single machine synchronization code of the group to a time sequence synchronization center node, and waiting for the time sequence synchronization center node to send a synchronization feedback instruction until the synchronization identifier is updated to be synchronized;
step S3: and (4) carrying out synchronization judgment, specifically, receiving the group synchronization code and the single machine synchronization code sent by the virtual digital single machine through the time sequence synchronization center node. And carrying out OR operation on the received single machine synchronization codes of the same group to judge whether the received single machine synchronization codes are the same as the synchronization judgment codes, and if the received single machine synchronization codes are the same as the synchronization judgment codes, indicating that all the virtual digital single machines of the group have operated to the appointed synchronization time point to complete synchronization, so that a synchronization feedback instruction is sent to each virtual digital single machine in a network broadcasting mode.
Step S4: and receiving a synchronous feedback instruction, specifically, receiving the synchronous feedback instruction by the virtual digital single machine through an independent process, judging whether the synchronous feedback instruction is a valid synchronous feedback instruction according to the group ID number, and updating the synchronous identifier in the synchronous information of the corresponding group to be synchronized if the group ID number of the synchronous feedback instruction is consistent with the group ID number in the synchronous information list.
When the virtual digital single machine recognizes that the synchronization identifier is updated to be synchronized, the simulation instruction of the virtual digital single machine is started again to operate, and the synchronization identifier is set to be not synchronized.
Steps S2 to S4 are repeatedly performed.
In the embodiment of the present invention, in the G1 grouping, the virtual digital single machine 1 is: group ID number 1; the synchronization discrimination code is 0x 3; the stand-alone identification code is 0x 1. The virtual digital single machine 2 in the G1 grouping is: group ID number 1; the synchronization discrimination code is 0x 3; the stand-alone identification code is 0x 2.
In the G2 grouping, virtual digital stand-alone 2 is: group ID number 2; and (3) synchronous discrimination code: 0x 7; a stand-alone identification code 0x 1; the virtual digital single machine 3 is: group ID number 2; and (3) synchronous discrimination code: 0x 7; a stand-alone identification code 0x 2; the virtual digital single machine 4 is: group ID number 2; and (3) synchronous discrimination code: 0x 7; the stand-alone identification code 0x 4.
As shown in fig. 4, the synchronization process flow of the virtual digital single machine 1 is as follows:
setting or reading the synchronous information through a configuration file;
the synchronization processing module of the virtual clock judges whether the virtual clock runs to a 1ms virtual clock synchronization point, namely whether the number of machine cycles reaches a value set in a synchronization cycle, if not, the instruction simulation is continued; if so, sending the synchronization information of the G1 group to the timing synchronization central node, and stopping instruction simulation operation;
receiving a synchronization feedback instruction in another thread, and setting the synchronization identifier of the G1 group as synchronized after receiving the synchronization feedback instruction of the G1 group;
and waiting and judging the synchronization identifier of the G1 group, and clearing the G1 group synchronization identifier (set to be not synchronized) if the synchronization identifier marks that the synchronization is synchronized, and resuming the instruction simulation operation.
As shown in fig. 4, the synchronization process flow of the virtual digital stand-alone 3 and the digital stand-alone 4 is as follows:
setting or reading the synchronous information through a configuration file;
the virtual clock synchronization processing module judges whether a 5ms virtual clock synchronization point is operated (whether the machine period number count reaches a value set in a synchronization period), and if not, instruction simulation is continued; if so, sending the synchronization information of the G2 group to the timing synchronization central node, and stopping instruction simulation operation;
receiving a synchronization feedback instruction in another thread, and setting the synchronization identifier of the G2 group as synchronized after receiving the synchronization feedback instruction of the G2 group;
and waiting and judging the synchronization identifier of the G2 group, and if the synchronization identifier is marked as synchronized, clearing the G2 group synchronization identifier and setting the synchronization identifier as not synchronized, and resuming the instruction simulation operation.
As shown in fig. 4, the synchronization process flow of the virtual digital single machine 2 is as follows:
setting or reading the synchronous information through a configuration file;
the virtual clock synchronization processing module judges whether a 1ms virtual clock synchronization point is operated, namely whether the number of machine cycles reaches a value set in a synchronization cycle, if so, the virtual clock synchronization processing module sends G1 group synchronization information to the time sequence synchronization central node and stops instruction simulation operation; if not, the judgment is continued to be carried out to the 5ms virtual clock synchronization point. If not, performing instruction simulation; if so, sending the synchronization information of the G2 group to the timing synchronization central node, and stopping instruction simulation operation;
receiving a synchronization feedback instruction in another thread, and setting synchronization marks of the groups G1 and G2 as synchronized after receiving the synchronization feedback instructions of the groups G1 and G2;
and waiting and judging the synchronization identifier of the G1 group, and if the synchronization identifier is marked as synchronized, clearing the G1 group synchronization identifier and setting the synchronization identifier as not synchronized, and resuming the instruction simulation operation.
And waiting and judging the synchronization identifier of the G2 group, and if the synchronization identifier is marked as synchronized, clearing the G2 group synchronization identifier and setting the synchronization identifier as not synchronized, and resuming the instruction simulation operation.
As shown in fig. 5, the processing flow of the timing synchronization center node is as follows:
receiving synchronous information sent by a virtual digital single machine in a virtual simulation system;
calculating a synchronization discrimination feedback code of the G1 group;
and judging whether the G1 group synchronization judging feedback code is consistent with the G1 group synchronization judging code (after calculation, if so, all the synchronization information of the group is received), and if so, broadcasting a G1 group synchronization feedback instruction to the virtual simulation system.
Similarly, the judgment feedback codes of the G2 group are calculated, whether the synchronization judgment feedback codes of the G2 group are consistent with the synchronization judgment codes of the G2 group is judged, and if so, the synchronization feedback instructions of the G2 group are broadcasted to the virtual simulation system.
As shown in fig. 5, after the virtual digital single machine in the virtual simulation system receives the synchronization feedback instruction, the synchronization identifier of the corresponding group is set to be synchronized according to the group ID number in the synchronization feedback instruction.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes and modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention.
Claims (10)
1. A virtual simulation system based on a virtual clock is characterized by comprising a plurality of virtual digital single machines and a time sequence synchronous central node;
the virtual digital single machine is used for simulating the instruction execution of a hardware chip; the virtual digital single machine can calculate the running time of the virtual digital single machine under the virtual clock environment according to the simulated instruction machine period number;
and the plurality of virtual digital single machines carry out time sequence synchronization through the time sequence synchronization center node.
2. The virtual clock-based simulation system according to claim 1, wherein the virtual digital masters are divided into a plurality of virtual digital master groups, and any one virtual digital master in each group can perform timing synchronization with other virtual digital masters in the group, or can form another group with other virtual digital masters, and perform timing synchronization with other digital masters in the group at a synchronization cycle of the group.
3. The virtual clock-based virtual simulation system of claim 1, wherein the virtual digital standalone sends timing synchronization through synchronization information; the structure of the synchronization information includes a group synchronization code, a single machine synchronization code, and a synchronization period.
4. The virtual clock-based simulation system of claim 3, wherein the group synchronization code comprises a group ID number and a synchronization discrimination code;
the group ID number is a 16-bit number and is a unique identifier in the virtual simulation system;
the synchronous discrimination code is obtained by performing OR operation on the single machine identification code in the same packet, and the length of the synchronous discrimination code is a power of 2.
5. The virtual clock-based simulation system of claim 3, wherein the stand-alone synchronization code comprises a stand-alone identification code and a synchronization identification:
the single machine identification code is a single machine unique identifier in the same packet, and the data length is consistent with the length of the synchronous discrimination code;
after all the single machine identification codes in each group are subjected to OR operation, the single machine identification codes are used as synchronous distinguishing codes;
the synchronous mark is used for marking the synchronous state for the virtual digital single machine, and is divided into a synchronized state and an unsynchronized state.
6. The virtual clock-based simulation system according to claim 3, wherein the synchronization cycle is obtained from the corresponding number of machine cycles in the synchronization cycle in the virtual clock environment, and the conversion formula is as follows: the machine cycle number n is the virtual clock cycle t, the operating frequency f of the chip.
7. The virtual clock-based simulation system of claim 3, wherein the timing synchronization is based on a synchronization feedback instruction, including a group ID number and a synchronization discrimination feedback code.
8. The virtual simulation system according to claim 7, wherein the time sequence synchronization center node is configured to receive the group synchronization code and the single-machine synchronization code sent by a single virtual digital machine, determine whether all the single virtual digital machines in the same group have been operated to a specified synchronization time point according to the group synchronization code and the single-machine synchronization code, and broadcast a synchronization feedback instruction for sending the group if all the single virtual digital machines have been operated to the specified synchronization time point.
9. A synchronization method of a virtual simulation system based on a virtual clock is characterized by comprising the following steps:
step S1: initializing synchronous information of a virtual digital single machine, specifically, initializing a synchronous information list after the virtual digital single machine is electrified and operated in a virtual simulation system, configuring synchronous information, and setting a synchronous identifier in the synchronous information as 'unsynchronized';
step S2: performing synchronization processing through a virtual clock, specifically, calculating the number of simulated instruction machine cycles through a synchronization processing module of the virtual clock, traversing a synchronization information list, setting a synchronization identifier as unsynchronized when the calculated number of instruction cycles meets the synchronization cycle of a certain group, suspending the operation of a simulation instruction of a virtual digital single machine, sending a group synchronization code and a single machine synchronization code of the group to a time sequence synchronization center node, and waiting for the time sequence synchronization center node to send a synchronization feedback instruction;
step S3: performing synchronization judgment, specifically, receiving a group synchronization code and a single-machine synchronization code sent by the virtual digital single machine through a time sequence synchronization center node, performing or operating the received single-machine synchronization code of the same group, judging whether the received single-machine synchronization code is the same as the synchronization judgment code, if so, operating all the virtual digital single machines of the group to a specified synchronization time point, and completing synchronization, so that a synchronization feedback instruction is sent to each virtual digital single machine in a network broadcasting manner;
step S4: and receiving a synchronous feedback instruction, specifically, receiving the synchronous feedback instruction by the virtual digital single machine through an independent process, judging whether the synchronous feedback instruction is a valid synchronous feedback instruction according to the group ID number, and updating the synchronous identifier in the synchronous information of the corresponding group to be synchronized if the group ID number of the synchronous feedback instruction is consistent with the group ID number in the synchronous information list.
10. The method for synchronizing a virtual simulation system according to claim 9, wherein when the virtual digital stand-alone recognizes that the synchronization flag is updated to be synchronized, the simulation instruction of the virtual digital stand-alone is started again to run, the synchronization flag is set to be not synchronized, and the steps S2 to S4 are repeatedly performed.
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