CN113810070B

CN113810070B - Signal transmission device capable of transmitting multiple groups of data streams

Info

Publication number: CN113810070B
Application number: CN202010848379.7A
Authority: CN
Inventors: 李安明; 黄柏凯
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2020-06-17
Filing date: 2020-08-21
Publication date: 2023-01-10
Anticipated expiration: 2040-08-21
Also published as: TW202201913A; TW202201955A; TWD213975S; TWI763001B; TWD213974S; TWD213336S; TWI788808B; TWD213338S; TWD218601S; CN113810070A; CN113809596A; TWD213337S; TWD218600S; TWD213973S

Abstract

The present disclosure provides a signal transmission device including a plurality of positive differential pins, a plurality of negative differential pins, a plurality of ground pins, a plurality of power signal pins, and a plurality of control signal pins. A first positive differential pin of the plurality of positive differential pins transmits a positive signal component of the first differential signal, and a second positive differential pin of the plurality of positive differential pins transmits a positive signal component of the second differential signal; a first negative differential pin of the plurality of negative differential pins transmits a negative signal component of the first differential signal, and a second negative differential pin of the plurality of negative differential pins transmits a negative signal component of the second differential signal; the first positive differential pin and the first negative differential pin are located on one side of a first ground pin of the plurality of ground pins, and the second positive differential pin and the second negative differential pin are located on the other side of the first ground pin.

Description

Signal transmission device capable of transmitting multiple data streams

Technical Field

The invention relates to a signal transmission device capable of transmitting a plurality of groups of data streams.

Background

As the quality of video playback screens is required to be higher, the original 4K resolution is increased to 8K resolution, and thus the amount of data transmission from a player as a Signal Source to a display as a Signal Sink increases. Moreover, due to the rise of home theaters, a longer transmission line is often required to connect the signal generation source and the signal receiving end, so as to meet the requirements of various living rooms.

In the current signal transmission device specification, if the Ground Shielding (Ground Shielding) regarded as important for the differential signal is not the best planning way in terms of the definition of the pin position, the signal quality when transmitting the high-speed signal is easily affected by Crosstalk (Crosstalk) and Delay (Delay), and the signal is difficult to be transmitted to a long distance.

Disclosure of Invention

In some embodiments, a signal transmission device includes a plurality of positive differential pins, a plurality of negative differential pins, a plurality of ground pins, a plurality of power signal pins, and a plurality of control signal pins. A first positive differential pin of the plurality of positive differential pins is used for transmitting a positive signal component of the first differential signal, and a second positive differential pin of the plurality of positive differential pins is used for transmitting a positive signal component of the second differential signal; a first negative differential pin of the plurality of negative differential pins is used for transmitting a negative signal component of the first differential signal, and a second negative differential pin of the plurality of negative differential pins is used for transmitting a negative signal component of the second differential signal; the first positive differential pin and the first negative differential pin are located on one side of a first grounding pin in the plurality of grounding pins, and the second positive differential pin and the second negative differential pin are located on the other side of the first grounding pin.

Drawings

Fig. 1 is a schematic diagram of an embodiment of a signal transmission apparatus according to the present disclosure.

Fig. 2 is a schematic diagram of another embodiment of the signal transmission device of fig. 1.

Fig. 3 is a schematic diagram of an embodiment of a pin arrangement of a signal transmission device according to the present disclosure.

Fig. 4 is a schematic diagram of an embodiment of a pin arrangement of a signal transmission device according to the present disclosure.

Fig. 5A is an external view of an embodiment of a female connector of a signal transmission device according to the disclosure.

Fig. 5B is an external view of an embodiment of a male connector of the signal transmission device corresponding to fig. 5A.

Fig. 5C is a side view of the signal transmission device of fig. 5A according to an embodiment.

FIG. 5D is a schematic side view of the signal transmission device of FIG. 5B according to an embodiment.

Fig. 6A is a side view schematic diagram of another embodiment of a female connector of a signal transmission device according to the present disclosure.

Fig. 6B is a schematic side view of another embodiment of a male connector of the signal transmission device corresponding to fig. 6A.

Fig. 7A is a side view schematic diagram of another embodiment of a female connector of a signal transmission device according to the present disclosure.

Fig. 7B is a schematic side view of another embodiment of a male connector of the signal transmission device corresponding to fig. 7A.

Fig. 8 is a schematic diagram of an embodiment of a transmission line and an electronic device including a signal transmission device according to the present disclosure.

Fig. 9 is a schematic diagram of another embodiment of a signal transmission device according to the present disclosure.

Fig. 10 is a schematic diagram of another embodiment of the signal transmission device of fig. 9.

Description of the symbols

111: first positive differential pin

112: first negative differential pin

121: second positive differential pin

122: second negative differential pin

131: third positive differential pin

132: third negative differential pin

141: fourth positive differential pin

142: fourth negative differential pin

151: first positive differential high-speed pin

152: first negative differential high-speed pin

161: second positive differential high speed pin

162: second negative differential high-speed pin

171: seventh positive differential pin

172: seventh negative differential pin

181: eighth positive differential pin

182: eighth negative differential pin

191: ninth positive differential pin

192: ninth negative differential pin

101: tenth positive differential pin

102: tenth negative differential pin

21: first grounding pin

22: second grounding pin

23: third grounding pin

24: fourth grounding pin

25: fifth grounding pin

26: sixth ground pin

27: seventh ground pin

28: eighth ground pin

29: ninth ground pin

20: tenth ground pin

31: power signal pin

32: power signal pin

33: power signal pin

34: power signal pin

410: system main power supply pin

411: hot plug detection pin

412: SDA/PCIE _ PERST _ N pin

413: CLK pin

414: SCL/PCIE _ WAKE _ N pin

415: ARC/SPDIF pin

416: SPI _ DI pin

417: SPI _ CS Pin

418: SPI _ CLK pin

419: REALONE _ SCL pin

420: REALONE _ SDA pin

421: SPI _ WP _ PWM pin

422: SPI _ HOLD _ PWM pin

423: SPI _ DO pin

51: positive differential low-speed pin

52: negative differential low-speed pin

61: power grounding pin

62: power grounding pin

I: insulating layer

M: metal barrier layer

D1: direction of rotation

D2: direction of rotation

G1: wire rod

G2: wire rod

G3: wire rod

G4: wire rod

And SA: one side of

SB: one side of

A: terminal end

A': terminal end

B: terminal end

B': terminal end

C: terminal end

C': terminal end

D: terminal end

D': terminal end

E: terminal end

E': terminal end

F: terminal end

F': terminal end

P: signal transmission device

Q: signal transmission device

R: signal transmission device

L: connecting part

N: electronic device

Detailed Description

Referring to fig. 1, fig. 1 is a schematic diagram of a signal transmission device according to an embodiment of the disclosure. The signal transmission device comprises a plurality of positive differential pins (Pin), a plurality of negative differential pins, a plurality of control signal pins, a plurality of power signal pins and a plurality of grounding pins. The number of the positive differential pins, the number of the negative differential pins, the number of the ground pins, the number of the power signal pins, and the number of the control signal pins may be customized according to different product requirements (e.g., required current, signal transmission rate), fig. 1 is only one embodiment of the signal transmission apparatus, and the disclosure is not limited thereto.

Fig. 1 illustrates a plurality of positive

differential pins

111, 121, 131, 141, a plurality of negative

differential pins

112, 122, 132, 142, and a plurality of ground pins (GND) 21-25 corresponding to the respective

differential pins

111, 112, 121, 122, 131, 132, 141, 142. The positive

differential pins

111, 121, 131, 141 and the negative

differential pins

112, 122, 132, 142 respectively transmit positive signal components and negative signal components of differential signals, and the positive differential pins 111, 121 (for convenience of description, referred to as the first positive differential pin 111 and the second positive differential pin 121, respectively), the negative differential pins 112, 122 (referred to as the first negative differential pin 112 and the second negative differential pin 122, respectively), and the corresponding ground pin 21 (hereinafter referred to as the first ground pin 21) are exemplified.

The first positive differential pin 111 and the first negative differential pin 112 transmit a first differential signal, wherein the first positive differential pin 111 transmits a positive signal component of the first differential signal, and the first negative differential pin 112 transmits a negative signal component of the first differential signal; the second positive differential pin 121 and the second negative differential pin 122 transmit another differential signal (hereinafter, referred to as a second differential signal) different from the first differential signal, the second positive differential pin 121 transmits a positive signal component of the second differential signal, and the second negative differential pin 122 transmits a negative signal component of the second differential signal. In configuration, the first positive differential pin 111 and the first negative differential pin 112 are located on one side of the first ground pin 21 (i.e., the two

differential pins

111 and 112 transmitting the same differential signal are located on the same side of the first ground pin 21), and the second positive differential pin 121 and the second negative differential pin 122 are located on the other side of the first ground pin 21 (i.e., the two

differential pins

121 and 122 transmitting the same differential signal are located on the same side of the first ground pin 21), i.e., the two

differential pins

111 and 122 transmitting different differential signals are located on different sides of the first ground pin 21.

Further, FIG. 1 illustrates four power signal pins 31-34 and a plurality of control signal pins. The power signal pins 31-34 can transmit power signals meeting specific communication specifications, and the control signal pins can transmit control signals meeting specific communication specifications. Therefore, different from the conventional signal transmission device, the signal transmission device of the present disclosure can avoid crosstalk (crosstalk) between different differential signals when transmitting the first differential signal and the second differential signal, and obtain better impedance matching characteristics, thereby improving the transmission quality of the signal transmission device and more efficiently transmitting signals to the electronic device.

In some embodiments, as shown in fig. 1, the signal transmission device may transmit at least four pairs of differential signals, the third positive differential pin 131 and the third negative differential pin 132 may transmit the third differential signal, the third positive differential pin 131 may transmit a positive signal component of the third differential signal, the third negative differential pin 132 may transmit a negative signal component of the third differential signal, the fourth positive differential pin 141 and the fourth negative differential pin 142 may transmit the fourth differential signal, the fourth positive differential pin 141 may transmit a positive signal component of the fourth differential signal, and the fourth negative differential pin 142 may transmit a negative signal component of the fourth differential signal. In order to prevent the four pairs of differential signals from interfering with each other, as shown in fig. 1, the plurality of ground pins of the signal transmission device are a first ground pin 21, a second ground pin 22, a third ground pin 23, a fourth ground pin 24, and a fifth ground pin 25. The second positive differential pin 121 and the second negative differential pin 122 are located between the first ground pin 21 and the fourth ground pin 24, that is, the second positive differential pin 121 and the second negative differential pin 122 are located on one side of the fourth ground pin 24, and the third positive differential pin 131 and the third negative differential pin 132 are located on the other side of the fourth ground pin 24; the third positive differential pin 131 and the third negative differential pin 132 are located between the fourth ground pin 24 and the fifth ground pin 25, that is, the third positive differential pin 131 and the third negative differential pin 132 are located on one side of the fifth ground pin 25, and the fourth positive differential pin 141 and the fourth negative differential pin 142 are located on the other side of the fifth ground pin 25. Therefore, the second positive differential pin 121 and the third negative differential pin 132 are shielded by the fourth ground pin 24, the third positive differential pin 131 and the fourth negative differential pin 142 are shielded by the fifth ground pin 25, and the first differential signal, the second differential signal, the third differential signal and the fourth differential signal do not interfere with each other.

In some embodiments, the positive

differential pins

111, 121, 131, 141 and the negative

differential pins

112, 122, 132, 142 are arranged along the same straight direction D1 (e.g., the length direction of the signal transmission device), and the signal transmission device can be more easily compatible with the existing communication transmission specifications.

In some embodiments, referring to fig. 2, fig. 2 is a schematic diagram of another embodiment of the signal transmission device of fig. 1, the signal transmission device may also include eight pairs of differential pins, and each pair of differential pins for transmitting the same differential signal is shielded by two ground pins. The signal transmission device also includes positive

differential pins

171, 181, 191, 101 (hereinafter referred to as a seventh positive differential pin 171, an eighth positive differential pin 181, a ninth positive differential pin 191, and a tenth positive differential pin 101, respectively), negative

differential pins

172, 182, 192, 102 (hereinafter referred to as a seventh negative differential pin 172, an eighth negative differential pin 182, a ninth negative differential pin 192, and a tenth negative differential pin 102, respectively), and corresponding ground pins 26, 27, 28, 29. The positive

differential pins

171, 181, 191, 101 and the negative

differential pins

172, 182, 192, 102 are also arranged along the same straight direction D1. The seventh positive differential pin 171 and the seventh negative differential pin 172 may transmit a seventh differential signal, the seventh positive differential pin 171 transmits a positive signal component of the seventh differential signal, and the seventh negative differential pin 172 transmits a negative signal component of the seventh differential signal. The eighth positive differential pin 181 and the eighth negative differential pin 182 may transmit an eighth differential signal, the eighth positive differential pin 181 may transmit a positive signal component of the eighth differential signal, and the eighth negative differential pin 182 may transmit a negative signal component of the eighth differential signal. The ninth positive differential pin 191 and the ninth negative differential pin 192 may transmit a ninth differential signal, the ninth positive differential pin 191 transmits a positive signal component of the ninth differential signal, and the ninth negative differential pin 192 transmits a negative signal component of the ninth differential signal. The tenth positive differential pin 101 and the tenth negative differential pin 102 may transmit a tenth differential signal, the tenth positive differential pin 101 transmits a positive signal component of the tenth differential signal, and the tenth negative differential pin 102 transmits a negative signal component of the tenth differential signal.

In order to prevent the above-mentioned eight differential signals from interfering with each other, as shown in fig. 2, the fourth positive differential pin 141 and the fourth negative differential pin 142 are located between the fifth ground pin 25 and the sixth ground pin 26, that is, the fourth positive differential pin 141 and the fourth negative differential pin 142 are located on one side of the sixth ground pin 26, and the seventh positive differential pin 171 and the seventh negative differential pin 172 are located on the other side of the sixth ground pin 26; the seventh positive differential pin 171 and the seventh negative differential pin 172 are located between the sixth ground pin 26 and the seventh ground pin 27, that is, the seventh positive differential pin 171 and the seventh negative differential pin 172 are located on one side of the seventh ground pin 27, and the eighth positive differential pin 181 and the eighth negative differential pin 182 are located on the other side of the seventh ground pin 27; the eighth positive differential pin 181 and the eighth negative differential pin 182 are located between the seventh ground pin 27 and the eighth ground pin 28, that is, the eighth positive differential pin 181 and the eighth negative differential pin 182 are located on one side of the eighth ground pin 28, and the ninth positive differential pin 191 and the ninth negative differential pin 192 are located on the other side of the eighth ground pin 28; the ninth positive differential pin 191 and the ninth negative differential pin 192 are located between the eighth ground pin 28 and the ninth ground pin 29, that is, the ninth positive differential pin 191 and the ninth negative differential pin 192 are located on one side of the ninth ground pin 29, and the tenth positive differential pin 101 and the tenth negative differential pin 102 are located on the other side of the ninth ground pin 29. Therefore, the fourth positive differential pin 141 and the seventh negative differential pin 172 are shielded by the sixth ground pin 26, the seventh positive differential pin 171 and the eighth negative differential pin 182 are shielded by the seventh ground pin 27, the eighth positive differential pin 181 and the ninth negative differential pin 192 are shielded by the eighth ground pin 28, the ninth positive differential pin 191 and the tenth negative differential pin 102 are shielded by the ninth ground pin 29, and the first differential signal, the second differential signal, the third differential signal, the fourth differential signal, the seventh differential signal, the eighth differential signal, the ninth differential signal and the tenth differential signal do not interfere with each other. Therefore, the signal transmission device can transmit at least eight pairs of differential signals, and the eight pairs of differential pins are arranged along the same linear direction D1, so that the signal transmission device can be more easily compatible with the existing communication transmission specification.

In some embodiments, as shown in fig. 1 and fig. 2, one side of the third ground pin 23 (i.e., the side far from the first negative differential pin 112) of the plurality of ground pins may be provided with the power signal pins 31 and 32 without the positive differential pin and the negative differential pin, and the other side of the third ground pin 23 is the first positive differential pin 111 and the first negative differential pin 112, i.e., the first positive differential pin 111 and the first negative differential pin 112 are located between the first ground pin 21 and the third ground pin 23, the first positive differential pin 111 and the first negative differential pin 112 are shielded by the two ground pins 21 and 23, and the ground pins 21 and 23 may collectively provide the first differential signal ground. Therefore, the third ground pin 23 separates the first positive differential pin 111 and the first negative differential pin 112 from the plurality of power signal pins 31 and 32, so that the first positive differential pin 111 and the first negative differential pin 112 are prevented from being interfered by the power signal when transmitting the first differential signal, and the transmission quality of the first differential signal is prevented from being reduced.

In some embodiments, as shown in fig. 2, the second ground pin 22 is located at an edge-most position of the signal transmission device, that is, one side of the second ground pin 22 in the linear direction D1 is not provided with the positive differential pin and the negative differential pin, and the other side of the second ground pin 22 in the linear direction D1 is the tenth positive differential pin 101 and the tenth negative differential pin 102. That is, the tenth positive differential pin 101 and the tenth negative differential pin 102 are located between the ninth ground pin 29 and the second ground pin 22, and the tenth positive differential pin 101 and the tenth negative differential pin 102 are shielded by the two ground pins 29 and 22, that is, the ground pins 29 and 22 can provide the tenth differential signal ground together. Therefore, the situation that the transmission quality of the tenth differential signal is reduced due to the fact that the tenth positive differential pin 101 and the tenth negative differential pin 102 are interfered by noise outside the signal transmission device when the tenth differential signal is transmitted can be further avoided.

In some embodiments, as shown in fig. 2, the differential pins of the signal transmission device also include two positive

differential pins

151 and 161 and two negative differential pins 152 and 162 (hereinafter, the positive

differential pins

151 and 161 are referred to as a first positive differential high-speed pin 151 and a second positive differential high-speed pin 161, respectively, and the negative

differential pins

152 and 162 are referred to as a first negative differential high-speed pin 152 and a second negative differential high-speed pin 162, respectively), and the ground pins of the signal transmission device also include a tenth ground pin 20. The first positive differential high-speed pin 151 is configured to transmit a positive signal component of the fifth differential signal, and the first negative differential high-speed pin 152 is configured to transmit a negative signal component of the fifth differential signal; the second positive differential high-speed pin 161 is used for transmitting a positive signal component of the sixth differential signal, and the second negative differential high-speed pin 162 is used for transmitting a negative signal component of the sixth differential signal. In configuration, the first positive differential high-speed pin 151 and the first negative differential high-speed pin 152 are located on one side of the tenth ground pin 20, the second positive differential high-speed pin 161 and the second negative differential high-speed pin 162 are located on the other side of the tenth ground pin 20, and the positive differential high-

speed pins

151, 161, the tenth ground pin 20 and the negative differential high-

speed pins

152, 162 are arranged along the same straight direction D1.

In some embodiments, the positive differential pins and the negative differential pins of the signal transmission device are used for transmitting high-speed data signals, for example, the first differential signal transmitted by the

differential pins

111 and 112, the second differential signal transmitted by the

differential pins

121 and 122, the third differential signal transmitted by the

differential pins

131 and 132, the fourth differential signal transmitted by the

differential pins

141 and 142, the seventh differential signal transmitted by the

differential pins

171 and 172, the eighth differential signal transmitted by the

differential pins

181 and 182, the ninth differential signal transmitted by the

differential pins

191 and 192, the tenth differential signal transmitted by the

differential pins

101 and 102, the fifth differential signal transmitted by the differential high-

speed pins

151 and 152, and the sixth differential signal transmitted by the differential high-

speed pins

161 and 162 are all high-speed data signals. As shown in fig. 1 and 2, the signal transmission device may further include a positive differential low-speed pin 51 and a negative differential low-speed pin 52 for transmitting low-speed data signals, and the positive differential low-speed pin 51 and the negative differential low-speed pin 52 are arranged along the same straight direction D1 as the differential high-

speed pins

151, 152, 161, and 162. The positive differential low-speed pin 51 and the negative differential low-speed pin 52 transmit a low-speed differential signal as low-speed data, the positive differential low-speed pin 51 transmits a positive signal component of the low-speed differential signal, and the negative differential low-speed pin 52 transmits a negative signal component of the low-speed differential signal. Therefore, the signal transmission device can simultaneously support the transmission of high-speed data signals and low-speed data signals.

In some embodiments, the signal transmission apparatus illustrated in fig. 1 to 2 may support a Universal Serial Bus (USB) 2.0 specification, the positive differential low-speed pin 51 and the negative differential low-speed pin 52 are suitable for the USB2.0 specification, the low-speed differential signals transmitted by the positive differential low-speed pin 51 and the negative differential low-speed pin 52 are USB signals of USB2.0, the positive differential low-speed pin 51 may transmit USB-DP signals, and the negative differential low-speed pin 52 may transmit USB-DM signals. Furthermore, the signal transmission device illustrated in fig. 2 can also support various specifications using differential transmission methods, and any two pairs of the positive differential pins and the negative differential pins (i.e., the

differential pins

111, 112, 121, 122, 131, 132, 141, 142, 171, 172, 181, 182, 191, 192, 101, 102 and the differential high-

speed pins

151, 152, 161, 162) of the signal transmission device for transmitting high-speed data signals can transmit high-speed data transmission and reception signals conforming to USB2.0 or PCIe 1.0 and update version specifications, or other specifications using differential transmission methods.

In some embodiments, the signal transmission apparatus illustrated in fig. 1 to 2 may also support the specification of the PCIe interface, wherein the positive differential low-speed pin 51, the negative differential low-speed pin 52, the first positive differential high-speed pin 151, the first negative differential high-speed pin 152, the second positive differential high-speed pin 161, and the second negative differential high-speed pin 162 may also be adapted to transmit the PCIe interface, and the positive differential low-speed pin 51 and the negative differential low-speed pin 52 may transmit clock signals (which may include a positive clock component and a negative clock component) conforming to the specification of the PCIe interface.

In some embodiments, the signal transmission apparatus may support a High Definition Multimedia Interface (HDMI), and as shown in fig. 1 and 2, the control signal pins may be SCL pins, SDA pins, and a Hot Plug Detection (Hot Plug Detection) pin 411, or a combination thereof. The SCL pins are the SCL/PCIE _ WAKE _ N pin 414 and the real _ SCL pin 419 for transmitting SCL (Serial Clock) signals; the SDA pins are the SDA/PCIE _ PERST _ N pin 412 and the real _ SDA pin 420 used to transmit SDA (Serial Data) signals. The SCL pin and the SDA pin may be used for communication between a signal generating source (e.g., a Digital Video Disc (DVD)) device and a signal receiving end (e.g., a Television (TV)) device, and the source device reads a resolution supported by the playback device through the SCL pin and the SDA pin, so that the source device displays an image frame conforming to the resolution of the playback device. Also, four pairs of the positive

Differential pins

111, 121, 131, 141, 171, 181, 191, 101 and the negative

Differential pins

112, 122, 132, 142, 172, 182, 192, 102 may transmit three pairs of Transition Minimized Differential Signaling (TMDS) and one pair of clock signals suitable for the HDMI specification to support the transmission of the HDMI signal.

In some embodiments, the plurality of control signal pins of the signal transmission device may be an ARC (Audio Return Channel)/SPDIF pin 415, a CLK (Audio-SYNC clock) pin 413, a plurality of pins adapted to a Serial Peripheral Interface (SPI), or a combination thereof, to transmit the Audio and video related control signals between the electronic devices, wherein the plurality of pins adapted to the SPI includes an SPI _ DI pin 416, an SPI _ CS pin 417, an SPI _ WP _ PWM pin 421, an SPI _ DO pin 423, an SPI _ HOLD _ PWM pin 422, and an SPI _ CLK pin 418.

In some embodiments, one of the control signal pins of the signal transmission device may be a system main power pin 410, the system main power pin 410 transmits a control signal (or called an enable signal) for turning on or off whether the external device provides power, for example, the signal transmission device may be connected between a notebook computer and a tablet computer, the tablet computer may be regarded as an external device of the notebook computer, the tablet computer has a power supply function for supplying power to the notebook computer, and the system main power pin 410 may transmit a control signal for turning on or off the power supply function. In configuration, the system main power pin 410 is located between the positive differential low speed pin 51, the negative differential low speed pin 52 and the first positive differential high speed pin 151, the first negative differential high speed pin 152, the second positive differential high speed pin 161, the second negative differential high speed pin 162 to isolate the transmission of the low speed data signal from the high speed data signal. In some embodiments, the control signal pins are arranged along the same straight direction D1.

In some embodiments, the POWER signal pins 31-34 may be a plurality of low voltage POWER pins and a plurality of high voltage POWER pins, wherein the POWER signal pins 31, 32 are low voltage POWER pins, i.e., HV-POWER pins, and the POWER signal pins 31, 32 supply a low voltage POWER signal related to HV, which may have a voltage of 12 volts (V); the POWER signal pins 33, 34 are high voltage POWER pins, i.e., UHV-POWER pins, and the POWER signal pins 33, 34 supply a UHV-related high voltage POWER signal, which may have a voltage of 350V. In some embodiments, the number of the low voltage power pins and the high voltage power pins can be adjusted according to the actual on-current of the signal transmission device and the differential signal transmission rate.

In some embodiments, as shown in fig. 1 and fig. 2, the plurality of ground pins of the signal transmission device may provide a power signal ground, that is, the power ground pins 61 and 62 of the plurality of ground pins may provide a ground for the power signal pins 33 and 34 of the high voltage power pin, and the power signal pins 33 and 34 and the power ground pins 61 and 62 are arranged along the same straight direction D1. Furthermore, the signal transmission device further includes an insulating layer I, the insulating layer I is located between the POWER signal pins 33 and 34 and the POWER ground pins 61 and 62 of the plurality of ground pins for grounding the POWER signal pins 33 and 34, that is, the POWER signal pins 33 and 34, which are UHV-POWER pins, are located on one side of the insulating layer I, and the POWER ground pins 61 and 62 are located on the other side of the insulating layer I. Therefore, the insulating layer I disposed between the power signal pins 33 and 34 and the power ground pins 61 and 62 can prevent the voltage across the pins from being too high to cause arcing or damage to the signal transmission device.

In some embodiments, referring to fig. 1 and 2, the signal transmission device is provided with a metal isolation layer M for isolating the electrical structure from the physical structure (among the pins of the signal transmission device). In detail, as shown in fig. 1 and fig. 2, the power signal pins 31 and 32, the positive differential pins 111, 121, 131, 141, 171, 181, 191, 101, the negative differential pins 112, 122, 132, 142, 172, 182, 192, 102, and the ground pins 21, 22, 23, 24, 25, 26, 27, 28, 29 are located on one side of the metal isolation layer M in the direction D2; the positive differential low-speed pin 51, the negative differential low-speed pin 52, the first positive differential high-speed pin 151, the first negative differential high-speed pin 152, the tenth ground pin 20, the second positive differential high-speed pin 161, the second negative differential high-speed pin 162, the plurality of control signal pins, the power signal pins 33, 34, the power ground pin 61, the power ground pin 62, and the insulating layer I are located on the other side of the metal isolation layer M in the direction D2, and the direction D2 is perpendicular to the direction D1 (for example, the direction D2 may be a length direction of the signal transmission device), in other words, the positive differential pins 111, 121, 131, 141, 171, 181, 191, 101, the negative differential pins 112, 122, 132, 142, 172, 182, 192, 102, and the positive differential low-speed pin 51 and the negative differential low-speed pin 52 are arranged in parallel to each other along the direction D2 through the metal isolation layer M; the positive differential pins 111, 121, 131, 141, 171, 181, 191, 101, the negative differential pins 112, 122, 132, 142, 172, 182, 192, 102 are arranged in parallel with the first positive differential high-speed pin 151, the first negative differential high-speed pin 152, the second positive differential high-speed pin 161, and the second negative differential high-speed pin 162 along the direction D2 through the metal spacer M; the positive differential pins 111, 121, 131, 141, 171, 181, 191, 101, the negative differential pins 112, 122, 132, 142, 172, 182, 192, 102, and the plurality of control signal pins are arranged in parallel along the direction D2 through the metal isolation layer M; the power signal pins 31, 32 and the power signal pins 33, 34 are arranged in parallel along the direction D2 through the metal isolation layer M. In some embodiments, the metal isolation layer M may be an iron sheet, and may provide a signal ground. Therefore, the metal isolation layer M can prevent the pins at two sides from interfering with each other, and provide a good reference ground plane to strengthen the signal quality and the impedance matching characteristic, and the double rows of parallel pins can also reduce the size of the signal transmission device and improve the convenience of production.

In some embodiments, referring to fig. 1, fig. 2 and fig. 3, all the pins of the signal transmission device may be formed by winding core wires (line), and the pins may be arranged in the same straight direction. For example, as shown in fig. 3, the wire G1 may be a twisted pair with a ground pin for shielding, the wire G2 may be a twisted pair without a ground pin for shielding, the wire G3 may be a thin single core wire, and the wire G4 may be a thick single core wire, all the pins of the signal transmission device may be bundled as the wires G1, G2, G3, and G4 respectively and arranged in the same straight direction. In other embodiments, as shown in fig. 4, the wires G1-G4 may also be a bundle of wires wrapped in a circular ring shape, that is, the wires G1, G2, G3, and G4 may not be arranged in the same straight direction.

In some embodiments, the signal transmission device includes a housing. The signal transmission device can be designed into one of a male connector or a female connector, the male connector and the female connector correspond to each other, and the signal transmission device serving as the male connector and the signal transmission device serving as the female connector can be connected. Referring to fig. 5A to 5D, fig. 5A and 5B are respectively an embodiment of a female connector and a male connector, fig. 5C is a side view of a side SA of the signal transmission device in fig. 5A, and fig. 5D is a side view of a side SB of the signal transmission device in fig. 5B. As shown in fig. 5C and 5D, the ends a and a 'are designed as oblique angles, and the ends B and B' are also designed as oblique angles, so that the two signal transmission devices, which are the female connector and the male connector respectively, can be connected with each other according to the ends a to a 'and the ends B to B', and the oblique angles can be used as a fool-proof mechanism for preventing the wrong connection between the male connector and the female connector. In other embodiments, the housing comprises a bevel angle and a right angle, and the bevel angle and the right angle are respectively located at two sides of the housing. Referring to fig. 6A and 6B, fig. 6A is another schematic diagram of a signal transmission device serving as a female connector, and fig. 6B is another schematic diagram of a signal transmission device serving as a male connector. As shown in fig. 6A and 6B, the ends C and C 'are designed as right angles, and the ends D and D' are designed as oblique angles, so that two signal transmission devices respectively serving as the female connector and the male connector can be connected to each other according to the ends C to C 'and the ends D to D'. In other embodiments, please refer to fig. 7A and 7B, in which fig. 7A is another schematic diagram of the signal transmission device serving as the female connector, and fig. 7B is another schematic diagram of the signal transmission device serving as the male connector. As shown in fig. 7A and 7B, the ends E and E ' are designed as chamfered corners, and the ends F and F ' are designed as right angles, so that two signal transmission devices respectively serving as the female connector and the male connector can be connected to each other according to the ends E ' and F ' to the ends F '. Therefore, the signal transmission device can provide signal transmission device combination on different products and separate the joints of the signal transmission device according to the fact that the joints are in different oblique angle forms, and the possibility of mistaken connection between the male joint and the female joint is avoided.

In some embodiments, referring to fig. 8, fig. 8 illustrates a transmission line and an electronic device N suitable for the transmission line. The transmission line comprises signal transmission devices P and Q and a connecting part L, wherein the signal transmission devices P and Q are arranged at two ends of the transmission line, and the connecting part L is connected between the signal transmission devices P and Q. The electronic device N comprises a signal transmission device R corresponding to the signal transmission devices P and Q of the transmission line. Since the signal transmission devices P, Q, and R are respectively designed as one of a male connector and a female connector, the male connector can be connected with the female connector, so that the signal transmission device P or the signal transmission device Q can be connected with the signal transmission device R of the electronic device N, and the electronic device N can be a notebook computer, a mobile phone, a tablet, a display, or other video-audio related devices. For example, when the signal transmission device Q as the male connector is connected to the signal transmission device R as the female connector and the signal transmission device P as the female connector is connected to the signal transmission device P as the male connector of another electronic device, the other electronic device can transmit signals from the signal transmission device P of the transmission line to the electronic device N through the connection portion L, the signal transmission device Q and the signal transmission device R.

In some embodiments, for example, the insulation layer I is not designed to be in the form of pins, and the total number of pins is 52, as shown in fig. 2 (from top to bottom and from left to right), pins 1, 4, 7, 10, 13, 16, 19, 22, 25, 33, 49, 50 are GND; pins 2, 3, 5, 6, 8, 9, 11, 12, 14, 15, 17, 18, 20, 21, 23, 24 are respectively P3_ RTK1_ P, P3_ RTK1_ M, P3_ RTK0_ P, P3_ RTK0_ M, P2_ RTK1_ P, P2_ RTK1_ M, P2_ RTK0_ P, P2_ RTK0_ M, P1_ RTK1_ P, P1_ RTK1_ M, P1_ 0_ P, P1_ RTK0_ M, P0_ RTK1_ P, P0_ 1_ M, P0_ RTK0_ P, P0_ RTK0_ M; the 26 th pin and the 27 th pin are HV _ POWER; the 51 st pin and the 52 th pin are UHV _ POWER; pins 28-32, 34-48 are USB _ DM/REFCLK _ M _ PCIE, USB _ DP/REFCLK _ P _ PCIE, SYSTEM _ MAIN _ POWER _ EN, USB _ SSRX _ M/PCIE _ HSIN, USB _ SSRX _ P/PCIE _ HSIP, USB _ SSTX _ M/PCIE _ HSON, USB _ SSTX _ P/PCIE _ HSOP, HOT _ PLUG _ ECTDET, SDA/PCIE _ PERST _ N, AUDIO _ CLK _ SCL, SPI/PCIE _ WAKE _ N, ARC/SPDIF, SPI _ DI, SPI _ CS, SPI _ CLK, REALONE _ PAS, REALONE _ RSA, SPI _ PWM, SPI _ HOLD _ PWM, SPI _ DO, respectively. Wherein, the outer sides of the 1 st pin and the 28 th pin are Panel (Panel) ends.

In some embodiments, for example, the insulation layer I is not designed to be in the form of pins, and the total number of pins is 52, as shown in fig. 9 (from top to bottom and from left to right), the 1 st, 4 th, 7 th, 10 th, 13 th, 16 th, 19 th, 22 th, 25 th, 33 th, 49 th, 50 th pins are GND; pins 2, 3, 5, 6, 8, 9, 11, 12, 14, 15, 17, 18, 20, 21, 23, 24 are P0_ RTK0_ M, P0_ RTK0_ P, P0_ RTK1_ M, P0_ RTK1_ P, P1_ RTK0_ M, P1_ RTK0_ P, P1_ RTK1_ M, P1_ RTK1_ P, P2_ RTK0_ M, P2_ RTK0_ P, P2_ RTK1_ M, P2_ RTK1_ P, P3_ RTK0_ M, P3_ 0_ P, P3_ RTK1_ M, P3_ RTK1_ P, respectively; the 26 th pin and the 27 th pin are HV _ POWER; the 51 st pin and the 52 th pin are UHV _ POWER; pins 28-32, 34-48 are USB _ DP/REFCLK _ P _ PCIE, USB _ DM/REFCLK _ M _ PCIE, SYSTEM _ MAIN _ POWER _ EN, USB _ SSTX _ P/PCIE _ HSIP, USB _ SSTX _ M/PCIE _ HSIN, USB _ SSRX _ P/PCIE _ HSOP, USB _ SSRX _ M/PCIE _ HSON, HOT _ PLUG _ DET, SDA/PCIE _ PERST _ N, AUDIO _ CLK, SCL/PCIE _ WAKE _ N, ARC/SPDIF, SPI _ DI, SPI _ CS, SPI _ CLK, REALOSCLL _ SYNC, REALONE _ SYNC, SPI _ PWM, SPI _ HOWP _ PWM, SPI _ DO, respectively. Wherein, the outer sides of the 1 st pin and the 28 th pin are System On Chip (SOC) ends.

In some embodiments, pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 31-35 may be left unused, i.e., the total number of pins is 35, in accordance with the design of fig. 2. That is, as shown in fig. 1, the 1 st, 4 th, 7 th, 10 th, 13 th, 32 th, 33 th pins are GND; the 2 nd, 3 rd, 5 th, 6 th, 8 th, 9 th, 11 th and 12 th pins are respectively P1_ RTK1_ P, P1_ RTK1_ M, P1_ RTK0_ P, P1_ RTK0_ M, P0_ RTK1_ P, P0_ RTK1_ M, P0_ RTK0_ P and P0_ RTK0_ M; the 14 th and 15 th pins are HV _ POWER; the 34 th and 35 th pins are UHV _ POWER; pins 16-31 are USB _ DM/REFCLK _ M _ PCIE, USB _ DP/REFCLK _ P _ PCIE, SYSTEM _ MAIN _ POWER _ EN, HOT _ PLUG _ DETECT, SDA/PCIE _ PERST _ N, AUDIO _ SYNC _ CLK, SCL/PCIE _ WAKE _ N, ARC/SPDIF, SPI _ DI, SPI _ CS, SPI _ CLK, REALONE _ SCL, REALONE _ SDA, SPI _ WP _ PWM, SPI _ HOLD _ PWM, SPI _ DO, respectively. Wherein, the outer side of the 16 th pin is a Panel (Panel) end.

In some embodiments, pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 31-35 may be left unused, i.e., the total number of pins is 35, in accordance with the design of fig. 9. That is, as shown in fig. 10, the 1 st, 4 th, 7 th, 10 th, 13 th, 32 th, 33 th pins are GND; the 2 nd, 3 rd, 5 th, 6 th, 8 th, 9 th, 11 th and 12 th pins are respectively P0_ RTK0_ M, P0_ RTK0_ P, P0_ RTK1_ M, P0_ RTK1_ P, P1_ RTK0_ M, P1_ RTK0_ P, P1_ RTK1_ M and P1_ RTK1_ P; the 14 th and 15 th pins are HV _ POWER; pins 34 and 35 are UHV _ POWER; pins 16-31 are USB _ DP/REFCLK _ P _ PCIE, USB _ DM/REFCLK _ M _ PCIE, SYSTEM _ MAIN _ POWER _ EN, HOT _ PLUG _ DETECT, SDA/PCIE _ PERST _ N, AUDIO _ SYNC _ CLK, SCL/PCIE _ WAKE _ N, ARC/SPDIF, SPI _ DI, SPI _ CS, SPI _ CLK, REALONE _ SCL, REALONE _ SDA, SPI _ WP _ PWM, SPI _ HOLD _ PWM, SPI _ DO, respectively. Wherein, the outer side of the 16 th pin is a System On Chip (SOC) end.

In some embodiments, the number of the core wires can be adjusted according to different applications and embodiments, for example, the number of the pins is 52 and all the pins are used, the signal transmission device can be formed by 50 core wires, and for example, the number of the pins is 52 and 35 of the pins are used, the signal transmission device can be formed by 33 core wires. The user can select different differential pins and winding combinations of control signals according to the specification types to be supported so as to realize the purpose of data transmission.

In summary, according to an embodiment of the signal transmission device of the present disclosure, the same pair of differential signal pins is disposed between the two ground pins, so that signal crosstalk can be avoided and a better impedance matching characteristic can be obtained. Furthermore, the grounding pin is disposed at the extreme edge position of the pin accommodating space, so as to prevent the differential signal from being interfered by noise outside the signal transmission device, and reduce energy transmitted by the differential signal to the outside of the signal transmission device in the form of Electromagnetic wave, so as to reduce Electromagnetic Interference (EMI) and achieve better Electromagnetic compatibility (EMC) and electrostatic discharge (ESD). The signal transmission device improves transmission quality, and the transmission line can transmit signals to the electronic device more efficiently. Moreover, the signal transmission device can support various existing transmission specifications, such as a USB specification, a PCIe specification, a Display Port specification, and an HDMI specification, so that a single signal transmission device transmits a larger data transmission amount in a multiplexing manner, and a user does not need to prepare various transmission lines supporting different specifications, thereby facilitating convenience in use.

Although the present disclosure has been described with reference to specific embodiments, it will be apparent to one of ordinary skill in the art that changes and modifications may be made without departing from the spirit and scope of the disclosure.

Claims

1. A signal transmission apparatus capable of transmitting a plurality of data streams, comprising:

a first positive differential pin of the positive differential pins is used for transmitting a positive signal component of a first differential signal, and a second positive differential pin of the positive differential pins is used for transmitting a positive signal component of a second differential signal;

a first negative differential pin of the plurality of negative differential pins is used for transmitting a negative signal component of a first differential signal, and a second negative differential pin of the plurality of negative differential pins is used for transmitting a negative signal component of a second differential signal;

a plurality of ground pins;

a plurality of power signal pins; and

a plurality of control signal pins;

wherein, this first positive differential pin and this first negative differential pin are located one side of a first ground pin in a plurality of ground pins, and this second positive differential pin and this second negative differential pin are located the opposite side of this first ground pin, and wherein, a plurality of positive differential pins and a plurality of negative differential pin transmission high-speed data signal, this signal transmission device still contains:

a positive differential low-speed pin for transmitting a positive signal component of a low-speed differential signal; and

and the negative differential low-speed pin is used for transmitting a negative signal component of the low-speed differential signal.

2. The signal transmission device as claimed in claim 1, wherein the second positive differential pin and the second negative differential pin are further located between the first ground pin and a second ground pin of the plurality of ground pins.

3. The signal transmission device according to claim 2, wherein the first positive differential pin and the first negative differential pin are further located between the first ground pin and a third ground pin of the plurality of ground pins.

4. The signal transmission device as claimed in claim 1, wherein a first positive differential high-speed pin of the plurality of positive differential pins is configured to transmit a positive signal component of a fifth differential signal, a first negative differential high-speed pin of the plurality of negative differential pins is configured to transmit a negative signal component of the fifth differential signal, a second positive differential high-speed pin of the plurality of positive differential pins is configured to transmit a positive signal component of a sixth differential signal, and a second negative differential high-speed pin of the plurality of negative differential pins is configured to transmit a negative signal component of the sixth differential signal;

the first positive differential high-speed pin and the first negative differential high-speed pin are located on one side of a tenth grounding pin of the grounding pins, and the second positive differential high-speed pin and the second negative differential high-speed pin are located on the other side of the tenth grounding pin.

5. The signal transmission device according to claim 4, wherein the plurality of control signal pins includes a system main power pin, the system main power pin being located between the positive differential low-speed pin, the negative differential low-speed pin and the first positive differential high-speed pin, the first negative differential high-speed pin, the second positive differential high-speed pin, the second negative differential high-speed pin.

6. The signal transmitting device as claimed in claim 3, wherein the power signal pins are a plurality of low voltage power pins and a plurality of high voltage power pins, the low voltage power pins are used for transmitting low voltage power signals, the high voltage power pins are used for transmitting high voltage power signals, and the third ground pin is located between the low voltage power pins and the first positive differential pin and the first negative differential pin.

7. The signal transmission apparatus of claim 6, further comprising:

a metal isolation layer;

the plurality of positive differential pins, the plurality of negative differential pins and the plurality of low-voltage power supply pins are positioned on one side of the metal isolation layer, the positive differential low-speed pins, the negative differential low-speed pins, the plurality of high-voltage power supply pins and the plurality of control signal pins are positioned on the other side of the metal isolation layer, and the plurality of positive differential pins, the plurality of negative differential pins, the plurality of low-voltage power supply pins and the plurality of control signal pins are arranged in parallel through the metal isolation layer.

8. The signal transmitting device as claimed in claim 7, wherein the first positive differential pin, the first negative differential pin, the second positive differential pin and the second negative differential pin are arranged in parallel with the first positive differential high-speed pin, the first negative differential high-speed pin, the second positive differential high-speed pin and the second negative differential high-speed pin through the metal isolation layer.

9. The signal transmitting device according to claim 1, further comprising a housing for accommodating the positive differential pins, the negative differential pins, the ground pins, the power signal pins, and the control signal pins, wherein the housing comprises a diagonal angle and a straight angle, and the diagonal angle and the straight angle are respectively located at two sides of the housing.