CN113809596A - Signal transmission device capable of transmitting multiple data streams - Google Patents

Abstract

The present disclosure provides a signal transmission device, which includes a plurality of positive differential pins, a plurality of negative differential pins, a plurality of ground pins, a plurality of power signal pins, and a plurality of control signal pins. A first positive differential pin of the plurality of positive differential pins transmits a positive signal component of the first differential signal, and a second positive differential pin of the plurality of positive differential pins transmits a positive signal component of the second differential signal; a first negative differential pin of the plurality of negative differential pins transmits a negative signal component of the first differential signal, and a second negative differential pin of the plurality of negative differential pins transmits a negative signal component of the second differential signal; the first positive differential pin and the first negative differential pin are located on one side of a first ground pin of the plurality of ground pins, and the second positive differential pin and the second negative differential pin are located on the other side of the first ground pin.

Description

Signal transmission device capable of transmitting multiple data streams

Technical Field

The present invention relates to a signal transmission apparatus capable of transmitting a plurality of sets of data streams.

Background

As the quality of video playback images is required to be higher, the original 4K resolution is increased to 8K resolution, and thus the amount of data transmission from a player serving as a Signal Source (Signal Source) to a display serving as a Signal Sink (Signal Sink) is also increased. Moreover, due to the rise of home theaters, it is often necessary to use longer transmission lines to connect signal generation sources and signal receiving ends, so as to meet the requirements of various living rooms.

In the current specifications of signal transmission devices, if the Ground Shielding (Ground Shielding) is regarded as the best way to design for differential signals, the signal quality when transmitting high-speed signals is easily affected by Crosstalk (Crosstalk) and Delay (Delay), and it is difficult to transmit signals over long distances.

Disclosure of Invention

In some embodiments, a signal transmitting device includes a plurality of positive differential pins, a plurality of negative differential pins, a plurality of ground pins, a plurality of power signal pins, and a plurality of control signal pins. A first positive differential pin of the plurality of positive differential pins is used for transmitting a positive signal component of the first differential signal, and a second positive differential pin of the plurality of positive differential pins is used for transmitting a positive signal component of the second differential signal; a first negative differential pin of the plurality of negative differential pins is used for transmitting a negative signal component of the first differential signal, and a second negative differential pin of the plurality of negative differential pins is used for transmitting a negative signal component of the second differential signal; the first positive differential pin and the first negative differential pin are located on one side of a first grounding pin in the plurality of grounding pins, and the second positive differential pin and the second negative differential pin are located on the other side of the first grounding pin.

Drawings

Fig. 1 is a schematic diagram of an embodiment of a signal transmission apparatus according to the present disclosure.

Fig. 2 is a schematic diagram of another embodiment of the signal transmission device of fig. 1.

Fig. 3 is a schematic diagram of an embodiment of a pin arrangement of a signal transmission device according to the present disclosure.

Fig. 4 is a schematic diagram of an embodiment of a pin arrangement of a signal transmission device according to the present disclosure.

Fig. 5A is an external view of an embodiment of a female connector of a signal transmission device according to the present disclosure.

Fig. 5B is an external view of an embodiment of a male connector of the signal transmission device corresponding to fig. 5A.

Fig. 5C is a side view of the signal transmission device of fig. 5A according to an embodiment.

FIG. 5D is a schematic side view of the signal transmission device of FIG. 5B according to an embodiment.

Fig. 6A is a side view schematic diagram of another embodiment of a female connector of a signal transmission device according to the present disclosure.

Fig. 6B is a schematic side view of another embodiment of a male connector corresponding to the signal transmission device of fig. 6A.

Fig. 7A is a side view schematic diagram of another embodiment of a female connector of a signal transmission device according to the present disclosure.

Fig. 7B is a schematic side view of another embodiment of a male connector corresponding to the signal transmission device of fig. 7A.

Fig. 8A is an external view schematically illustrating another embodiment of a female connector of a signal transmission device according to the present disclosure.

Fig. 8B is a schematic side view of another embodiment of the signal transmission device of fig. 8A.

Fig. 8C is a schematic external view of another embodiment of the male connector of the signal transmission device corresponding to fig. 8A.

Fig. 8D is a schematic side view of another embodiment of the signal transmission device corresponding to fig. 8C.

Fig. 8E is an external view of an embodiment of the female connector of the signal transmission device of fig. 8A and the male connector of the signal transmission device of fig. 8C connected to each other.

Fig. 8F is a top view of an embodiment of the female connector of the signal transmission device of fig. 8A and the male connector of the signal transmission device of fig. 8C.

Fig. 9 is a schematic top view of another embodiment of a female connector and a male connector of a signal transmission device according to the present disclosure.

Fig. 10 is a schematic top view of another embodiment of a female connector and a male connector of a signal transmission device according to the present disclosure.

Fig. 11 is a schematic top view of another embodiment of a female connector and a male connector of a signal transmission device according to the present disclosure.

Fig. 12 is a schematic diagram of an embodiment of a transmission line and an electronic device including a signal transmission device according to the present disclosure.

Fig. 13A and 13B are schematic diagrams of another embodiment of a signal transmission device according to the disclosure.

Fig. 14A and 14B are schematic diagrams illustrating another embodiment of the signal transmission device of fig. 13 respectively.

Fig. 15A and 15B are schematic diagrams illustrating a signal transmission device according to an embodiment of the disclosure.

Fig. 16A and 16B are schematic diagrams illustrating a signal transmission device according to an embodiment of the disclosure.

Fig. 17A and 17B are schematic diagrams illustrating an embodiment of a public signal transmission apparatus according to the present disclosure.

Fig. 18A and 18B are schematic diagrams illustrating a signal transmission device according to an embodiment of the disclosure.

Fig. 19A and 19B are schematic diagrams illustrating a signal transmission device according to an embodiment of the disclosure.

Fig. 20A and 20B are schematic diagrams illustrating a signal transmission device according to an embodiment of the disclosure.

Description of the symbols

111: first positive differential pin

112: first negative differential pin

121: second positive differential pin

122: second negative differential pin

131: third positive differential pin

132: third negative differential pin

141: fourth positive differential pin

142: fourth negative differential pin

151: first positive differential high-speed pin

152: first negative differential high-speed pin

161: second positive differential high speed pin

162: second negative differential high-speed pin

171: seventh positive differential pin

172: seventh negative differential pin

181: eighth positive differential pin

182: eighth negative differential pin

191: ninth positive differential pin

192: ninth negative differential pin

101: tenth positive differential pin

102: tenth negative differential pin

21: first grounding pin

22: second grounding pin

23: third grounding pin

24: fourth grounding pin

25: fifth grounding pin

26: sixth ground pin

27: seventh ground pin

28: eighth ground pin

29: ninth ground pin

20: tenth ground pin

31: power signal pin

32: power signal pin

33: power signal pin

34: power signal pin

410: system main power supply enable pin

411: hot plug detection pin

412: SDA/PCIE _ PERST _ N pin

413: CLK pin

414: SCL/PCIE _ WAKE _ N pin

415: iRealOne _ LINK pin

416: SPI _ DI pin

417: SPI _ CS Pin

418: SPI _ CLK pin

419: REALONE _ SCL pin

420: REALONE _ SDA pin

421: SPI _ WP _ PWM pin

422: SPI _ HOLD _ PWM pin

423: SPI _ DO pin

51: positive differential low-speed pin

52: negative differential low-speed pin

61: high-voltage grounding pin

62: high-voltage grounding pin

I: insulating layer

M: metal barrier layer

D1: direction of rotation

D2: direction of rotation

G1: wire rod

G2: wire rod

G3: wire rod

G4: wire rod

And SA: one side of

SB: one side of

And SE: right inner side surface

SF: left inner side surface

SG: right lateral surface

SH: left outer side surface

A: terminal end

A': terminal end

B: terminal end

B': terminal end

C: terminal end

C': terminal end

D: terminal end

D': terminal end

E: terminal end

E': terminal end

F: terminal end

F': terminal end

H: terminal end

H': terminal end

J: terminal end

J': terminal end

O1: shell body

O11: projecting part

O12: spring buckle

O13: buckle hole

O2: tongue part

O3: containing space

O4: insertion space

And Oa: side wall

Ob: side wall

And Oc: roof wall

K1: shell body

K11: projecting part

K12: groove

K13: buckle hole

K2: containing space

K3: insertion space

Ka: side wall

Kb: side wall

Kc: roof wall

T: insulator

Z: substrate

P: signal transmission device

Q: signal transmission device

R: signal transmission device

L: connecting part

N: electronic device

SV: direction of butt joint

SH: in the horizontal direction

Y: center shaft

a 1: length of

a 2: length of

a 3: length of

a 4: length of

b 1: length of

b 2: length of

b 3: length of

b 4: length of

c 1: length of

c 2: length of

c 3: length of

c 4: length of

d 1: length of

d 2: length of

d 3: length of

d 4: length of

Detailed Description

Referring to fig. 1, fig. 1 is a schematic diagram of a signal transmission device according to an embodiment of the disclosure. The signal transmission device comprises a plurality of positive differential pins (Pin), a plurality of negative differential pins, a plurality of control signal pins, a plurality of power signal pins and a plurality of grounding pins. The number of the positive differential pins, the number of the negative differential pins, the number of the ground pins, the number of the power signal pins, and the number of the control signal pins may be customized according to different product requirements (e.g., required current, signal transmission rate), fig. 1 is only one embodiment of the signal transmission apparatus, and the disclosure is not limited thereto.

Fig. 1 illustrates a plurality of positive differential pins 111, 121, 131, 141, a plurality of negative differential pins 112, 122, 132, 142, and a plurality of ground pins (GND)21-25 corresponding to the respective differential pins 111, 112, 121, 122, 131, 132, 141, 142. The positive differential pins 111, 121, 131, 141 and the negative differential pins 112, 122, 132, 142 respectively transmit positive signal components and negative signal components of differential signals, and the positive differential pins 111, 121 (for convenience of description, referred to as the first positive differential pin 111 and the second positive differential pin 121, respectively), the negative differential pins 112, 122 (referred to as the first negative differential pin 112 and the second negative differential pin 122, respectively), and the corresponding ground pin 21 (hereinafter referred to as the first ground pin 21) are exemplified.

The first positive differential pin 111 and the first negative differential pin 112 transmit a first differential signal, wherein the first positive differential pin 111 transmits a positive signal component of the first differential signal, and the first negative differential pin 112 transmits a negative signal component of the first differential signal; the second positive differential pin 121 and the second negative differential pin 122 transmit another differential signal (hereinafter, referred to as a second differential signal) different from the first differential signal, the second positive differential pin 121 transmits a positive signal component of the second differential signal, and the second negative differential pin 122 transmits a negative signal component of the second differential signal. In configuration, the first positive differential pin 111 and the first negative differential pin 112 are located on one side of the first ground pin 21 (i.e., the two differential pins 111 and 112 transmitting the same differential signal are located on the same side of the first ground pin 21), and the second positive differential pin 121 and the second negative differential pin 122 are located on the other side of the first ground pin 21 (i.e., the two differential pins 121 and 122 transmitting the same differential signal are located on the same side of the first ground pin 21), i.e., the two differential pins 111 and 122 transmitting different differential signals are located on different sides of the first ground pin 21.

Further, FIG. 1 illustrates four power signal pins 31-34 and a plurality of control signal pins. The power signal pins 31-34 can transmit power signals meeting a specific communication specification, and the control signal pins can transmit control signals meeting the specific communication specification, in other words, the signal transmission device can transmit power signals and control signals for the electronic device to operate in addition to differential signals, and meet the specific communication specification. Therefore, different from the conventional signal transmission device, the signal transmission device of the present disclosure can avoid crosstalk (crosstalk) between different differential signals when transmitting the first differential signal and the second differential signal, and obtain better impedance matching characteristics, thereby improving the transmission quality of the signal transmission device and transmitting signals to the electronic device more efficiently.

In some embodiments, as shown in fig. 1, the signal transmission device can transmit at least four pairs of differential signals, the third positive differential pin 131 and the third negative differential pin 132 can transmit a third differential signal, the third positive differential pin 131 can transmit a positive signal component of the third differential signal, the third negative differential pin 132 can transmit a negative signal component of the third differential signal, the fourth positive differential pin 141 and the fourth negative differential pin 142 can transmit a fourth differential signal, the fourth positive differential pin 141 can transmit a positive signal component of the fourth differential signal, and the fourth negative differential pin 142 can transmit a negative signal component of the fourth differential signal. In order to prevent the four pairs of differential signals from interfering with each other, as shown in fig. 1, the plurality of ground pins of the signal transmission device are a first ground pin 21, a second ground pin 22, a third ground pin 23, a fourth ground pin 24, and a fifth ground pin 25. The second positive differential pin 121 and the second negative differential pin 122 are located between the first ground pin 21 and the fourth ground pin 24, that is, the second positive differential pin 121 and the second negative differential pin 122 are located on one side of the fourth ground pin 24, and the third positive differential pin 131 and the third negative differential pin 132 are located on the other side of the fourth ground pin 24; the third positive differential pin 131 and the third negative differential pin 132 are located between the fourth ground pin 24 and the fifth ground pin 25, that is, the third positive differential pin 131 and the third negative differential pin 132 are located on one side of the fifth ground pin 25, and the fourth positive differential pin 141 and the fourth negative differential pin 142 are located on the other side of the fifth ground pin 25. Therefore, the second positive differential pin 121 and the third negative differential pin 132 are shielded by the fourth ground pin 24, the third positive differential pin 131 and the fourth negative differential pin 142 are shielded by the fifth ground pin 25, and the first differential signal, the second differential signal, the third differential signal and the fourth differential signal do not interfere with each other.

In some embodiments, the positive differential pins 111, 121, 131, 141 and the negative differential pins 112, 122, 132, 142 are arranged along the same straight direction D1 (e.g., the length direction of the signal transmission device), and the signal transmission device can be more easily compatible with the existing communication transmission specifications.

In some embodiments, referring to fig. 2, fig. 2 is a schematic diagram of another embodiment of the signal transmission device of fig. 1, the signal transmission device may also include eight pairs of differential pins, and each pair of differential pins for transmitting the same differential signal is shielded by two ground pins. The signal transmission device also includes positive differential pins 171, 181, 191, 101 (hereinafter referred to as a seventh positive differential pin 171, an eighth positive differential pin 181, a ninth positive differential pin 191, and a tenth positive differential pin 101, respectively), negative differential pins 172, 182, 192, 102 (hereinafter referred to as a seventh negative differential pin 172, an eighth negative differential pin 182, a ninth negative differential pin 192, and a tenth negative differential pin 102, respectively), and corresponding ground pins 26, 27, 28, 29. The positive differential pins 171, 181, 191, 101 and the negative differential pins 172, 182, 192, 102 are also arranged along the same linear direction D1. The seventh positive differential pin 171 and the seventh negative differential pin 172 can transmit a seventh differential signal, the seventh positive differential pin 171 transmits a positive signal component of the seventh differential signal, and the seventh negative differential pin 172 transmits a negative signal component of the seventh differential signal. The eighth positive differential pin 181 and the eighth negative differential pin 182 can transmit an eighth differential signal, the eighth positive differential pin 181 transmits a positive signal component of the eighth differential signal, and the eighth negative differential pin 182 transmits a negative signal component of the eighth differential signal. The ninth positive differential pin 191 and the ninth negative differential pin 192 can transmit a ninth differential signal, the ninth positive differential pin 191 transmits a positive signal component of the ninth differential signal, and the ninth negative differential pin 192 transmits a negative signal component of the ninth differential signal. The tenth positive differential pin 101 and the tenth negative differential pin 102 can transmit a tenth differential signal, the tenth positive differential pin 101 transmits a positive signal component of the tenth differential signal, and the tenth negative differential pin 102 transmits a negative signal component of the tenth differential signal.

In order to prevent the eight differential signals from interfering with each other, as shown in fig. 2, the fourth positive differential pin 141 and the fourth negative differential pin 142 are located between the fifth ground pin 25 and the sixth ground pin 26, that is, the fourth positive differential pin 141 and the fourth negative differential pin 142 are located on one side of the sixth ground pin 26, and the seventh positive differential pin 171 and the seventh negative differential pin 172 are located on the other side of the sixth ground pin 26; the seventh positive differential pin 171 and the seventh negative differential pin 172 are located between the sixth ground pin 26 and the seventh ground pin 27, that is, the seventh positive differential pin 171 and the seventh negative differential pin 172 are located on one side of the seventh ground pin 27, and the eighth positive differential pin 181 and the eighth negative differential pin 182 are located on the other side of the seventh ground pin 27; the eighth positive differential pin 181 and the eighth negative differential pin 182 are located between the seventh ground pin 27 and the eighth ground pin 28, that is, the eighth positive differential pin 181 and the eighth negative differential pin 182 are located on one side of the eighth ground pin 28, and the ninth positive differential pin 191 and the ninth negative differential pin 192 are located on the other side of the eighth ground pin 28; the ninth positive differential pin 191 and the ninth negative differential pin 192 are located between the eighth ground pin 28 and the ninth ground pin 29, that is, the ninth positive differential pin 191 and the ninth negative differential pin 192 are located on one side of the ninth ground pin 29, and the tenth positive differential pin 101 and the tenth negative differential pin 102 are located on the other side of the ninth ground pin 29. Therefore, the fourth positive differential pin 141 and the seventh negative differential pin 172 are shielded by the sixth ground pin 26, the seventh positive differential pin 171 and the eighth negative differential pin 182 are shielded by the seventh ground pin 27, the eighth positive differential pin 181 and the ninth negative differential pin 192 are shielded by the eighth ground pin 28, the ninth positive differential pin 191 and the tenth negative differential pin 102 are shielded by the ninth ground pin 29, and the first differential signal, the second differential signal, the third differential signal, the fourth differential signal, the seventh differential signal, the eighth differential signal, the ninth differential signal and the tenth differential signal do not interfere with each other. Therefore, the signal transmission device can transmit at least eight pairs of differential signals, and the eight pairs of differential pins are arranged along the same straight line direction D1, so that the signal transmission device can be more easily compatible with the existing communication transmission specification.

In some embodiments, as shown in fig. 1 and fig. 2, one side of the third ground pin 23 (i.e., the side far from the first negative differential pin 112) of the plurality of ground pins may be provided with the power signal pins 31 and 32 without the positive differential pin and the negative differential pin, and the other side of the third ground pin 23 is the first positive differential pin 111 and the first negative differential pin 112, i.e., the first positive differential pin 111 and the first negative differential pin 112 are located between the first ground pin 21 and the third ground pin 23, the first positive differential pin 111 and the first negative differential pin 112 are shielded by the two ground pins 21 and 23, and the ground pins 21 and 23 may collectively provide the first differential signal ground. Therefore, the third ground pin 23 separates the first positive differential pin 111 and the first negative differential pin 112 from the plurality of power signal pins 31 and 32, so that the first positive differential pin 111 and the first negative differential pin 112 are prevented from being interfered by the power signal when transmitting the first differential signal, and the transmission quality of the first differential signal is prevented from being reduced.

In some embodiments, as shown in fig. 2, the second ground pin 22 is located at an edge-most position of the signal transmission device, that is, one side of the second ground pin 22 in the straight direction D1 is not provided with the positive differential pin and the negative differential pin, and the other side of the second ground pin 22 in the straight direction D1 is the tenth positive differential pin 101 and the tenth negative differential pin 102. That is, the tenth positive differential pin 101 and the tenth negative differential pin 102 are located between the ninth ground pin 29 and the second ground pin 22, and the tenth positive differential pin 101 and the tenth negative differential pin 102 are shielded by the two ground pins 29 and 22, that is, the ground pins 29 and 22 can provide the tenth differential signal ground together. Therefore, the situation that the transmission quality of the tenth differential signal is reduced due to the fact that the tenth positive differential pin 101 and the tenth negative differential pin 102 are interfered by noise outside the signal transmission device when the tenth differential signal is transmitted can be further avoided. . .

In some embodiments, as shown in fig. 2, the plurality of differential pins of the signal transmission device also includes two positive differential pins 151, 161 and two negative differential pins 152, 162 (hereinafter, the positive differential pins 151, 161 are respectively referred to as a first positive differential high-speed pin 151 and a second positive differential high-speed pin 161, and the negative differential pins 152, 162 are respectively referred to as a first negative differential high-speed pin 152 and a second negative differential high-speed pin 162), and the plurality of ground pins of the signal transmission device also includes a tenth ground pin 20. The first positive differential high-speed pin 151 is configured to transmit a positive signal component of the fifth differential signal, and the first negative differential high-speed pin 152 is configured to transmit a negative signal component of the fifth differential signal; the second positive differential high-speed pin 161 is used for transmitting a positive signal component of the sixth differential signal, and the second negative differential high-speed pin 162 is used for transmitting a negative signal component of the sixth differential signal. In configuration, the first positive differential high speed pin 151 and the first negative differential high speed pin 152 are located on one side of the tenth ground pin 20, the second positive differential high speed pin 161 and the second negative differential high speed pin 162 are located on the other side of the tenth ground pin 20, and the positive differential high speed pins 151, 161, the tenth ground pin 20 and the negative differential high speed pins 152, 162 are arranged along the same straight direction D1.

In some embodiments, the positive differential pins and the negative differential pins of the signal transmission device are used for transmitting high-speed signals, for example, the first differential signal transmitted by the differential pins 111 and 112, the second differential signal transmitted by the differential pins 121 and 122, the third differential signal transmitted by the differential pins 131 and 132, the fourth differential signal transmitted by the differential pins 141 and 142, the seventh differential signal transmitted by the differential pins 171 and 172, the eighth differential signal transmitted by the differential pins 181 and 182, the ninth differential signal transmitted by the differential pins 191 and 192, the tenth differential signal transmitted by the differential pins 101 and 102, the fifth differential signal transmitted by the differential high- speed pins 151 and 152, and the sixth differential signal transmitted by the differential high- speed pins 161 and 162 are all high-speed signals. As shown in fig. 1 and 2, the signal transmission device may further include a positive differential low-speed pin 51 and a negative differential low-speed pin 52 for transmitting low-speed data signals, and the positive differential low-speed pin 51 and the negative differential low-speed pin 52 are arranged along the same straight direction D1 as the differential high- speed pins 151, 152, 161, and 162. The positive differential low-speed pin 51 and the negative differential low-speed pin 52 transmit low-speed differential signals that are low-speed data, the positive differential low-speed pin 51 transmits a positive signal component of the low-speed differential signals, and the negative differential low-speed pin 52 transmits a negative signal component of the low-speed differential signals. Therefore, the signal transmission device can simultaneously support the transmission of high-speed signals and low-speed data signals.

In some embodiments, the signal transmission apparatus illustrated in fig. 1 to 2 may support a Universal Serial Bus (USB) 2.0 specification, the positive differential low-speed pin 51 and the negative differential low-speed pin 52 are suitable for the USB2.0 specification, the low-speed differential signals transmitted by the positive differential low-speed pin 51 and the negative differential low-speed pin 52 are USB signals of USB2.0, the positive differential low-speed pin 51 can transmit USB-DP signals, and the negative differential low-speed pin 52 can transmit USB-DM signals. Moreover, the signal transmission apparatus illustrated in fig. 2 can also support various specifications using differential transmission methods, and any two pairs of the positive differential pins and the negative differential pins (i.e., the differential pins 111, 112, 121, 122, 131, 132, 141, 142, 171, 172, 181, 182, 191, 192, 101, 102 and the differential high- speed pins 151, 152, 161, 162) of the signal transmission apparatus for transmitting high-speed signals can transmit high-speed data transmission and reception signals conforming to USB2.0 or PCIe 1.0 and update version specifications, or other specifications using differential transmission methods.

In some embodiments, the signal transmission apparatus illustrated in fig. 1 to 2 may also support the specification of the PCIe interface, wherein the positive differential low-speed pin 51, the negative differential low-speed pin 52, the first positive differential high-speed pin 151, the first negative differential high-speed pin 152, the second positive differential high-speed pin 161, and the second negative differential high-speed pin 162 may also be suitable for transmission of the PCIe interface, and the positive differential low-speed pin 51 and the negative differential low-speed pin 52 may transmit clock signals (which may include a positive clock component and a negative clock component) conforming to the specification of the PCIe interface.

In some embodiments, the signal transmission apparatus may support High Definition Multimedia Interface (HDMI), and the control signal pins may be SCL pins, SDA pins, and Hot Plug Detection (Hot Plug Detection) pin 411 or a combination thereof, as shown in fig. 1 and 2. The multiple SCL pins are the SCL/PCIE _ WAKE _ N pin 414 and the real _ SCL pin 419 for transmitting SCL (serial clock) signals; the SDA pins are the SDA/PCIE _ PERST _ N pin 412 and the reload _ SDA pin 420 used to transmit SDA (serial data) signals. The SCL pin and the SDA pin may be used for communication between a signal generating source (e.g., a Digital Video Disc (DVD)) device and a signal receiving end (e.g., a Television (TV)) device, and the source device reads a resolution supported by the playback device through the SCL pin and the SDA pin, so that the source device displays an image frame conforming to the resolution of the playback device. Also, the four pairs of the positive Differential pins 111, 121, 131, 141, 171, 181, 191, 101 and the negative Differential pins 112, 122, 132, 142, 172, 182, 192, 102 can commonly transmit three pairs of Transition Minimized Differential Signaling (TMDS) and a pair of clock signals suitable for the HDMI specification, so as to support the transmission of the HDMI signals.

In some embodiments, the plurality of control signal pins of the signal transmission device may be an irealon _ LINK pin 415, a CLK (AUDIO-SYNC) pin 413, a plurality of pins adapted to a Serial Peripheral Interface (SPI), or a combination selected from the aforementioned items, to transmit the voice and video related control signals between the electronic devices, wherein the plurality of pins adapted to the SPI includes an SPI _ DI pin 416, an SPI _ CS pin 417, an SPI _ WP _ PWM pin 421, an SPI _ DO pin 423, an SPI _ HOLD _ PWM pin 422, and an SPI _ CLK pin 418.

In some embodiments, one of the control signal pins of the signal transmission device may be a system main power enable pin 410, the system main power enable pin 410 transmits a control signal (or called an enable signal) for turning on or off whether the external device provides power, for example, the signal transmission device may be connected between a notebook computer and a tablet computer, the tablet computer may be regarded as an external device of the notebook computer, the tablet computer has a power supply function for supplying power to the notebook computer, and the system main power enable pin 410 transmits a control signal for turning on or off the power supply function. In configuration, the system main power enable pin 410 is located between the positive differential low speed pin 51, the negative differential low speed pin 52, and the first positive differential high speed pin 151, the first negative differential high speed pin 152, the second positive differential high speed pin 161, and the second negative differential high speed pin 162 to isolate the transmission of the low speed data signal and the high speed signal. In some embodiments, the control signal pins are arranged along the same straight direction D1.

In some embodiments, the POWER signal pins 31-34 may be a plurality of low voltage POWER pins and a plurality of high voltage POWER pins, wherein the POWER signal pins 31, 32 are low voltage POWER pins, i.e., HV-POWER pins, and the POWER signal pins 31, 32 supply a low voltage POWER signal related to HV, which may have a voltage of 12 volts (V); the POWER signal pins 33, 34 are high voltage POWER pins, i.e., UHV-POWER pins, and the POWER signal pins 33, 34 supply a UHV-related high voltage POWER signal, which may have a voltage of 350V. In some embodiments, the number of the low voltage power pins and the high voltage power pins can be adjusted according to the actual on-current of the signal transmission device and the differential signal transmission rate.

In some embodiments, as shown in fig. 1 and fig. 2, the plurality of ground pins of the signal transmission device may provide a power signal ground, that is, the high voltage ground pins 61, 62 of the plurality of ground pins may provide a ground for the power signal pins 33, 34 of the high voltage power pin, and the power signal pins 33, 34 and the high voltage ground pins 61, 62 are arranged along the same straight direction D1. Furthermore, the signal transmission device further includes an insulating layer I, the insulating layer I is located between the POWER signal pins 33 and 34 and the high voltage ground pins 61 and 62 of the plurality of ground pins for grounding the POWER signal pins 33 and 34, that is, the POWER signal pins 33 and 34, which are UHV-POWER pins, are located on one side of the insulating layer I, and the high voltage ground pins 61 and 62 are located on the other side of the insulating layer I. Therefore, the insulating layer I disposed between the power signal pins 33 and 34 and the high voltage ground pins 61 and 62 can prevent the over voltage from causing an arc or damage to the signal transmission device. In this embodiment, the insulating layer I is in the form of a pin.

In some embodiments, referring to fig. 1 and 2, the signal transmission device is provided with a metal isolation layer M for isolating the electrical structure from the physical structure (among the pins of the signal transmission device). In detail, as shown in fig. 1 and fig. 2, the power signal pins 31 and 32, the positive differential pins 111, 121, 131, 141, 171, 181, 191, 101, the negative differential pins 112, 122, 132, 142, 172, 182, 192, 102, and the ground pins 21, 22, 23, 24, 25, 26, 27, 28, 29 are located on one side of the metal isolation layer M in the direction D2; the positive differential low-speed pin 51, the negative differential low-speed pin 52, the first positive differential high-speed pin 151, the first negative differential high-speed pin 152, the tenth ground pin 20, the second positive differential high-speed pin 161, the second negative differential high-speed pin 162, the plurality of control signal pins, the power signal pins 33, 34, the high-voltage ground pin 61, the high-voltage ground pin 62, and the insulating layer I are located on the other side of the metal isolation layer M in the direction D2, and the direction D2 is perpendicular to the direction D1 (for example, the direction D2 may be the length direction of the signal transmission device), in other words, the positive differential pins 111, 121, 131, 141, 171, 181, 191, 101, the negative differential pins 112, 122, 132, 142, 172, 182, 192, 102 are arranged in parallel to the positive differential low-speed pin 51 and the negative differential low-speed pin 52 through the metal isolation layer M along the direction D2; the positive differential pins 111, 121, 131, 141, 171, 181, 191, 101, the negative differential pins 112, 122, 132, 142, 172, 182, 192, 102 are arranged in parallel with the first positive differential high-speed pin 151, the first negative differential high-speed pin 152, the second positive differential high-speed pin 161, and the second negative differential high-speed pin 162 along the direction D2 through the metal spacer M; the positive differential pins 111, 121, 131, 141, 171, 181, 191, 101, the negative differential pins 112, 122, 132, 142, 172, 182, 192, 102 and the plurality of control signal pins are arranged in parallel along the direction D2 through the metal isolation layer M; the power signal pins 31, 32 and the power signal pins 33, 34 are arranged in parallel along the direction D2 through the metal isolation layer M. In some embodiments, the metal isolation layer M may be an iron sheet, and may provide a signal ground. Therefore, the metal isolation layer M can prevent the pins at the two sides from interfering with each other, and provide a good reference ground plane to enhance the signal quality and the impedance matching characteristic, and the double rows of parallel pins can also reduce the size of the signal transmission device and improve the convenience of production.

In some embodiments, referring to fig. 1, fig. 2 and fig. 3, all the pins of the signal transmission device may be formed by winding core wires (lines), and the arrangement may be arranged in the same straight direction. For example, as shown in fig. 3, the wire G1 may be a twisted pair with a shielding pin, the wire G2 may be a twisted pair without a shielding pin, the wire G3 may be a thin single core wire, and the wire G4 may be a thick single core wire, and all the pins of the signal transmission device may be bundled as the wires G1, G2, G3, and G4 respectively and arranged in the same straight direction. In other embodiments, as shown in fig. 4, the wires G1-G4 may also be a bundle of windings wrapped in a circular ring shape, that is, the wires G1, G2, G3 and G4 may not be arranged in the same straight direction.

In some embodiments, the signal transmission device includes a housing. The signal transmission device can be designed into one of a male connector or a female connector, the male connector and the female connector correspond to each other, and the signal transmission device serving as the male connector and the signal transmission device serving as the female connector can be connected. Referring to fig. 5A to 5D, fig. 5A and 5B are schematic diagrams of an embodiment of a female connector and a male connector, respectively, fig. 5C is a schematic diagram of a side SA of the signal transmission device in fig. 5A, and fig. 5D is a schematic diagram of a side SB of the signal transmission device in fig. 5B. As shown in fig. 5C and 5D, the ends a and a 'are designed as oblique angles, and the ends B and B' are also designed as oblique angles, so that the two signal transmission devices, which are the female connector and the male connector respectively, can be connected to each other according to the ends a to a 'and the ends B to B', and the oblique angles can be used as a fool-proof mechanism for preventing the connection error between the male connector and the female connector. In other embodiments, the housing includes a chamfered corner and a right corner, and the chamfered corner and the right corner are respectively located at two sides of the housing. Referring to fig. 6A and 6B, fig. 6A is another schematic diagram of the signal transmission device as the female connector, and fig. 6B is another schematic diagram of the signal transmission device as the male connector. As shown in fig. 6A and 6B, the ends C and C 'are designed as right angles, and the ends D and D' are designed as oblique angles, so that two signal transmission devices, which are the female connector and the male connector, respectively, can be connected to each other according to the ends C to C 'and D to D'. In other embodiments, referring to fig. 7A and 7B, fig. 7A is another schematic diagram of a signal transmission device serving as a female connector, and fig. 7B is another schematic diagram of a signal transmission device serving as a male connector. As shown in fig. 7A and 7B, the ends E and E ' are designed as chamfered corners, and the ends F and F ' are designed as right angles, so that two signal transmission devices, which are the female connector and the male connector, respectively, can be connected to each other according to the ends E ' and F ' to F '. Therefore, the signal transmission device can provide signal transmission device combination on different products and separate the joints of the signal transmission device according to the fact that the joints are in different oblique angle forms, and the possibility of mistaken connection between the male joint and the female joint is avoided.

In some embodiments, referring to fig. 8A to 8E, fig. 8A and 8B are an external view and a side view of a female connector, fig. 8C and 8D are an external view and a side view of a male connector, respectively, and fig. 8E is an external view of an embodiment of the female connector corresponding to fig. 8A and 8B and the male connector corresponding to fig. 8C and 8D. As shown in fig. 8A and 8B, the female connector includes a housing O1, a tongue O2, an accommodating space O3 surrounded by the housing, and a plurality of pins, wherein the tongue O2 is disposed in the accommodating space O3, and the tongue O2 is made of an insulating material. In some embodiments, the tongue O2 is embedded with a metal isolation layer M, so that the tongue O2 can be provided with pins, and the metal isolation layer M can be used for electrical isolation of signals on the upper and lower surfaces of the tongue O2 and for reference ground of high-speed signals when the metal isolation layer M is connected to a fixed potential (e.g., ground potential). The female connector is disposed on a substrate Z which is a circuit board. The plurality of pins are the differential pins 111, 121, 131, 141, 171, 181, 191, 101, 51, 151, 161, 112, 122, 132, 142, 172, 182, 192, 102, 52, 152, 162, the ground pins 20-29, 61-62, the power signal pins 31-34, and the control signal pins 410 and 423, which are disposed on the tongue O2 and are respectively disposed on the upper and lower surfaces of the tongue O2, for example, the power signal pins 31, 32, the positive differential pins 111, 121, 131, 141, 171, 181, 191, 101 and the negative differential pins 112, 122, 132, 142, 172, 182, 192, 102 and the ground pins 21, 22, 23, 24, 25, 26, 27, 28, 29 may be disposed on the upper surface of the tongue O2, and the positive differential low-speed pin 51, the negative differential low-speed pin 52, the first positive differential high-speed pin 151, the first negative differential high-speed pin 152, The tenth ground pin 20, the second positive differential high speed pin 161, the second negative differential high speed pin 162, the plurality of control signal pins, the power signal pins 33, 34, the high voltage ground pin 61, the high voltage ground pin 62, and the insulating layer I may be located on the lower surface of the tongue O2. In addition, the metal isolation layer M is also located on the tongue portion O2, and the metal isolation layer M is located between the upper surface and the lower surface of the tongue portion O2. In another example, the pins disposed on the upper surface of the tongue O2 may be disposed on the lower surface instead, and the pins disposed on the lower surface may be disposed on the upper surface instead.

In some embodiments, housing O1 includes a protrusion O11, and protrusion O11 is located on a surface of housing O1, for example, as shown in fig. 8A and 8B, protrusion O11 may be located on an upper surface of housing O1. The protrusion O11 includes a pair of side walls Oa and Ob, and a top wall Oc, the side walls Oa and Ob are respectively connected to the housing O1, and the top wall Oc is connected between the side walls Oa and Ob, whereby the side walls Oa, Ob and the top wall Oc together form an insertion space O4 of the female connector, and the insertion space O4 and the accommodating space O3 are communicated with each other.

In some embodiments, housing O1 includes a plurality of snap buttons O12, wherein the number of snap buttons O12 is adjustable, snap buttons O12 are located on at least one surface of the housing, for example, as shown in fig. 8A and 8B, the number of snap buttons O12 is two, and snap buttons O12 can be located on the upper surface of housing O1, i.e., the same surface as protrusion O11. In other embodiments, the housing O1 includes a plurality of fastening holes O13, wherein the number of the fastening holes O13 is also adjustable, the fastening holes O13 are located on at least one surface of the housing, as shown in fig. 8A and 8B, the number of the fastening holes O13 is two, and the fastening holes O13 can be located on the upper surface of the housing O1, i.e., the same surface as the protrusion O11 and the snap-fastener O12.

In some embodiments, the male connector shown in fig. 8C and 8D includes a housing K1, an insulator T located in the housing K1, a receiving space K2 surrounded by the insulator T, and a plurality of pins disposed on the insulator T. Wherein the plurality of pins are the differential pins 111, 121, 131, 141, 171, 181, 191, 101, 51, 151, 161, 112, 122, 132, 142, 172, 182, 192, 102, 52, 152, 162, the ground pins 20-29, 61-62, the power signal pins 31-34, and the control signal pins 410 and 423, the pins and the insulating layer I are disposed inside the housing K1 (i.e. inside the insulator T) and are respectively disposed on the upper and lower surfaces of the housing K1 (i.e. the upper and lower surfaces inside the insulator T), for example, the power signal pins 31, 32, the positive differential pins 111, 121, 131, 141, 171, 181, 191, 101, and the negative differential pins 112, 122, 132, 142, 172, 182, 192, 102, and the ground pins 21, 22, 23, 24, 25, 26, 27, 28, 29 can be disposed on the upper surface inside the housing K1 (i.e. the upper surface inside the insulator T), and the positive differential low-speed pin 51, the negative differential low-speed pin 52, the first positive differential high-speed pin 151, the first negative differential high-speed pin 152, the tenth ground pin 20, the second positive differential high-speed pin 161, the second negative differential high-speed pin 162, the plurality of control signal pins, the power signal pins 33, 34, the high-voltage ground pin 61, the high-voltage ground pin 62, and the insulating layer I may be located on a lower surface of the inside of the case K1 (i.e., a lower surface of the inside of the insulator T). In another example, the pins disposed on the inner upper surface of the casing K1 may be disposed on the lower surface instead, and the pins disposed on the inner lower surface may be disposed on the upper surface instead.

In some embodiments, housing K1 includes a protrusion K11, and protrusion K11 is located on a surface of housing K1, for example, as shown in fig. 8C and 8D, protrusion K11 may be located on an upper surface of housing K1. The projection K11 includes a pair of side walls Ka, Kb and a top wall Kc, the side walls Ka, Kb are respectively connected to the housing K1, and the top wall Kc is connected between the side walls Ka, Kb, whereby the side walls Ka, Kb and the top wall Kc together form the insertion space K3 of the male connector.

In some embodiments, the housing K1 includes a plurality of grooves K12, wherein the number of the grooves K12 corresponds to the number of snap buttons O12 of the female connector to be connected thereto, and the position of the groove K12 on the housing K1 corresponds to the position of the snap button O12 on the housing O1, for example, as shown in fig. 8C and 8D, the number of the grooves K12 is two, and the grooves K12 and the snap buttons O12 are both disposed on the upper surface of the housing, and the grooves K12 and the protrusions K11 are disposed on the same surface of the housing K1. In other embodiments, the housing K1 includes a plurality of fastening holes K13, wherein the number of the fastening holes K13 corresponds to the number of the fastening holes O13 of the female connector to be connected thereto, and the position of the fastening hole K13 on the housing K1 corresponds to the position of the fastening hole O13 on the housing O1, as shown in fig. 8C, the number of the fastening holes K13 is two, and the fastening hole K13 may be located on the upper surface of the housing K1, i.e. the same surface as the protrusion K11 and the groove K12.

In some embodiments, referring to fig. 8E, fig. 8E is a schematic view of a structure of the female connector of fig. 8A (fig. 8B) and the male connector of fig. 8C (fig. 8D) in butt joint (connection in a butt joint direction SV). When the two signal transmission devices are connected, the housing O1 of the female connector surrounds the housing K1 of the male connector, in other words, a plurality of surfaces of the housing O1 cover a plurality of surfaces of the housing K1, the housing K1 is located inside the housing O1, in detail, the housing O1 is connected to the housing K1, the protrusion O11 is connected to the protrusion K11 and the protrusion O11 covers the protrusion K11, and the tongue O2 of the female connector is inserted into the receiving space K2 of the male connector, so that the pins of the female connector are electrically connected to the pins of the male connector, respectively. In addition, the snap O12 and the groove K12 are connected with each other in a snap fit manner, and the snap hole O13 and the snap hole K13 are also connected with each other in a snap fit manner, so that the female connector and the male connector cannot be easily separated after being butted.

In some embodiments, referring to fig. 8F, fig. 8F is a top view of the male connector and the female connector of fig. 8E not yet connected. As can be seen, the protrusion O11 of the female connector is located at the left position (in the horizontal direction SH in fig. 8F) of the center of the housing O1, that is, the distance from the central axis Y of the protrusion O11 to the right inner side surface SE of the housing O1 (hereinafter referred to as the first distance) is a length a1, the distance from the central axis Y of the protrusion O11 to the left inner side surface SF of the housing O1 (hereinafter referred to as the second distance) is a length a2, and the length a1 is greater than or equal to the length a 2. Similarly, the protrusion K11 of the male connector is located at a position (horizontal direction SH according to fig. 8F) that is left from the central axis Y of the housing K1, that is, the distance from the central axis Y of the protrusion K11 to the right outer side SG of the housing K1 (hereinafter referred to as the third distance) is a length a3, the distance from the protrusion K11 to the left outer side SH of the housing K1 (hereinafter referred to as the fourth distance) is a length a4, and the length a3 is greater than or equal to the length a 4. The first distance corresponds to the third distance, and the second distance corresponds to the fourth distance, so that when the male connector is connected with the female connector, the shell of the female connector surrounds the shell of the male connector.

In some embodiments, the position of the protrusions O11, K11 on the housings O1, K1 can be adjusted according to the user's design, as long as the protrusion O11 of the female housing O1 can smoothly cover the protrusion K11 of the male housing K1 when the female and male connectors are mated. In some embodiments, the positions of the protrusions O11, K11 on the housings O1, K1 may also be configured as shown in fig. 9, 10 or 11. In fig. 9, length b1 of the first distance is greater than or equal to length b2 of the second distance, length b3 of the third distance is greater than or equal to length b4 of the fourth distance, and compared to fig. 8F, length b1 is less than length a1, length b2 is greater than length a2, length b3 is less than length a3, and length b4 is greater than length a 4. In other embodiments, in fig. 10, the protrusion O11 may also be located at the right position (according to the horizontal direction SH of fig. 8F) of the center of the housing O1, the length c1 of the first distance is less than or equal to the length c2 of the second distance, and the length c3 of the third distance is less than or equal to the length c4 of the fourth distance. In other embodiments, in fig. 11, length d1 of the first distance is less than or equal to length d2 of the second distance, length d3 of the third distance is less than or equal to length d4 of the fourth distance, and compared to fig. 10, length d1 is less than length c1, length d2 is greater than length c2, length d3 is less than length c3, and length d4 is greater than length c 4. Therefore, after the distance between the protrusions O11 and K11 and the two sides of the housings O1 and K1 is designed, only a specific male connector can be connected to a specific female connector, i.e. the position of the protrusion K11 of the specific male connector on the housing K1 can correspond to the position of the protrusion O11 of the specific female connector on the housing O1, so that the design of the protrusions O11 and K11 can provide the combination of signal transmission devices on different products and separate the signal transmission device connectors, so as to prevent the possibility of incorrect connection between the male connector and the female connector of different products.

In some embodiments, the housing of the signal transmission device may also be designed with a protrusion and a chamfer, that is, as shown in fig. 8A to 8E, the H end and the H 'end may also be designed as chamfer, the J end and the J' end may also be designed as chamfer, and the two signal transmission devices, which are the female connector and the male connector respectively, may be connected to each other according to the H end to the H 'end, the J end to the J' end, the housing O1 to the housing K1, and the protrusion O11 to the protrusion K11, so that more signal transmission devices may be combined to achieve the fool-proof effect.

In some embodiments, the number of the protrusions O11 and K11 may not be limited, but the number of the protrusions O11 and K11 may be plural according to the design of the user, the number of the protrusions O11 is equal to the number of the protrusions K11, and the position of each protrusion O11 on the housing O1 corresponds to the position of each protrusion K11 on the housing K1.

In some embodiments, referring to fig. 12, fig. 12 illustrates a transmission line and an electronic device N suitable for the transmission line. The transmission line includes a signal transmission device P, Q and a connection portion L, wherein the signal transmission device P, Q is disposed at two ends of the transmission line, and the connection portion L is connected between the signal transmission device P and the signal transmission device Q. The electronic device N includes a signal transmission device R corresponding to the signal transmission device P, Q of the transmission line. Since the signal transmission device P, Q, R is designed as one of a male connector and a female connector, respectively, the male connector can be connected with the female connector, so that the signal transmission device P or the signal transmission device Q can be connected with the signal transmission device R of the electronic device N, which can be a notebook computer, a mobile phone, a tablet, a monitor or other video-audio related devices. For example, when the signal transmission device P as the male connector is connected to the signal transmission device R as the female connector and the signal transmission device Q as the female connector is connected to the signal transmission device Q as the male connector of another electronic device, the other electronic device can transmit signals from the signal transmission device Q of the transmission line to the electronic device N through the connection portion L, and then through the signal transmission device P and the signal transmission device R.

In some embodiments, both signal transmission devices P, Q of the transmission line are both male connectors or both female connectors. In some embodiments, the pin assignment definitions (pin assignments) of the two signal transmitting devices P, Q of the transmission line are the same or different.

In some embodiments, for example, the insulation layer I is not designed to be in the form of pins, and the total number of pins is 52, as shown in fig. 2 (from top to bottom and from left to right), pins 1, 4, 7, 10, 13, 16, 19, 22, 25, 33, 49, 50 are GND; pins 2, 3, 5, 6, 8, 9, 11, 12, 14, 15, 17, 18, 20, 21, 23, 24 are P3_ RTK1_ P, P3_ RTK1_ M, P3_ RTK0_ P, P3_ RTK0_ M, P2_ RTK1_ P, P2_ RTK1_ M, P2_ RTK0_ P, P2_ RTK0_ M, P1_ RTK1_ P, P1_ 1_ M, P1_ RTK0_ P, P1_ RTK0_ M, P0_ RTK1_ P, P0_ RTK1_ M, P0_ RTK0_ P, P0_ RTK0_ M, respectively; the 26 th pin and the 27 th pin are HV _ POWER; the 51 st pin and the 52 th pin are UHV _ POWER; pins 28-32, 34-48 are USB _ DM/REFCLK _ M _ PCIE, USB _ DP/REFCLK _ P _ PCIE, SYSTEM _ MAIN _ POWER _ EN, USB _ SSRX _ M/PCIE _ HSIN, USB _ SSRX _ P/PCIE _ HSIP, USB _ SSTX _ M/PCIE _ HSON, USB _ SSTX _ P/PCIE _ HSOP, HOT _ PLUG _ DET, SDA/PCIE _ PERST N, AUDIO _ SYNC _ CLK, SCL/PCIE _ WAKE _ N, iRealOne _ LINK, SPI _ DI, SPI _ CS, SPI _ CLK, REALONE _ SCL, REALONE _ SDA, SPI _ PWM, SPI _ HOLD _ PWM, SPI _ DO, respectively.

In some embodiments, for example, the insulation layer I is not designed to be in the form of pins, and the total number of pins is 52, as shown in fig. 13A (from top to bottom and from left to right), pins 1, 4, 7, 10, 13, 16, 19, 22, 25, 33, 49, 50 are GND; pins 2, 3, 5, 6, 8, 9, 11, 12, 14, 15, 17, 18, 20, 21, 23, 24 are P3_ RTK1_ P, P3_ RTK1_ M, P3_ RTK0_ P, P3_ RTK0_ M, P2_ RTK1_ P, P2_ RTK1_ M, P2_ RTK0_ P, P2_ RTK0_ M, P1_ RTK1_ P, P1_ 1_ M, P1_ RTK0_ P, P1_ RTK0_ M, P0_ RTK1_ P, P0_ RTK1_ M, P0_ RTK0_ P, P0_ RTK0_ M, respectively; the 26 th pin and the 27 th pin are HV _ POWER; the 51 st pin and the 52 th pin are UHV _ POWER; pins 28-32, 34-48 are USB _ DM/REFCLK _ M _ PCIE, USB _ DP/REFCLK _ P _ PCIE, SYSTEM _ MAIN _ POWER _ EN, USB _ SSRX _ M/PCIE _ HSIN, USB _ SSRX _ P/PCIE _ HSIP, USB _ SSTX _ M/PCIE _ HSON, USB _ SSTX _ P/PCIE _ HSOP, HOT _ PLUG _ DET, SDA/PCIE _ PERST N, AUDIO _ SYNC _ CLK, SCL/PCIE _ WAKE _ N, iRealOne _ LINK, SPI _ DI, SPI _ CS, SPI _ CLK, REALONE _ SCL, REALONE _ SDA, SPI _ PWM, SPI _ HOLD _ PWM, SPI _ DO, respectively.

In some embodiments, for example, the insulation layer I is not designed to be in the form of pins, and the total number of pins is 52, as shown in fig. 13B (from top to bottom and from left to right), pins 1, 4, 7, 10, 13, 16, 19, 22, 25, 33, 49, 50 are GND; pins 2, 3, 5, 6, 8, 9, 11, 12, 14, 15, 17, 18, 20, 21, 23, 24 are P0_ RTK0_ M, P0_ RTK0_ P, P0_ RTK1_ M, P0_ RTK1_ P, P1_ RTK0_ M, P1_ RTK0_ P, P1_ RTK1_ M, P1_ RTK1_ P, P2_ RTK0_ M, P2_ 0_ P, P2_ RTK1_ M, P2_ RTK1_ P, P3_ RTK0_ M, P3_ RTK0_ P, P3_ RTK1_ M, P3_ RTK1_ P, respectively; the 26 th pin and the 27 th pin are HV _ POWER; the 51 st pin and the 52 th pin are UHV _ POWER; pins 28-32, 34-48 are USB _ DP/REFCLK _ P _ PCIE, USB _ DM/REFCLK _ M _ PCIE, SYSTEM _ MAIN _ POWER _ EN, USB _ SSTX _ P/PCIE _ HSIP, USB _ SSTX _ M/PCIE _ HSIN, USB _ SSRX _ P/PCIE _ HSOP, USB _ SSRX _ M/PCIE _ HSON, HOT _ PLUG _ DET, SDA/PCIE _ PERST N, AUDIO _ SYNC _ CLK, SCL/PCIE _ WAKE _ N, iRealOne _ LINK, SPI _ DI, SPI _ CS, SPI _ CLK, REALONE _ SCL, REALONE _ SDA, SPI _ PWM, SPI _ HOLD _ PWM, SPI _ DO, respectively.

In some embodiments, pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 31-35 may be left unused, i.e., the total number of pins is 35, in accordance with the design of fig. 2. That is, as shown in fig. 1, the 1 st, 4 th, 7 th, 10 th, 13 th, 32 th, 33 th pins are GND; pins 2, 3, 5, 6, 8, 9, 11 and 12 are respectively P1_ RTK1_ P, P1_ RTK1_ M, P1_ RTK0_ P, P1_ RTK0_ M, P0_ RTK1_ P, P0_ RTK1_ M, P0_ RTK0_ P, P0_ RTK0_ M; the 14 th and 15 th pins are HV _ POWER; pins 34 and 35 are UHV _ POWER; pins 16-31 are USB _ DM/REFCLK _ M _ PCIE, USB _ DP/REFCLK _ P _ PCIE, SYSTEM _ MAIN _ POWER _ EN, HOT _ PLUG _ DETECT, SDA/PCIE _ PERST _ N, AUDIO _ SYNC _ CLK, SCL/PCIE _ WAKE _ N, iRealOne _ LINK, SPI _ DI, SPI _ CS, SPI _ CLK, REALONE _ SCL, REALONE _ SDA, SPI _ WP _ PWM, SPI _ HOLD _ PWM, SPI _ DO, respectively.

In some embodiments, pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 31-35 may be unused (also referred to as empty pins, NC, Not connected), i.e., the total number of pins is 35, according to the design of fig. 13A. That is, as shown in fig. 14A, the 1 st, 4 th, 7 th, 10 th, 13 th, 32 th, 33 th pins are GND; pins 2, 3, 5, 6, 8, 9, 11 and 12 are respectively P1_ RTK1_ P, P1_ RTK1_ M, P1_ RTK0_ P, P1_ RTK0_ M, P0_ RTK1_ P, P0_ RTK1_ M, P0_ RTK0_ P, P0_ RTK0_ M; the 14 th and 15 th pins are HV _ POWER; pins 34 and 35 are UHV _ POWER; pins 16-31 are USB _ DM/REFCLK _ M _ PCIE, USB _ DP/REFCLK _ P _ PCIE, SYSTEM _ MAIN _ POWER _ EN, HOT _ PLUG _ DETECT, SDA/PCIE _ PERST _ N, AUDIO _ SYNC _ CLK, SCL/PCIE _ WAKE _ N, iRealOne _ LINK, SPI _ DI, SPI _ CS, SPI _ CLK, REALONE _ SCL, REALONE _ SDA, SPI _ WP _ PWM, SPI _ HOLD _ PWM, SPI _ DO, respectively.

In some embodiments, pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 31-35 may be unused (also referred to as empty pins, NC, Not connected), i.e., the total number of pins is 35, according to the design of fig. 13B. That is, as shown in fig. 14B, the 1 st, 4 th, 7 th, 10 th, 13 th, 32 th, 33 th pins are GND; pins 2, 3, 5, 6, 8, 9, 11 and 12 are respectively P0_ RTK0_ M, P0_ RTK0_ P, P0_ RTK1_ M, P0_ RTK1_ P, P1_ RTK0_ M, P1_ RTK0_ P, P1_ RTK1_ M, P1_ RTK1_ P; the 14 th and 15 th pins are HV _ POWER; pins 34 and 35 are UHV _ POWER; pins 16-31 are USB _ DP/REFCLK _ P _ PCIE, USB _ DM/REFCLK _ M _ PCIE, SYSTEM _ MAIN _ POWER _ EN, HOT _ PLUG _ DETECT, SDA/PCIE _ PERST _ N, AUDIO _ SYNC _ CLK, SCL/PCIE _ WAKE _ N, iRealOne _ LINK, SPI _ DI, SPI _ CS, SPI _ CLK, REALONE _ SCL, REALONE _ SDA, SPI _ WP _ PWM, SPI _ HOLD _ PWM, SPI _ DO, respectively.

Please refer to fig. 15A-20B, which are schematic diagrams illustrating an embodiment of the disclosed signal transmitting apparatus. The signal transmission devices shown in fig. 15A and 15B can be applied to the two signal transmission devices P, Q of the transmission line shown in fig. 12, respectively; the signal transmission devices of fig. 16A and 16B can be applied to the two signal transmission devices P, Q of the transmission line of fig. 12, respectively; the signal transmission devices of fig. 17A and 17B can be applied to the two signal transmission devices P, Q of the transmission line of fig. 12, respectively; the signal transmission devices of fig. 18A and 18B may be applied to the two signal transmission devices P, Q of the transmission line of fig. 12, respectively; the signal transmission devices of fig. 19A and 19B can be applied to the two signal transmission devices P, Q of the transmission line of fig. 12, respectively; the signal transmission devices of fig. 20A and 20B can be applied to the two signal transmission devices P, Q of the transmission line of fig. 12, respectively.

The pins that are not defined by the pins in fig. 1 and fig. 14A to fig. 20B (e.g., the first 12 pins (pins 1-12) at the top left side and the 4 th to 8 th pins (pins 31-35) at the right side in fig. 1) are empty pins (NC, not-connected), but not limited thereto. In some embodiments, the dummy pin can be electrically connected to a power or ground terminal, or can be a General Purpose Input/Output (General Purpose Input/Output) pin, or can be a pin for other purposes without affecting electrical characteristics.

The pins of the signal transmission device in fig. 15A are GND, GPIO1, GPIO2, GND, irelon _ SCL, irelon _ SDA, GND, SDA, SCL, GND, GPIO3/PDM _ D1, GPIO4/PDM _ D0, GND, P1_ RTK1_ RTK1_ M, GND, P869 _ RTK0_ P, P1_ RTK0_ M, GND, P0_ RTK1_ P, P0_ RTK1_ M, GND, P0_ 0_ M, HV _ POWER, RTK _ POWER, USB _ DM, USB SYSTEM _ MAIN _ POWER _ ne, uh3672 _ 0_ M, HV _ POWER, USB _ DP, USB SYSTEM _ POWER _ MAIN _ POWER _ NC, uhp 0_ POWER, insert _ 0_ POWER _ M, HV _ POWER _ NC, uhp _ POWER _ 0_ NC, hnc _ POWER _ 0_ NC, GND _ POWER _ 0_ NC, GND, uh _ POWER _ 0_ NC, GND _ POWER _ 0_ NC, GND, uh _ 0_ POWER _ 0, HV _ NC, UHV _ NC, HV _ 0, HV _ NC, HV _ POWER, HV _ 0_ NC, HV _ 0, HV _ NC, GND, HV _ 0_ NC, HV _ NC, GND, HV _ POWER, GND, HV _ 0_ soc _ 0, HV _ 0_ NC, HV _ NC, GND, HV _ POWER, GND, HV _ 0_ soc _ 0, GND, HV _ POWER, GND, HV _ 0, HV _ POWER, HV _ 0_ NC, GND, HV _ NC, GND, HV _ 0, HV _ POWER, GND, HV _ NC, HV _ POWER, GND, HV _ 0, GND, HV _ NC, HV _ POWER, GND, HV _ POWER, HV _ 0, HV _ POWER, HV _ NC, GND, HV _ 0, GND, HV _ 0, HV _ NC, HV _ 0, HV _ NC, GND, HV _ POWER, GND, HV _ 0, HV _ NC, HV _ POWER, GND, HV _ 0, GND, HV _ NC. Wherein NC represents a null pin, PHYSICAL isolation represents PHYSICAL insulation for avoiding arcing or electrical coupling effects caused by excessive voltage between the POWER signal pin and the ground pin, HOT _ PLUG _ DETECT represents HOT PLUG detection, GND represents ground, and POWER represents POWER. PDM denotes a digital microphone interface (Pulse sensitivity Modulation), SCL/SDA denotes a set of I2C interfaces, ireion _ SCL and ireion _ SDA denote a set of dedicated I2C interfaces of the signal transmission device, GPIO denotes a general-purpose output/input terminal, and P0_ RTK0_ M and P0_ RTK0_ P denote the same set of differential signal pins of the signal transmission device. HV _ POWER and HV _ POWER2 represent two high voltage POWER supplies transmitted by the signal transmission device, UHV _ POWER and UHV _ GND represent the ultra high voltage POWER supply and the corresponding ground signal transmitted by the signal transmission device, respectively, SYSTEM _ MAIN _ POWER _ EN represents a signal for controlling the on and off of the MAIN POWER supply, and ireion _ LINK represents a signal used by the signal transmission device for transmitting a specific packet.

The pins of the signal transmission device of fig. 15B are GND, GPIO1, GPIO2, GND, irelone _ SCL, irelone _ SDA, GND, SDA, SCL, GND, GPIO3/PDM _ D1, GPIO4/PDM _ D0, GND, P0_ RTK0_ M, P0_ RTK0_ P, GND, P0_ RTK1_ M, P0_ RTK1_ P, GND, P1_ RTK0_ M, P1_ RTK0_ P, GND, P1_ 1_ RTK1_ P, GND, HV _ POWER, USB _ DP, USB _ DM, SYSTEM _ MAIN _ POWER _ EN, RTK1_ 1_ RTK1_ P, GND, HV _ POWER, HV _ pc, USB _ DM, SYSTEM _ MAIN _ POWER _ EN _ n _ POWER _ EN, RTK, HV _ 1, HV _ POWER, HV _ NC, GND, uhp _ P, HV _ P _ POWER _ h _ P, HV _ P _ r _ POWER, HV _ amplifier, uh _ amplifier, uh _ amplifier, uh _ amplifier, uhp _ amplifier, HV _ amplifier, hnc, uhp _ amplifier, hnc, hnic _ 72, hnc, hnic _ amplifier, hnic _ 72, hnc, hnic _ NC, hnic _ 72, hnic, GND, hnic _ NC, uhp, hnic _ NC, GND, hnic _ NC, hnic, GND, hnic _ NC, hnic, GND, hnic, GND, hnic _ NC, hnic _ 72, hnic _ NC, hnic _ 72, hnic _ NC, GND, hnic _ 72, GND, hnic _ NC, GND, hnic _ NC, hnic _ 72, hnic _ NC, hnic, GND, hnic _ NC, GND, hnic _ NC, hnic _.

The pins of the signal transmission device of fig. 16A are GND, GPIO1, GPIO2, GND, irelone _ SCL, irelone _ SDA, GND, SDA, SCL, GND, GPIO3/PDM _ D1, GPIO4/PDM _ D0, GND, NC, GND, P0_ RTK1_ P, P0_ 1_ M, GND, P0_ RTK0_ P, P0_ RTK0_ M, GND, NC, GND, HV _ POWER, USB _ DM, USB _ DP, SYSTEM _ MAIN _ POWER _ EN, NC, insn, NC, HOT _ PLUG _ det, irelone _ LINK, GPIO 2_ PDM _ CLK, NC, HV _ POWER _ 596, POWER, HV _ 638, POWER, NC, HOT _ POWER _ P, GND, UHV _ P _ r2, UHV _ POWER, GND, UHV _ r _ P _ POWER _ r _ sw _ 596, UHV _ r _ P, UHV _ P _ M _ POWER _ n _ P _ n _ r _ n _ P _ n _ r _ n _ NC, uht _ P _ r _ P _ r _ NC, HV _ P.

The pins of the signal transmission device of fig. 16B are GND, GPIO1, GPIO2, GND, irelone _ SCL, irelone _ SDA, GND, SDA, SCL, GND, GPIO3/PDM _ D1, GPIO4/PDM _ D0, GND, NC, GND, P0_ RTK0_ M, P0_ 0_ P, GND, P0_ RTK1_ M, P0_ RTK1_ P, GND, NC, GND, HV _ POWER, USB _ DP, USB _ DM, SYSTEM _ MAIN _ POWER _ EN, NC, insn, NC, HOT _ PLUG _ det, irei realone _ LINK, GPIO 2_ PDM _ CLK, NC, HV _ POWER _ 63596, HV _ POWER, HV _ oscillator 638, POWER, NC, HOT _ POWER _ sync, GND, UHV _ P _ r2, UHV _ POWER, GND, UHV _ r _ P, UHV _ POWER _ CLK, UHV _ r 638, UHV _ POWER _ r, UHV _ r _ P, UHV _ P, NC, GND, RTK, and uht _ P _.

The pins of the signal transmission device of fig. 17A are GND, GPIO1, GPIO2, GND, irelone _ SCL, irelone _ SDA, GND, SDA, SCL, GND, GPIO3/PDM _ D1, GPIO4/PDM _ D0, GND, NC, GND, P0_ RTK1_ P, P0_ RTK1_ M, GND, P0_ RTK0_ P, P0_ RTK0_ M, GND, HV _ POWER, USB _ DM, USB _ DP, SYSTEM _ MAIN _ POWER _ EN, NC, insn, NC, HOT _ PLUG _ det, irelone _ LINK, GPIO 2_ PDM _ CLK, NC, HV _ POWER _ 596, por 638, HV _ POWER, NC, HOT _ POWER _ det _ 596, GND, uhr _ POWER _ 2, UHV _ POWER, GND, UHV _ r _ P, UHV _ P _ RTK0_ M, GND, NC, UHV _ POWER _ sw _ CLK, UHV _ majn _ P _ POWER _ sw _ ref _ CLK, NC, HV _ ref, GND, UHV _ ref, GND, UHV _ ref _ P _ M, and GND, UHV _ P _ M _ P _ M _ P _ M _ P _ M _ P _ M _ P _ M _ P _ M _ P _ M _.

The pins of the signal transmission device of fig. 17B are GND, GPIO1, GPIO2, GND, irelone _ SCL, irelone _ SDA, GND, SDA, SCL, GND, GPIO3/PDM _ D1, GPIO4/PDM _ D0, GND, NC, GND, P0_ RTK0_ M, P0_ RTK0_ P, GND, P0_ RTK1_ M, P0_ RTK1_ P, GND, HV _ POWER, USB _ DP, USB _ DM, SYSTEM _ MAIN _ POWER _ EN, NC, insn, NC, HOT _ PLUG _ det, irelone _ LINK, GPIO 2_ PDM _ CLK, NC, HV _ POWER _ 596, por 638, HV _ POWER, NC, HOT _ POWER _ det _ 596, GND, uhr _ POWER _ 2, UHV _ POWER, GND, UHV _ r _ P, UHV _ POWER _ r 638, UHV _ POWER _ r, GND, UHV _ r _ P, UHV _ P _ RTK, GND, UHV _ P _ RTK, and UHV _ POWER _ P.

The pins of the signal transmission device of FIG. 18A from the 1 st pin to the 54 th pin are GND, GPIO1, GPIO2, GND, iRealOne _ SCL, iRealOne _ SDA, GND, SDA, SCL, GND, GPIO3/PDM _ D1, GPIO4/PDM _ D0, GND, P1_ RTK1_ P, P1_ RTK1_ M, GND, P1_ RTK0_ P, P1_ RTK0_ M, GND, P0_ RTK1_ 1_ RTK1_ M, GND, HV _ POWER, USB _ DM/REFCLK _ PCIE _ M _ STD, USB _ DP/REFCP _ P _ PCIE, SYSTEM _ POIN _ POEN, USB _ SSIN/SSIN, PCIE _ HV _ VSS/USB _ POND, HSUPON _ PSIP _ GND, HSUPON/PSITX _ 1, PCIE _ PSITCH _ PSITH _ PSITCH, SSON _ PSITCH _ PSK _ 1, HSPOX _ PSK _ 1, SSON _ PSK _ 1, SSON _ PSITH _ PSK, UHV _ GND, PHILICAL INSULATOR, UHV _ POWER, and UHV _ POWER.

The pins of the signal transmission device of FIG. 18B from the 1 st pin to the 54 th pin are GND, GPIO1, GPIO2, GND, iRealOne _ SCL, iRealOne _ SDA, GND, SDA, SCL, GND, GPIO3/PDM _ D1, GPIO4/PDM _ D0, GND, P0_ RTK0_ M, P0_ RTK0_ P, GND, P0_ RTK1_ M, P0_ RTK1_ P, GND, P1_ RTK0_ 0_ RTK0_ P, RTK, P0_ 0_ RTK0_ P, GND, HV _ POWER, SSTP _ DP/REFCLK _ PCIE _ P _ PSI _ PSD, USB _ DM/REFCP, USB _ DM _ M _ PCIE, SYSTEM _ HV _ POIN _ HV _ PSK _ HV _ PSK, USB _ HV _ PSK _ HV _ PSK, USB _ HV _ PSK, UHV _ GND, PHILICAL INSULATOR, UHV _ POWER, and UHV _ POWER.

The pins of the signal transmission device in FIG. 19A are GND, GPIO1, GPIO2, GND, iRealOne _ SCL, iRealOne _ SDA, GND, SDA, SCL, GND, GPIO3/PDM _ D1, GPIO4/PDM _ D0, GND, NC, GND, P0_ RTK1_ P, P0_ SST 1_ M, GND, P0_ RTK0_ P, P0_ RTK0_ M, GND, NC, GND, HV _ POWER, USB _ DM/REFCLK _ M _ PCIE, USB _ DP/REFCLK _ PCIE _ MAIN, USB _ SSRX _ M/PCIE _ HSRX _ P/PCIE, USB _ HSRX _ P/VSS _ GND, UHSSRX _ VSS _ NSX _ SSNO _ SSN, UHSSRX _ VSS _ P/GND, PCIE _ VSS, USB _ VSS, UHV _ POWER, and UHV _ POWER.

The pins of the signal transmission device of FIG. 19B are GND, GPIO1, GPIO2, GND, iRealOne _ SCL, iRealOne _ SDA, GND, SDA, SCL, GND, GPIO3/PDM _ D1, GPIO4/PDM _ D0, GND, NC, GND, P0_ RTK0_ M, P0_ 0_ P, GND, P0_ RTK1_ M, P0_ RTK1_ P, GND, NC, GND, HV _ POWER, USB _ DP/REFCLK _ P _ PCIE, USB _ DM/REFCLK _ PCIE _ MAIN, USB _ SSTX _ HSIP, USB _ HSX _ P/SSTR _ HSIP, USB _ HV _ HSX _ M/HSM _ GND/SSIN, USB _ SSIN/SHSOPT _ INS, SSP _ SSOP _ SUSPEN _ POS _ SOR, HSONP _ SOR _ GND, PCIE _ SOCK _ SSOR _ SSUT _ SSP, SSOP _ SOCK _ SSOR _ SSON _ GND, USB _ SOCK _ SSON _ SSOR _ SSON _ SSW _ SSON _ SSW _ SSON, PCIE _ SSON _ PSK _ PSN, SSON _ PSK _ PSN _ PSK _ PSN, PSK _ PSN, PSK _ PSN, PSN _ PSK _ PSN, PSN _ PSK _ PSN, PSK _ PSN _ PSK _ PS, UHV _ POWER, and UHV _ POWER.

The pins of the signal transmission device in FIG. 20A are GND, GPIO1, GPIO2, GND, iRealOne _ SCL, iRealOne _ SDA, GND, SDA, SCL, GND, GPIO3/PDM _ D1, GPIO4/PDM _ D0, GND, NC, GND, P0_ RTK1_ P, P0_ RTK1_ M, GND, P0_ RTK0_ P, P0_ RTK0_ M, GND, HV _ POWER, USB _ DM/REFCLK _ M _ PCIE, USB _ DP/REFCIRCIP _ P _ INS, SYSTEM _ MAIN _ POWER _ EN, USB _ SSRX _ M/PCIE _ HSRX _ P/VSS, USB _ HV _ VSS _ P _ NV _ VSS _ NV _ STP _ NV _ SSON, PCIE _ VSS _ P/VSS _ P/VSS, PCIE _ VSS, USB _ VSS, UHV _ POWER, and UHV _ POWER.

The pins of the signal transmission device in FIG. 20B are GND, GPIO1, GPIO2, GND, iRealOne _ SCL, iRealOne _ SDA, GND, SDA, SCL, GND, GPIO3/PDM _ D1, GPIO4/PDM _ D0, GND, NC, GND, P0_ RTK0_ M, P0_ RTK0_ P, GND, P0_ RTK1_ M, P0_ RTK1_ P, GND, HV _ POWER, USB _ DM/REFCLK _ M _ PCIE, USB _ DP/REFCIRCOP _ P _ INS, SYSTEM _ MAIN _ POWER _ EN, USB _ SSTX _ P/PCIE _ HSIP, USB _ HV _ HSX _ M/HSM _ PSIN, PCIE _ SSIN/SSOP _ SSOP, SYSTELK _ SOMP _ POS _ SOR _ GND, UHSSOP _ SOPT _ SOUT _ SSOM _ SSON _ SNOW _ SOUT _ SNOW, PCIE _ SOCK _ PSUT _ 27, PCIE _ SOCK _ PSUT _ SNOW _ PSEU _ PSEUR, PCIE _ PSEU _ PSEUR, SSP _ PSEU, USB _ PSEU _ PSEUP _ PSN, USB _ PSN, SSP _ PSEUP _ PSN, USB, UHV _ POWER, and UHV _ POWER.

In some embodiments, the number of the core wires can be adjusted according to different applications and embodiments, for example, the number of the pins 52 and all the pins are used, the signal transmission device can be formed by 50 core wires, and for example, the number of the pins 52 and 35 pins are used, the signal transmission device can be formed by 33 core wires. The user can select different winding combinations of the differential pins and the control signals according to the specification types to be supported by the user, so that the purpose of transmitting data and power signals is achieved.

In summary, according to an embodiment of the signal transmission device of the present disclosure, the same pair of differential signal pins is disposed between the two ground pins, so that signal crosstalk can be avoided and a better impedance matching characteristic can be obtained. Furthermore, the grounding pin is arranged at the extreme edge position end of the pin accommodating space, so that the Interference of the differential signal by noise outside the signal transmission device can be avoided, the energy of the differential signal transmitted to the outside of the signal transmission device in an Electromagnetic wave form is reduced, and the Electromagnetic Interference (EMI) is reduced, thereby achieving the preferable Electromagnetic compatibility (EMC) and electrostatic discharge (ESD) effects. The signal transmission device can improve transmission quality, and the transmission line can transmit signals to the electronic device more efficiently. Moreover, the signal transmission device can support various existing transmission specifications, such as a USB specification, a PCIe specification, a Display Port specification, and an HDMI specification, so that a single signal transmission device transmits a larger data transmission amount in a multiplexing manner, and a user does not need to prepare various transmission lines supporting different specifications, thereby facilitating convenience in use.

Although the present disclosure has been described with reference to exemplary embodiments, it should be understood that various changes and modifications can be made without departing from the spirit and scope of the disclosure, and therefore the scope of the disclosure should be limited only by the appended claims.

Claims (10)

1. A signal transmission apparatus capable of transmitting a plurality of sets of data streams, comprising:

a first positive differential pin of the positive differential pins is used for transmitting a positive signal component of a first differential signal, and a second positive differential pin of the positive differential pins is used for transmitting a positive signal component of a second differential signal;

a first negative differential pin of the plurality of negative differential pins is used for transmitting a negative signal component of a first differential signal, and a second negative differential pin of the plurality of negative differential pins is used for transmitting a negative signal component of a second differential signal;

a positive differential low-speed pin for transmitting a positive signal component which is a low-speed differential signal;

a negative differential low-speed pin for transmitting a negative signal component of the low-speed differential signal;

a plurality of ground pins;

a plurality of power signal pins;

a plurality of control signal pins; and

a metal isolation layer;

the first positive differential pin and the first negative differential pin are located on one side of a first grounding pin in the plurality of grounding pins, the second positive differential pin and the second negative differential pin are located on the other side of the first grounding pin, the plurality of positive differential pins and the plurality of negative differential pins are located on one side of the metal isolation layer, and the positive differential low-speed pin, the negative differential low-speed pin and the plurality of control signal pins are located on the other side of the metal isolation layer.

2. The signal transmission device as claimed in claim 1, wherein the second positive differential pin and the second negative differential pin are further located between the first ground pin and a second ground pin of the plurality of ground pins.

3. The signal transmission device as claimed in claim 2, wherein the first positive differential pin and the first negative differential pin are further located between the first ground pin and a third ground pin of the plurality of ground pins.

4. The signal transmission device of claim 1, wherein the plurality of positive differential pins and the plurality of negative differential pins transmit high speed signals.

5. The signal transmission device as claimed in claim 4, wherein a first positive differential high-speed pin of the plurality of positive differential pins is configured to transmit a positive signal component of a fifth differential signal, a first negative differential high-speed pin of the plurality of negative differential pins is configured to transmit a negative signal component of the fifth differential signal, a second positive differential high-speed pin of the plurality of positive differential pins is configured to transmit a positive signal component of a sixth differential signal, and a second negative differential high-speed pin of the plurality of negative differential pins is configured to transmit a negative signal component of the sixth differential signal;

the plurality of control signal pins comprise a system main power supply enabling pin, the system main power supply enabling pin is positioned among the positive differential low-speed pin, the negative differential low-speed pin, the first positive differential high-speed pin, the first negative differential high-speed pin, the second positive differential high-speed pin and the second negative differential high-speed pin, the first positive differential high-speed pin and the first negative differential high-speed pin are positioned on one side of a tenth grounding pin in the plurality of grounding pins, and the second positive differential high-speed pin and the second negative differential high-speed pin are positioned on the other side of the tenth grounding pin.

6. The signal transmitting device as claimed in claim 3, wherein the power signal pins are a plurality of low voltage power pins and a plurality of high voltage power pins, the low voltage power pins are used for transmitting low voltage power signals, the high voltage power pins are used for transmitting high voltage power signals, and the third ground pin is located between the low voltage power pins and the first positive differential pin and the first negative differential pin.

7. A signal transmission apparatus capable of transmitting a plurality of sets of data streams, comprising:

a first positive differential pin of the positive differential pins is used for transmitting a positive signal component of a first differential signal, and a second positive differential pin of the positive differential pins is used for transmitting a positive signal component of a second differential signal;

a first negative differential pin of the plurality of negative differential pins is used for transmitting a negative signal component of a first differential signal, and a second negative differential pin of the plurality of negative differential pins is used for transmitting a negative signal component of a second differential signal;

a positive differential low-speed pin for transmitting a positive signal component which is a low-speed differential signal;

a negative differential low-speed pin for transmitting a negative signal component of the low-speed differential signal;

a plurality of ground pins;

a plurality of power signal pins;

a plurality of control signal pins;

a metal isolation layer;

a housing; and

an insulator disposed in the housing, the housing being configured to receive the positive differential pins, the negative differential pins, the ground pins, the power signal pins, and the control signal pins, the housing including a chamfer disposed at one side of the housing;

the first positive differential pin and the first negative differential pin are located on one side of a first grounding pin in the plurality of grounding pins, the second positive differential pin and the second negative differential pin are located on the other side of the first grounding pin, the plurality of positive differential pins and the plurality of negative differential pins are located on one side of the metal isolation layer, and the positive differential low-speed pin, the negative differential low-speed pin and the plurality of control signal pins are located on the other side of the metal isolation layer.

8. The signal transmission device according to claim 7, wherein the housing has a receiving space and a protruding portion, the protruding portion includes a pair of sidewalls and a top wall, the top wall connects between the pair of sidewalls, the pair of sidewalls and the top wall together form an insertion space, and the insertion space and the receiving space are communicated with each other; the insulator is a tongue portion, the tongue portion is located in the accommodating space, and the positive differential pins, the negative differential pins, the ground pins, the power signal pins and the control signal pins are located on the tongue portion.

9. The signal transmission device according to claim 7, wherein the housing has an accommodation space surrounded by the insulator and a protrusion, the positive differential pins, the negative differential pins, the ground pins, the power signal pins and the control signal pins are located on an inner surface of the insulator, and the protrusion includes a pair of side walls and a top wall, the top wall is connected between the pair of side walls, and the pair of side walls and the top wall together form an insertion space.

10. A signal transmission apparatus capable of transmitting a plurality of sets of data streams, comprising:

a plurality of positive differential pins for transmitting positive signal components of a plurality of differential signals;

a plurality of negative differential pins to transmit negative signal components of the plurality of differential signals;

a positive differential low-speed pin for transmitting a positive signal component which is a low-speed differential signal;

a negative differential low-speed pin for transmitting a negative signal component of the low-speed differential signal;

a plurality of ground pins;

a plurality of power signal pins;

a plurality of control signal pins;

the positive differential pins and the negative differential pins are arranged in parallel with the positive differential high-speed pins and the negative differential high-speed pins through the metal isolation layer; and

the shell is provided with an accommodating space and a protruding part, the positive differential pins, the negative differential pins, the ground pins, the power signal pins and the control signal pins are located on the inner surface of the shell, the protruding part comprises a pair of side walls and a top wall, the top wall is connected between the pair of side walls, the pair of side walls and the top wall jointly form an inserting space, and the inserting space is communicated with the accommodating space.

Images