CN113809019B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN113809019B CN113809019B CN202111080778.4A CN202111080778A CN113809019B CN 113809019 B CN113809019 B CN 113809019B CN 202111080778 A CN202111080778 A CN 202111080778A CN 113809019 B CN113809019 B CN 113809019B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000007789 sealing Methods 0.000 claims abstract description 121
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 238000005530 etching Methods 0.000 claims abstract description 13
- 125000004122 cyclic group Chemical group 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 230000005611 electricity Effects 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 abstract description 12
- 239000001301 oxygen Substances 0.000 abstract description 12
- 230000004888 barrier function Effects 0.000 abstract description 8
- 238000005192 partition Methods 0.000 abstract description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The application relates to a semiconductor device and a manufacturing method thereof, comprising the following steps: a substrate; a dielectric layer on the substrate; the sealing ring structure comprises at least two annular sealing rings arranged at intervals and a connecting structure located between the annular sealing rings, the annular sealing rings penetrate through the dielectric layer, and the connecting structure is connected with the two adjacent annular sealing rings to partition the dielectric layer located between the two adjacent annular sealing rings, so that etching stress in the forming process of the sealing ring structure can be reduced, and the water-oxygen barrier performance of the sealing ring structure is prevented from being influenced due to dislocation of the sealing ring structure.
Description
[ field of technology ]
The application relates to the technical field of semiconductor devices, in particular to a semiconductor device and a manufacturing method thereof.
[ background Art ]
As technology advances, the semiconductor industry continues to search for new production methods to enable each memory die in a memory device to have a greater number of memory cells. Among them, 3d nand (three-dimensional nand gate) memory devices have become a currently leading-edge memory technology with great development potential due to the advantages of high memory density, low cost and the like.
In the 3D NAND memory device structure, a stacked structure (or stack) including a plurality of gate layers and insulating layers vertically stacked alternately is formed with a channel hole in which a memory cell string is formed, and the gate layers in the stacked structure serve as gate lines of each layer of memory cells, thereby realizing a stacked 3D NAND memory device. In addition, the 3D NAND memory device may further have a seal Ring (S eal Ring) structure, where the seal Ring structure is used to release and block stress generated in the packaging process of the 3D NAND memory device, and block moisture penetration of the 3D NAND memory device during manufacturing and use, so as to improve reliability of the memory device.
In the prior art, a deep groove process is generally used to form two or more annular grooves around the periphery of the stacked structure, and the sealing ring structure is formed by filling conductive materials. However, with the increase of the number of stacked layers in the 3D NAND memory device, when the sealing ring structure is formed, the depth of the deep groove formed by etching is deeper, the etching stress is larger, the side wall of the deep groove is inclined easily, and therefore dislocation of the sealing ring structure is caused, and the water-oxygen barrier performance of the sealing ring structure is affected.
[ application ]
The application aims to provide a semiconductor device and a manufacturing method thereof, so as to avoid dislocation of a sealing ring structure and further improve water-oxygen barrier performance of the sealing ring structure.
In order to solve the above-described problems, the present application provides a semiconductor device including: a substrate; a dielectric layer on the substrate; and the sealing ring structure is positioned on the substrate and comprises at least two annular sealing rings arranged at intervals and a connecting structure positioned between the annular sealing rings, wherein the annular sealing rings penetrate through the dielectric layer, and the connecting structure is connected with the adjacent two annular sealing rings.
The connecting structure comprises a plurality of first connecting walls which are arranged at intervals, and two adjacent annular sealing rings are respectively connected with the end parts of two opposite sides of the first connecting walls.
Wherein, connection structure still includes the second connecting wall that a plurality of intervals set up, and adjacent two cyclic annular sealing rings are connected respectively to the relative both sides tip of second connecting wall, and second connecting wall and first connecting wall are arranged in turn along cyclic annular sealing ring's circumferencial direction, and adjacent second connecting wall and first connecting wall are nonparallel.
Wherein, adjacent second connecting wall is connected with first connecting wall.
Wherein, connection structure still includes the third connecting wall that a plurality of intervals set up, and adjacent two cyclic annular sealing rings are connected respectively to the relative both sides tip of third connecting wall, and third connecting wall, second connecting wall and first connecting wall are periodic alternate arrangement along cyclic annular sealing ring's the circumferencial direction, and adjacent third connecting wall and first connecting wall are unparallel, and adjacent third connecting wall and second connecting wall are unparallel.
Wherein, first connecting wall perpendicular to annular sealing ring.
The connecting structure further comprises a fourth connecting wall, and the fourth connecting wall is connected with the plurality of first connecting walls.
Wherein the substrate comprises a device region and the annular seal ring is disposed around an edge of the device region.
Wherein the semiconductor device further comprises: a stacked structure on the device region, the stacked structure including a plurality of gate layers and gate insulating layers alternately stacked, ends of the plurality of gate layers and the gate insulating layers forming a step structure; and a plurality of contact plugs electrically connected with the gate layer at the step structure.
Wherein, the material of the sealing ring structure is the same as the material of the contact plug.
In order to solve the above problems, the present application also provides a method for manufacturing a semiconductor device, the method comprising: providing a substrate; forming a dielectric layer on a substrate; and forming a sealing ring structure on the substrate, wherein the sealing ring structure comprises at least two annular sealing rings arranged at intervals and a connecting structure positioned between the annular sealing rings, the annular sealing rings penetrate through the dielectric layer, and the connecting structure is connected with two adjacent annular sealing rings.
Wherein, form the seal ring structure on the substrate, specifically include: etching a dielectric layer on a substrate to form a sealing ring isolation groove; a seal ring structure is formed in the seal ring spacer.
The beneficial effects of the application are as follows: compared with the prior art, the semiconductor device and the manufacturing method thereof provided by the application have the advantages that the connecting structure is arranged between the two adjacent annular sealing rings, and the connecting structure is connected with the two adjacent annular sealing rings to isolate the dielectric layer between the two adjacent annular sealing rings, so that the etching stress in the forming process of the sealing ring structure can be reduced, and the influence of dislocation of the sealing ring structure on the water-oxygen barrier performance of the sealing ring structure is avoided.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic top view of a conventional semiconductor device;
FIG. 2 is a schematic cross-sectional view taken along line O-O' in FIG. 1;
FIG. 3 is a schematic cross-sectional view taken along line P-P' in FIG. 1;
FIG. 4 is a schematic top view of a prior art annular groove formed;
FIG. 5 is a schematic cross-sectional view taken along line P-P' in FIG. 4;
fig. 6 is a schematic top view of a semiconductor device according to an embodiment of the present application;
FIG. 7 is a schematic cross-sectional view taken along line O-O' in FIG. 6;
FIG. 8 is a schematic cross-sectional view taken along line P-P' in FIG. 6;
FIG. 9 is a schematic top view of an embodiment of the present application after forming an annular groove;
FIG. 10 is a schematic cross-sectional view taken along line O-O' in FIG. 9
FIG. 11 is a schematic cross-sectional view taken along line P-P' in FIG. 9;
FIG. 12 is a schematic top view of a portion of a seal ring structure provided in an embodiment of the present application;
FIG. 13 is another schematic top view of a portion of a seal ring structure provided in accordance with an embodiment of the present application;
FIG. 14 is another schematic top view of a portion of a seal ring structure provided in accordance with an embodiment of the present application;
FIG. 15 is another schematic top view of a portion of a seal ring structure provided in an embodiment of the present application;
FIG. 16 is another schematic top view of a portion of a seal ring structure provided in accordance with an embodiment of the present application;
FIG. 17 is another schematic top view of a portion of a seal ring structure provided in an embodiment of the present application;
FIG. 18 is a schematic cross-sectional view taken along line Q-Q' in FIG. 6;
fig. 19 is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present application.
[ detailed description ] of the application
The application is described in further detail below with reference to the drawings and examples. It is specifically noted that the following examples are only for illustrating the present application, but do not limit the scope of the present application. Likewise, the following examples are only some, but not all, of the examples of the present application, and all other examples, which a person of ordinary skill in the art would obtain without making any inventive effort, are within the scope of the present application.
In addition, directional terms such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., as used herein, refer only to the directions of the attached drawings. Accordingly, directional terminology is used to describe and understand the application and is not limiting of the application. In the various drawings, like elements are designated by like reference numerals. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown in the drawings.
Referring to fig. 1 to 3, fig. 1 is a schematic top view of a conventional semiconductor device, fig. 2 is a schematic cross-sectional view taken along a line O-O 'in fig. 1, and fig. 3 is a schematic cross-sectional view taken along a line P-P' in fig. 1. As shown in fig. 1 to 3, a conventional semiconductor device 10 includes a substrate 11, and a dielectric layer 12 and a seal ring structure 13 sequentially disposed on the substrate 11. In the prior art, the seal ring structure 13 is composed of two or more annular seal rings 131/132 surrounding the device region 11A of the substrate 11. Also, as shown in fig. 4 and 5, in the prior art, two or more annular grooves 131A/132A surrounding the device region 11A are generally formed by a deep groove process, and filled with a conductive material, thereby forming the seal ring structure 13. However, as the height of the semiconductor device 10 increases, the depth of the deep groove (i.e., the annular groove 131A/132A) required to be etched increases when the seal ring structure 13 is formed, which results in an increase in etching stress, and thus, the dielectric layer 121 between the annular grooves 131A/132A is inclined or deviated, so that the feature sizes of the two annular grooves 131A/132A are inconsistent, which results in misalignment of the annular seal ring 131/132 in the seal ring structure 13, and affects the water-oxygen barrier performance of the seal ring structure 13.
In order to solve the problems, the technical scheme adopted by the application is to provide a semiconductor device and a manufacturing method thereof, wherein a connecting structure is arranged between two adjacent annular sealing rings, and the connecting structure is connected with the two adjacent annular sealing rings so as to isolate a dielectric layer between the two adjacent annular sealing rings, thereby reducing etching stress in the forming process of the sealing ring structure, solving the problem that the annular sealing rings are misplaced due to the increase of the height of the semiconductor device in the conventional semiconductor device, and further improving the water-oxygen barrier performance of the sealing ring structure.
Referring to fig. 6 to 8, fig. 6 is a schematic top view of a semiconductor device according to an embodiment of the present application, fig. 7 is a schematic cross-sectional view taken along a line O-O 'in fig. 6, and fig. 8 is a schematic cross-sectional view taken along a line P-P' in fig. 6. As shown in fig. 6 to 8, the semiconductor device 20 includes a substrate 21, and a dielectric layer 22 and a seal ring structure 23 sequentially disposed on the substrate 21. In this embodiment, the seal ring structure 23 may include at least two annular seal rings 231/232 (e.g., a first annular seal ring 231 and a second annular seal ring 232) disposed at intervals, and a connection structure 233 between the annular seal rings 231/232. The annular seal rings 231/232 penetrate through the dielectric layer 22, and the connection structure 233 connects two adjacent annular seal rings 231/232 (e.g., the first annular seal ring 231 and the second annular seal ring 232) to isolate the dielectric layer 221 between the two adjacent annular seal rings 231/232.
Specifically, the substrate 21 may include a device region 21A, and the seal ring structure 23 may be disposed on the substrate 21 and around an edge of the device region 21A, and specifically, the seal ring structure 23 may surround the device structure disposed on the device region 21A to protect the device structure from external water and oxygen and protect the device structure from mechanical damage during dicing.
In some embodiments, the annular seal rings 231/232 in the seal ring structure 23 may penetrate the dielectric layer 22 in a direction Z perpendicular to the substrate Z and may be disposed around the edge of the device region 21A of the substrate 21.
Thus, as shown in fig. 9 to 11, in the present embodiment, in the process of forming the seal ring structure 23, two or more annular grooves 231A/232A surrounding the device region 21A are formed by a deep groove process, and at the same time, a connection groove 233A is formed between two adjacent annular grooves 231A/232A, the connection groove 233A being capable of connecting the two adjacent annular grooves 231A/232A together and penetrating the dielectric layer 221 between the two adjacent annular grooves 231A/232A in the direction Z perpendicular to the substrate 21, thereby being capable of breaking the dielectric layer 221 between the two adjacent annular grooves 231A/232A into a plurality of block structures. Therefore, compared with the prior art that the dielectric layer between two adjacent annular grooves is a continuous wall structure surrounding the edge of the device region, in the embodiment, the dielectric layer between two adjacent annular grooves is broken into a plurality of block structures surrounding the edge of the device region and arranged at intervals, so that the etching stress of etching to form the annular grooves can be reduced, and the dielectric layer between two adjacent annular grooves cannot be bent, inclined or offset integrally due to local stress, so that the water-oxygen blocking performance of the sealing ring structure is prevented from being influenced due to dislocation of the sealing ring structure.
In one embodiment, as shown in fig. 6, the connecting structure 233 may include a plurality of first connecting walls 2331 disposed at intervals, the first connecting walls 2331 are located between two adjacent annular sealing rings 231/232 (for example, the first annular sealing ring 231 and the second annular sealing ring 232), and opposite side ends of the first connecting walls 2331 may respectively connect the two adjacent annular sealing rings 231/232 to connect the two adjacent annular sealing rings 231/232 together. Further, the first connection wall 2331 may penetrate the dielectric layer 22 in a direction Z perpendicular to the substrate 21 to partition the dielectric layer 221 between the adjacent two annular seal rings 231/232.
In particular, as shown in fig. 6, the cross-sectional shape of the annular seal rings 231/232 (for example, the first annular seal ring 231 and the second annular seal ring 232) may be any closed geometric shape such as a rectangle or a circle. Specifically, when the cross-sectional shape of the above-described annular seal rings 231/232 is an arbitrarily closed geometric polygon such as a rectangle, the respective side walls of the adjacent two annular seal rings 231/232 may be disposed opposite and in parallel at a spacing. For example, as shown in fig. 6, when the cross-sectional shape of the annular seal rings 231/232 is rectangular, four side walls (e.g., a front side wall, a rear side wall, a left side wall, or a right side wall) of two adjacent annular seal rings 231/232 may be disposed opposite and parallel to each other at a spacing, e.g., a front side wall of the first annular seal ring 231 and a front side wall of the second annular seal ring 232 are disposed opposite and parallel to each other at a spacing, a rear side wall of the first annular seal ring 231 and a rear side wall of the second annular seal ring 232 are disposed opposite and parallel to each other at a spacing, a left side wall of the first annular seal ring 231 and a left side wall of the second annular seal ring 232 are disposed opposite and parallel to each other at a spacing, and a right side wall of the first annular seal ring 231 and a right side wall of the second annular seal ring 232 are disposed opposite and parallel to each other at a spacing.
Specifically, as shown in fig. 12, a plurality of the above-described first connection walls 2331 located between a certain side wall (e.g., right side wall) of the adjacent two annular seal rings 231/232 may be disposed in parallel at intervals, and may be disposed in parallel and at equal intervals.
In one embodiment, as shown in fig. 12, the first connection wall 2331 may be vertically connected to the annular sealing ring 231/232, and in particular, when the cross-sectional shape of the annular sealing ring 231/232 is polygonal, the first connection wall 2331 may be vertically connected to a side wall (e.g., a right side wall) of the annular sealing ring 231/232. In other embodiments, as shown in fig. 13, the first connection wall 2331 may further connect to but not perpendicular to the annular sealing ring 231/232, and in particular, when the cross-sectional shape of the annular sealing ring 231/232 is polygonal, the first connection wall 2331 may connect to but not perpendicular to a side wall (e.g., a right side wall) of the annular sealing ring 231/232.
In some embodiments, as shown in fig. 14, the connecting structure 233 may further include a plurality of second connecting walls 2332 disposed at intervals, the second connecting walls 2332 are located between two adjacent annular sealing rings 231/232 (for example, the first annular sealing ring 231 and the second annular sealing ring 232), and opposite side ends of the second connecting walls 2332 may respectively connect the two adjacent annular sealing rings 231/232 to connect the two adjacent annular sealing rings 231/232 together. Further, the second connection wall 2332 may penetrate through the dielectric layer 22 in a direction Z perpendicular to the substrate 21 to further partition the dielectric layer 221 between the adjacent two annular seal rings 231/232 into a smaller block structure.
Specifically, the second connection walls 2332 and the first connection walls 2331 may be alternately arranged along the circumferential direction of the annular seal rings 231/232, for example, the annular seal rings 231/232 may be disposed around the edge of the device region 21A, and then the second connection walls 2332 and the first connection walls 2331 may be alternately arranged around the edge of the device region 21A. Meanwhile, adjacent second connection walls 2332 and first connection walls 2331 may not be parallel.
In some embodiments, as shown in fig. 14, the adjacent second connection wall 2332 and first connection wall 2331 may be connected, and the dielectric layer 221 between the corresponding annular sealing rings 231/232 may be separated by the second connection wall 2332 and first connection wall 2331 into a plurality of triangular prism-shaped block structures. In other embodiments, the adjacent second connecting walls 2332 and first connecting walls 2331 may not be connected together, i.e. spaced apart, and the dielectric layer 221 between the annular sealing rings 231/232 may be separated into a plurality of square block structures by the second connecting walls 2332 and the first connecting walls 2331.
Specifically, as shown in fig. 14, the first connection wall 2331 may be vertically connected to the annular sealing ring 231/232, and the second connection wall 2332 may be connected to and not vertically connected to the annular sealing ring 231/232. In other embodiments, as shown in FIG. 15, the first connection wall 2331 and the second connection wall 2332 may be connected to each other but not perpendicular to the annular seal rings 231/232.
In one embodiment, as shown in fig. 16, the connecting structure 233 may further include a plurality of third connecting walls 2333 disposed at intervals, the third connecting walls 2333 are located between two adjacent annular sealing rings 231/232 (for example, the first annular sealing ring 231 and the second annular sealing ring 232), and opposite side ends of the third connecting walls 2333 may respectively connect the two adjacent annular sealing rings 231/232 to connect the two adjacent annular sealing rings 231/232 together. Further, the third connection wall 2333 may penetrate the dielectric layer 22 in a direction Z perpendicular to the substrate 21 to further partition the dielectric layer 221 between the adjacent two annular seal rings 231/232 into a smaller block structure.
The third connection wall 2333, the second connection wall 2332 and the first connection wall 2331 may be periodically and alternately arranged along the circumferential direction of the annular seal ring 231/232, for example, the annular seal ring 231/232 is disposed around the edge of the device region 21A, and then the third connection wall 2333, the second connection wall 2332 and the first connection wall 2331 may be periodically and alternately arranged around the edge of the device region 21A. Meanwhile, adjacent third connection walls 2333 and first connection walls 2331 may be non-parallel, adjacent third connection walls 2333 and second connection walls 2332 may be non-parallel, and adjacent first connection walls 2331 and second connection walls 2332 may be non-parallel.
Specifically, as shown in fig. 16, adjacent third connection walls 2333 and first connection walls 2331 may be connected, adjacent third connection walls 2333 and second connection walls 2332 may be connected, and adjacent first connection walls 2331 and second connection walls 2332 may be connected, and the dielectric layer 221 between the corresponding annular seal rings 231/232 may be partitioned into a plurality of triangular prism-shaped block structures by the third connection walls 2333, the second connection walls 2332 and the first connection walls 2331. In other embodiments, the adjacent second connection wall 2332 and first connection wall 2331 may not be connected together, the adjacent third connection wall 2333 and second connection wall 2332 may not be connected together, and the adjacent first connection wall 2331 and second connection wall 2332 may not be connected together, and the dielectric layer 221 between the corresponding annular seal rings 231/232 may be separated into a plurality of rectangular block structures by the third connection wall 2333, the second connection wall 2332 and the first connection wall 2331.
In some embodiments, as shown in FIG. 16, the first connection wall 2331 may be vertically connected to the annular sealing ring 231/232, and the second connection wall 2332 and the third connection wall 2333 are connected but not vertically connected to the annular sealing ring 231/232. In other embodiments, the first connection wall 2331, the second connection wall 2332, and the third connection wall 2333 may be connected to but not perpendicular to the annular seal rings 231/232.
In some embodiments, as shown in fig. 17, the connecting structure 233 may further include a fourth connecting wall 2334, where the fourth connecting wall 2334 is located between two adjacent annular sealing rings 231/232 (for example, the first annular sealing ring 231 and the second annular sealing ring 232) and is not connected to the two adjacent annular sealing rings 231/232. Specifically, the fourth connection wall 2334 may be connected to the plurality of first connection walls 2331 between the adjacent two annular seal rings 231/232, and may penetrate through the dielectric layer 22 in the direction Z perpendicular to the substrate 21, so as to further partition the dielectric layer 211 having a block shape between the adjacent two first connection walls 2331 into a smaller block structure.
Specifically, the fourth connection wall 2334 may extend along the circumferential direction of the annular seal rings 231/232, for example, the annular seal rings 231/232 are disposed around the edge of the device region 21A, and then the fourth connection wall 2334 may be disposed around the edge of the device region 21A of the substrate 21, so that the fourth connection wall 2334 may be connected to all the first connection walls 2331 between the adjacent two annular seal rings 231/232.
In the above embodiment, the seal ring structure 23 may penetrate the dielectric layer 22 and extend into the substrate 21 to form a groove on the substrate 21. The substrate 21 may be made of a semiconductor material such as Silicon, germanium, or Silicon-On-Insulator (SOI). The dielectric layer 22 may be made of an insulating material such as silicon oxide.
In the above embodiment, the above semiconductor device 20 may be embodied as a three-dimensional memory device (e.g., a 3D NAND memory device). Accordingly, as shown in fig. 18, the semiconductor device 20 may further include an array memory structure 24 disposed on the device region 21A of the substrate 21. In particular, the array memory structure 24 may include a stacked structure on the device region 21A, the stacked structure may include a plurality of gate layers 241 and gate insulating layers 242 alternately stacked, and ends of the plurality of gate layers 241 and gate insulating layers 242 may form a stepped structure. Further, the array memory structure 24 may further include a plurality of contact plugs 243, and the plurality of contact plugs 243 may be electrically connected to the gate layer 241 at the step structures, respectively.
The substrate 21 may further include a peripheral region 21B located at a periphery of the device region 21A, and the seal ring structure 23 may be formed on the peripheral region 21B of the substrate 21 and may surround the array memory structure 24 to protect the array memory structure 24 from outside water and oxygen and protect the device structure from mechanical damage during dicing.
Specifically, the dielectric layer 22 may cover a step structure in the array memory structure 24, and the contact plug 243 may pass through the dielectric layer 22 on the step structure to be electrically connected with an end of the gate layer 241.
In a specific embodiment, the material of the contact plug 243 may be the same as that of the seal ring structure 23, for example, may be a metal material such as tungsten or copper. Also, in practice, the seal ring structure 23 and the contact plug 243 may be formed together, thereby eliminating the need for additional process steps.
In other embodiments, the array memory structure 24 may further include a gate line isolation structure (not shown) passing through the stacked structure 24, and the material of the seal ring structure 23 may be the same as that of the gate line isolation structure. Furthermore, in implementation, the seal ring structure 23 and the gate line isolation structure may be formed together, so that no additional process steps are required.
In contrast to the prior art, the semiconductor device in this embodiment sets up connection structure between two adjacent annular seal rings to make connection structure connect two adjacent annular seal rings, with the dielectric layer that will be located between two adjacent annular seal rings cut off, thereby can reduce the etching stress of sealing ring structure in-process of formation, in order to avoid sealing ring structure dislocation and influence sealing ring structure's water oxygen barrier property.
Referring to fig. 19, fig. 19 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application, where a specific flow chart of the method for manufacturing a semiconductor device may be as follows:
step S11: a substrate is provided.
Step S12: a dielectric layer is formed on a substrate.
Step S13: and forming a sealing ring structure on the substrate, wherein the sealing ring structure comprises at least two annular sealing rings arranged at intervals and a connecting structure positioned between the annular sealing rings, the annular sealing rings penetrate through the dielectric layer, and the connecting structure is connected with two adjacent annular sealing rings.
The step S13 may specifically include:
step S131: and etching the dielectric layer on the substrate to form the sealing ring isolation groove.
Step S132: a seal ring structure is formed in the seal ring spacer.
In particular, the substrate may include a device region, and the seal ring structure may be located on the substrate and disposed around an edge of the device region, and in particular, the seal ring structure may surround the device structure disposed on the device region to protect the device structure from outside water oxygen and to protect the device structure from mechanical damage during dicing.
In some embodiments, the annular seal ring in the seal ring structure may penetrate the dielectric layer in a direction perpendicular to the substrate and may be disposed around an edge of the device region of the substrate.
In a specific embodiment, before the step S12, the method may further include:
step S14: an array memory structure is formed over a device region of a substrate.
The array memory structure may include a stacked structure formed on the device region, the stacked structure may include a plurality of gate layers and gate insulating layers alternately stacked, and ends of the plurality of gate layers and gate insulating layers may form a stepped structure. Further, the array memory structure may further include a plurality of contact plugs electrically connected to the gate layer at the step structures, respectively.
Specifically, the dielectric layer may cover the array memory structure, and the contact plug may pass through the dielectric layer on the step structure to be electrically connected to an end of the gate layer.
In a specific embodiment, the material of the contact plug may be the same as that of the sealing ring structure, for example, may be a metal material such as tungsten or copper. In addition, the sealing ring structure and the contact plug can be formed together in implementation, so that no extra process steps are required.
It should be noted that, the specific structure of the seal ring structure may refer to the specific implementation manner in the embodiment of the semiconductor device, so that the description is omitted here.
Compared with the prior art, the manufacturing method of the semiconductor device in the embodiment is characterized in that the substrate is provided, the dielectric layer is formed on the substrate, then the sealing ring structure is formed on the substrate, the sealing ring structure comprises at least two annular sealing rings arranged at intervals and a connecting structure positioned between the annular sealing rings, the annular sealing rings penetrate through the dielectric layer, the connecting structure is connected with the two adjacent annular sealing rings to partition the dielectric layer positioned between the two adjacent annular sealing rings, and therefore etching stress in the forming process of the sealing ring structure can be reduced, and the influence on water-oxygen barrier performance of the sealing ring structure due to dislocation of the sealing ring structure is avoided.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the application.
Claims (9)
1. A semiconductor device, comprising:
a substrate comprising a device region;
a dielectric layer on the substrate;
the sealing ring structure is positioned on the substrate and comprises at least two annular sealing rings which are arranged at intervals and a connecting structure positioned between the annular sealing rings, the annular sealing rings penetrate through the dielectric layer and are arranged around the edge of the device area, and the connecting structure is connected with two adjacent annular sealing rings;
a stacked structure on the device region, the stacked structure including a plurality of gate layers and gate insulating layers alternately stacked, and a step structure at an end of the plurality of gate layers and the gate insulating layers, the dielectric layer covering the step structure;
the contact plugs penetrate through the dielectric layer on the step structure and are respectively and electrically connected with the grid layer at the position of the step structure, and the sealing ring structure is made of the same material as the contact plugs;
and forming a plurality of contact plugs in the process of forming the sealing ring structure on the substrate.
2. The semiconductor device according to claim 1, wherein the connection structure includes a plurality of first connection walls arranged at intervals, opposite side ends of the first connection walls being respectively connected to adjacent two of the annular seal rings.
3. The semiconductor device according to claim 2, wherein the connection structure further comprises a plurality of second connection walls arranged at intervals, opposite side ends of the second connection walls are respectively connected with two adjacent annular sealing rings, the second connection walls and the first connection walls are alternately arranged along a surrounding direction of the annular sealing rings, and the adjacent second connection walls and the first connection walls are not parallel.
4. A semiconductor device according to claim 3, wherein adjacent second connection walls and first connection walls are connected.
5. The semiconductor device according to claim 3, wherein the connection structure further comprises a plurality of third connection walls arranged at intervals, opposite side ends of the third connection walls are respectively connected with two adjacent annular sealing rings, the third connection walls, the second connection walls and the first connection walls are periodically and alternately arranged along a surrounding direction of the annular sealing rings, the adjacent third connection walls and the first connection walls are not parallel, and the adjacent third connection walls and the adjacent second connection walls are not parallel.
6. The semiconductor device of claim 2, wherein the first connection wall is vertically connected to the annular seal ring.
7. The semiconductor device according to claim 2, wherein the connection structure further includes a fourth connection wall connected to the plurality of first connection walls.
8. A method of fabricating a semiconductor device, comprising:
providing a substrate;
forming a memory array structure on a device region of the substrate, the memory array structure including a stack structure including a plurality of gate layers and gate insulating layers alternately stacked, and a step structure at an end of the plurality of gate layers and gate insulating layers;
forming a dielectric layer on the substrate, wherein the dielectric layer covers the step structure;
simultaneously form sealing ring structure and a plurality of contact plug on the substrate, sealing ring structure includes at least two cyclic annular sealing rings that the interval set up and is located connection structure between the cyclic annular sealing ring, cyclic annular sealing ring runs through the dielectric layer, just connection structure connects two adjacent cyclic annular sealing rings, and encircle device region edge sets up, a plurality of contact plugs run through dielectric layer on the step structure and respectively in step structure's position with grid layer electricity is connected.
9. The method for manufacturing a semiconductor device according to claim 8, wherein the forming a seal ring structure on the substrate specifically comprises:
etching the dielectric layer on the substrate to form a sealing ring isolation groove;
and forming a sealing ring structure in the sealing ring isolation groove.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103579199A (en) * | 2012-07-31 | 2014-02-12 | 台湾积体电路制造股份有限公司 | Double seal ring |
| CN203941897U (en) * | 2014-07-01 | 2014-11-12 | 中芯国际集成电路制造(北京)有限公司 | A kind of chip seal ring structure |
| US10692786B1 (en) * | 2019-03-28 | 2020-06-23 | Vanguard International Semiconductor Corporation | Semiconductor structures |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2010153753A (en) * | 2008-12-26 | 2010-07-08 | Renesas Electronics Corp | Semiconductor device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103579199A (en) * | 2012-07-31 | 2014-02-12 | 台湾积体电路制造股份有限公司 | Double seal ring |
| CN203941897U (en) * | 2014-07-01 | 2014-11-12 | 中芯国际集成电路制造(北京)有限公司 | A kind of chip seal ring structure |
| US10692786B1 (en) * | 2019-03-28 | 2020-06-23 | Vanguard International Semiconductor Corporation | Semiconductor structures |
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