CN113806280B

CN113806280B - Data processing method and device and processing chip

Info

Publication number: CN113806280B
Application number: CN202111323013.9A
Authority: CN
Inventors: 张染
Original assignee: New H3C Technologies Co Ltd
Current assignee: New H3C Technologies Co Ltd
Priority date: 2021-11-10
Filing date: 2021-11-10
Publication date: 2022-02-25
Anticipated expiration: 2041-11-10
Also published as: CN113806280A

Abstract

The embodiment of the application provides a data processing method, a data processing device and a processing chip. The scheme is as follows: acquiring first data; after the invalid data in the first data are shifted to the valid data, second data are obtained; caching the second data into an FIFO (first in first out) cache, and performing EOP (Ethernet over coax) position retrieval to obtain a first retrieval result; splicing the first residual data, a preset buoy and cache data output by an FIFO (first in first out) cache to obtain a first spliced array; performing EOP position retrieval on the first residual data in the first spliced array to obtain a second retrieval result; and outputting the target data when the first spliced array meets the preset output condition according to the first retrieval result and the second retrieval result. By applying the technical scheme provided by the embodiment of the application, under the condition of multi-data channel transmission, the matching between the data transmission bandwidth and the time sequence processing capacity of the processing chip is ensured, so that the receiving design of the chip ILKN _ LA is realized, and the normal operation of data transmission is maintained.

Description

Data processing method and device and processing chip

Technical Field

The present application relates to the field of communications technologies, and in particular, to a data processing method, an apparatus, and a processing chip.

Background

Due to the requirement of high-speed data transmission of network chips, the data transmission bandwidth requirement of data transmitted based on an interchip high-speed data transmission (ILKN) protocol is higher and higher. At present, in the face of the demand of increasing data transmission bandwidth, the data transmission bandwidth is increased by expanding the number of data transmission channels. For example, the transmission bandwidth of each data channel (i.e. the width of each data transmission channel) is 67 bits (bit), and expanding 8 data transmission channels into 16 data transmission channels, the data transmission bandwidth will be doubled, i.e. the data transmission bandwidth is increased by (16-8) × 67 bits.

However, in the related art, a processing chip outside the Interlaken protocol (ILKN _ LA) needs to complete operations such as retrieving a Packet Start (SOP) and a Packet End (EOP) position Of received data, calculating a float position, and acquiring residual data in one clock cycle. This makes the processing chip need to complete all operations on the received data within one clock cycle when increasing the number of data transmission channels, which puts a high demand on the data processing capability of the processing chip within a unit clock cycle. That is, the processing chip needs to have a high timing processing capability. However, as the number of data transmission channels increases, the data transmission bandwidth and the timing processing capability of the processing chip cannot be matched, which results in that the receiving design of the chip ILKN _ LA cannot be implemented, and normal transmission of data is affected.

Disclosure of Invention

An object of the embodiments of the present application is to provide a data processing method, an apparatus, and a processing chip, so as to ensure matching between a data transmission bandwidth and a timing processing capability of the processing chip under the condition of multiple data channel transmission, thereby implementing a receiving design of the chip ILKN _ LA and maintaining normal data transmission. The specific technical scheme is as follows:

the embodiment of the application also provides a data processing method, which is applied to an ILKN-LA processing chip and comprises the following steps:

respectively acquiring first data from a plurality of data transmission channels in a first clock cycle of a current first clock cycle group; the data obtained by each data transmission channel in the first data comprises a VALID (VALID) identifier corresponding to the data transmission channel;

shifting invalid data in the first data to VALID data to obtain second data, wherein the VALID data is data transmitted by a data transmission channel with a VALID identifier as a first numerical value, and the invalid data is data transmitted by a data transmission channel with a VALID identifier as a second numerical value;

in a second clock cycle of the First clock cycle group, caching the second data into a First-in First-out (FIFO) cache, and performing EOP position retrieval on cache data in the FIFO cache to obtain a First retrieval result;

in a third clock cycle of the first clock cycle group, according to a first buoy position corresponding to a second clock cycle group, splicing first residual data, a preset buoy and cache data output by the FIFO cache to obtain a first spliced array of the first clock cycle group, so that the position of the preset buoy in the first spliced array is the first buoy position, data before the preset buoy in the first spliced array is effective data in the first residual data, and data after the preset buoy in the first spliced array is the cache data output by the FIFO cache; the second clock cycle group is a previous clock cycle group of the first clock cycle group, and the first residual data is data which is not output in a second splicing array of the second clock cycle group;

performing EOP position retrieval on the first residual data in the first spliced array to obtain a second retrieval result;

and outputting target data when the first spliced array meets a preset output condition according to the first retrieval result and the second retrieval result, wherein the target data is effective data between the first spliced array and the target position of the first EOP.

The embodiment of the present application further provides a data processing apparatus, which is applied to the ILKN-LA processing chip, and the apparatus includes:

the first acquisition module is used for respectively acquiring first data from the plurality of data transmission channels in a first clock cycle of the current first clock cycle group; the data obtained by each data transmission channel in the first data comprises a VALID identifier corresponding to the data transmission channel;

a shifting module, configured to shift invalid data in the first data to VALID data to obtain second data, where the VALID data is data transmitted by a data transmission channel whose VALID identifier is a first numerical value, and the invalid data is data transmitted by a data transmission channel whose VALID identifier is a second numerical value;

the first retrieval module is used for caching the second data into an FIFO (first in first out) cache in a second clock cycle of the first clock cycle group, and performing EOP (Ethernet over coax) position retrieval on cache data in the FIFO cache to obtain a first retrieval result;

a splicing module, configured to splice, in a third clock cycle of the first clock cycle group, first residual data, a preset buoy, and cache data output by the FIFO buffer according to a first buoy position corresponding to a second clock cycle group, so as to obtain a first spliced array of the first clock cycle group, where a position of the preset buoy in the first spliced array is the first buoy position, data before the preset buoy in the first spliced array is valid data in the first residual data, and data after the preset buoy in the first spliced array is the cache data output by the FIFO buffer; the second clock cycle group is a previous clock cycle group of the first clock cycle group, and the first residual data is data which is not output in a second splicing array of the second clock cycle group;

the second retrieval module is used for carrying out EOP position retrieval on the first residual data in the first spliced array to obtain a second retrieval result;

and the output module is used for outputting target data when the first spliced array meets a preset output condition according to the first retrieval result and the second retrieval result, wherein the target data is effective data between the first spliced array and the target position where the first EOP is located.

The embodiment of the application also provides a processing chip, and the processing chip is used for executing any one of the steps of the data processing method.

Embodiments of the present application also provide a machine-readable storage medium storing machine-executable instructions executable by a processing chip, the processing chip being caused by the machine-executable instructions to: implementing any of the data processing method steps described above.

Embodiments of the present application further provide a computer program product containing instructions, which when run on a computer, cause the computer to perform any of the data processing methods described above.

In the technical scheme provided by the embodiment of the application, in the first clock cycle of the current first clock cycle group, the second data is obtained by shifting the invalid data in the received first data to the valid data; caching second data into the FIFO cache in a second clock cycle of the first clock cycle group, and performing EOP position retrieval on cache data in the FIFO cache to obtain a first retrieval result; splicing the first residual data, the preset buoy and the cache data output by the FIFO cache in a third clock cycle of the first clock cycle group to obtain a first spliced array of the first clock cycle group; performing EOP position retrieval on the first residual data in the first spliced array to obtain a second retrieval result; and outputting the target data when the first spliced array meets the preset output condition according to the first retrieval result and the second retrieval result.

Compared with the related technology, the processing chip processes the received data through three clock cycles included in the first clock cycle group, namely, the received data is respectively subjected to operations of position adjustment of valid data, data caching, EOP position retrieval, target data output and the like through the first clock cycle, the second clock cycle and the third clock cycle, and the received data is processed, so that the processing chip can complete a data processing process in the first clock cycle group, on the premise that the data receiving bandwidth is met, the time sequence convergence capacity of the processing chip is improved through time-sharing processing of multiple clock cycles, and the matching between the data transmission bandwidth and the time sequence convergence capacity of the processing chip is guaranteed under the condition of multi-data channel transmission.

In addition, EOP position retrieval is respectively carried out on the cache data part and the residual data part in the first spliced array in the second clock cycle and the third clock cycle, segmented processing of data is achieved, timing sequence convergence capability of a processing chip is improved, and matching between data transmission bandwidth and the timing sequence convergence capability of the processing chip is guaranteed under the condition of multi-data channel transmission.

In addition, in the first clock cycle, the situation that invalid data are arranged in the front can be avoided by adjusting the position of the valid data in the received data, the received valid data can be conveniently processed in the later period, the time sequence convergence capability of the processing chip is improved, and the matching between the data transmission bandwidth and the time sequence convergence capability of the processing chip is ensured under the condition of multi-data channel transmission.

Therefore, by adopting the technical scheme provided by the embodiment of the application, under the condition of multi-data channel transmission, the matching between the data transmission bandwidth and the time sequence processing capability of the processing chip is ensured, so that the receiving design of the chip ILKN _ LA is realized, and the normal operation of data transmission is maintained.

Of course, it is not necessary for any product or method of the present application to achieve all of the above-described advantages at the same time.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a first schematic flowchart of a data processing method according to an embodiment of the present application;

fig. 2 is a second flowchart of a data processing method according to an embodiment of the present application;

fig. 3 is a third schematic flowchart of a data processing method according to an embodiment of the present application;

fig. 4 is a fourth flowchart illustrating a data processing method according to an embodiment of the present application;

fig. 5 is a schematic flow chart of a fifth data processing method according to an embodiment of the present application;

fig. 6 is a sixth flowchart illustrating a data processing method according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a processing chip according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the related art, when data transmission is performed using the ILKN protocol, a plurality of data transmission channels may be provided between two processing chips (i.e., a processing chip on the transmitting side and a processing chip on the receiving side). For the sake of understanding, the number of data transmission channels between two processing chips is illustrated as 8 (i.e., channel 0-channel 8). The bandwidth of each data transmission channel is 67 bits.

When the processing chip on the transmitting side sends a plurality of data packets to the processing chip on the receiving side, each data packet can be split into VALID data with the size of 64 bits, 8 times 67 bits of data are sent to the processing chip on the receiving side in each clock cycle through 8 data transmission channels between the processing chip and the processing chip on the receiving side, and each 67bit of data includes VALID data of 64 bits and a VALID identifier of each data channel. In addition, each 67-bit data may further include an SOP or EOP corresponding to the data packet.

After the processing chip on the receiving side receives the 67-bit data sent by the processing chip on the sending side through each data channel, the processing chip on the receiving side can combine the data corresponding to the 8 data transmission channels to obtain 8 x 67-bit data, that is, obtain 1 x 536-bit data, and store the data in the FIFO buffer.

And the processing chip at the receiving side splices the residual data, the preset buoy and the 8 x 67bit data output by FIFO buffer in the current clock cycle according to the residual data and the buoy position corresponding to the previous clock cycle to obtain a spliced array of the current clock cycle.

And the processing chip at the receiving side performs SOP position retrieval and EOP position retrieval on the spliced array in the current clock period, and outputs all effective data from the position of the first SOP to the position of the first EOP after determining the position of the first SOP and the position of the first EOP in the spliced array.

And the processing chip at the receiving side determines the residual data and the buoy position corresponding to the current clock cycle according to the output condition of the data in the spliced array of the current clock cycle.

In the data processing process, the processing chip on the receiving side needs to complete the operations of the SOP position retrieval, the EOP position retrieval, the mosaic array construction, the data output, the residual data determination, the buoy position determination and the like in one clock cycle. After the number of the data transmission channels between the processing chips at the transmitting side and the receiving side is expanded, if the number of the data transmission channels is expanded from 8 to 16, when the related technology is adopted, the data amount received by the processing chip at the receiving side in the same time period is greatly increased, which causes that the processing chip at the receiving side cannot complete the data processing process in one time period, and the time sequence convergence capability of the data transmission bandwidth and the processing chip cannot be matched, thereby causing that the receiving design of the chip ILKN _ LA cannot be realized, and affecting the normal transmission of data.

In order to solve the technical problems of the related art, embodiments of the present application provide a data processing method, where the method is applied to an ILKN-LA processing chip, where the processing chip may be a network chip, and the processing chip may be integrated in various network devices, such as a router, a gateway, and other network devices, and here, the processing chip and the network device into which the processing chip is integrated are not specifically limited. As shown in fig. 1, fig. 1 is a first schematic flow chart of a data processing method according to an embodiment of the present application. The method comprises the following steps.

Step S101, in a first clock cycle of a current first clock cycle group, respectively acquiring first data from a plurality of data transmission channels; the data obtained by each data transmission channel in the first data includes VALID identifiers corresponding to the data transmission channels.

Step S102, obtaining second data after shifting invalid data in the first data to VALID data, where the VALID data is data transmitted by a data transmission channel whose VALID identifier is a first numerical value, and the invalid data is data transmitted by a data transmission channel whose VALID identifier is a second numerical value.

Step S103, in a second clock cycle of the first clock cycle group, buffering the second data into the FIFO buffer, and performing EOP position retrieval on the buffered data in the FIFO buffer to obtain a first retrieval result.

And step S104, splicing the first residual data, the preset buoy and the cache data output by the FIFO cache according to the first buoy position corresponding to the second clock cycle group in the third clock cycle of the first clock cycle group to obtain a first spliced array of the first clock cycle group, so that the position of the preset buoy in the first spliced array is the first buoy position, the data before the preset buoy in the first spliced array is effective data in the first residual data, and the data after the preset buoy in the first spliced array is the cache data output by the FIFO cache.

The second clock cycle group is a previous clock cycle group of the first clock cycle group, and the first residual data is data which is not output in the second splicing array of the second clock cycle group.

And step S105, performing EOP position retrieval on the first residual data in the first spliced array to obtain a second retrieval result.

And S106, outputting target data when the first spliced array meets a preset output condition according to the first retrieval result and the second retrieval result, wherein the target data is effective data between the first spliced array and the target position of the first EOP.

In the embodiment of the present application, the processing chip on the transmitting side and the processing chip on the receiving side may be used for data transmission or data reception. Here, the processing chip on the transmitting side and the processing chip on the receiving side are not limited at all.

By the method shown in fig. 1, in the first clock cycle of the current first clock cycle group, the second data is obtained by shifting the invalid data in the received first data to be behind the valid data; caching second data into the FIFO cache in a second clock cycle of the first clock cycle group, and performing EOP position retrieval on cache data in the FIFO cache to obtain a first retrieval result; splicing the first residual data, the preset buoy and the cache data output by the FIFO cache in a third clock cycle of the first clock cycle group to obtain a first spliced array of the first clock cycle group; performing EOP position retrieval on the first residual data in the first spliced array to obtain a second retrieval result; and outputting the target data when the first spliced array meets the preset output condition according to the first retrieval result and the second retrieval result.

The following examples are given to illustrate the examples of the present application. For convenience of description, the data processing procedure will be explained below with only a processing chip on the receiving side (hereinafter simply referred to as a processing chip) as an execution subject.

For the step S101, in a first clock cycle of the current first clock cycle group, first data are respectively obtained from the plurality of data transmission channels; the data obtained by each data transmission channel in the first data includes VALID identifiers corresponding to the data transmission channels.

In this step, the processing chip on the transmitting side and the processing chip (i.e., the processing chip on the receiving side) are communicatively connected by a plurality of data transmission channels. And the processing chip at the transmitting side can transmit data to the processing chip through each data transmission channel in the first clock cycle of the current first clock cycle group. The data sent by the processing chip on the sending side through each data transmission channel includes a VALID identifier corresponding to the data transmission channel. At this time, the processing chip receives data, i.e., first data, transmitted by the processing chip on the transmitting side through each data transmission channel.

For convenience of understanding, the number of data transmission channels between the processing chip on the transmitting side and the processing chip is 16, and the bandwidth of each data transmission channel is 67 bit.

The processing chip at the transmitting side can divide data in one data packet or a plurality of data packets into a plurality of 64-bit data, and send each 64-bit data obtained by division to the processing chip through each output transmission channel, that is, the processing chip at the transmitting side sends 16 × 67-bit data each time. In addition to the 64-bit data obtained by splitting the data packet, each 67-bit data also includes a VALID identifier corresponding to each data transmission channel. At this time, the processing chip may obtain 16 data of 67 bits from the 16 data transmission channels, where the 16 data of 67 bits is the first data.

A plurality of data transmission channels may be provided between the processing chip and the sending side, and may be expanded according to user requirements, where the number of data transmission channels between the processing chip and the sending side is not particularly limited. For the sake of understanding, the following description will only take the number of data transmission channels as 16 and the bandwidth of each data transmission channel as 67 bits, which are not limiting.

In this embodiment, for each data packet, in at least one 64-bit data corresponding to the data packet, the first data includes the SOP of the data packet, and the last data includes the EOP of the data packet.

For the sake of understanding, a packet is divided into 5 64-bit data, i.e., data 1 to data 5. The processing chip on the transmitting side may transmit the data 1 to the data 5 corresponding to the data packet to the processing chip by using 5 data transmission channels, such as channel 1 to channel 5, respectively. The data volume transmitted by each data transmission channel is 67 bits, each 67-bit data includes VALID identification of the data transmission channel corresponding to the data, the 67-bit data transmitted by channel 1 further includes SOP of the data packet, and the 67-bit data transmitted by channel 5 further includes EOP of the data packet.

When the processing chip on the transmitting side transmits data to the processing chip through each data channel, the data may be any segment of data in a certain data packet, and therefore, the data may include SOP and/or EOP of the data packet in addition to the data and VALID identifier into which the data packet is split. Here, the content of the data transmitted by each data transmission channel is not particularly limited.

In this embodiment, when the processing chip on the transmitting side transmits data through a plurality of data transmission channels, at least one piece of data obtained by splitting each data packet may be transmitted to the processing chip according to a predetermined transmission method.

For example, a certain data packet is split into 16 data of 64 bits, i.e. data 0-data 15. The arrangement sequence of the data 0-data 15 is the arrangement sequence of each 64-bit data in the data packet. The processing chip at the transmitting side transmits data 0-data 15 to the processing chip, and the data can be transmitted to the processing chip sequentially through different data transmission channels according to the sequence of each 64-bit data in the data packet. For example, data 0 is sent through the data transmission channel 0, data 1 is sent through the data transmission channel 1, and so on, and the 16 data with 64 bits are sent to the processing chip through the corresponding data transmission channels.

And the processing chip sequences each 67bit of received data according to a predetermined receiving mode to obtain the first data.

The processing chip and the processing chip on the transmitting side can effectively ensure the orderliness of data transmission according to the predetermined transmitting mode and receiving mode.

In this embodiment of the present application, the VALID flag is used to indicate whether data in the data channel is VALID. For example, when the VALID identifier corresponding to a certain data transmission channel is the first numerical value, the data transmission channel is VALID, and the data transmitted by the data transmission channel is VALID data; when the VALID identifier corresponding to a certain data transmission channel is the second numerical value, the data transmission channel is invalid, and accordingly, the data transmitted by the data transmission channel is invalid data.

In an alternative embodiment, the first value may be 1, and the second value may be 0. Here, the first numerical value and the second numerical value are not particularly limited.

In this embodiment, since the data in the data packet sent to the processing chip by the processing chip on the sending side may be from a plurality of data packets, when the processing chip on the sending side sends data to the processing chip, a piece of invalid data, such as 67-bit invalid data, may be sent between two data packets. That is, after sending a data packet to the processing chip, the processing chip at the sending side may send a segment of invalid data, and after the sending of the invalid data is completed, send another data packet to the processing chip, thereby implementing the distinguishing of different data packets.

The processing chip on the transmitting side may be a chip in any device communicatively connected to the processing chip, and the device includes, but is not limited to, a user terminal, a server, and the like. Here, the device in which the processing chip on the transmitting side is located is not particularly limited.

The processing chip on the transmitting side may be a transmitting end of data, or may be a receiving end of data. For convenience of understanding, in the embodiment of the present application, only the processing chip on the transmitting side is taken as an example for explanation, and does not perform any limiting function.

In the embodiment of the application, the processing chip is in communication connection with the processing chip on the transmitting side. The number of the processing chips on the transmitting side may be one or more. When the number of the processing chips on the transmitting side is multiple, when the processing chip on each transmitting side transmits data to the processing chip, the routing protocol performs data transmission based on the Interlaken protocol. And the processing chip determines the processing chip of the sending side corresponding to each received first data according to the routing information carried in the received data.

In step S102, after the invalid data in the first data is shifted to the VALID data, the second data is obtained, where the VALID data is data transmitted by the data transmission channel whose VALID identifier is the first numerical value, and the invalid data is data transmitted by the data transmission channel whose VALID identifier is the second numerical value.

In this step, since the first data received by the processing chip may include VALID data and invalid data at the same time, in the first clock cycle, the processing chip determines, for the data acquired from each data transmission channel, whether the data is VALID data or invalid data according to the VALID identifier of the data transmission channel. When the first data includes invalid data, the processing chip may adjust a position of the invalid data and a position of the valid data in the first data to obtain second data. That is, the processing chip may move the invalid data in the first data to the valid data to obtain the second data.

For ease of understanding, the above-described position adjustment process of invalid data is exemplified.

The 16 data transmission channels between the processing chips on the transmitting side are channels 0 to 15. Now, assume that VALID identifiers corresponding to the channels 3 and 4 are the second value, and VALID identifiers of the other 14 data transmission channels are the first value. After the processing chip receives the first data, it may be determined that the data transmitted through the channels 3 and 4 in the first data is invalid data, and the data transmitted through the other 14 data transmission channels is valid data.

And the data transmitted by each data transmission channel received by the processing chip is represented by the arrangement sequence of the data transmission channels. If the arrangement sequence corresponding to the data transmitted through each data transmission channel in the first data is represented as: channel 0, channel 1, channel 2, channel 3, channel 4, channel 5, channel 6, channel 7, channel 8, channel 9, channel 10, channel 11, channel 12, channel 13, channel 14, channel 15. After determining that the data transmitted through the channels 3 and 4 are invalid data, the processing chip may adjust the data transmitted through the channels 3 and 4 to all valid data to obtain second data. At this time, the arrangement order corresponding to the data transmitted through each data transmission channel in the second data is represented as: channel 0, channel 1, channel 2, channel 5, channel 6, channel 7, channel 8, channel 9, channel 10, channel 11, channel 12, channel 13, channel 14, channel 15, channel 3, channel 4.

In the embodiment of the present application, since the invalid data is sent before one data packet is sent and another data packet is sent, the invalid data is between the EOP and the SOP of two data packets, and between the EOP of the previous data packet and the SOP of the next data packet. The processing chip adjusts the position of the invalid data in the first data, so that the effective data in the second data obtained by adjustment is always located before the invalid data, the situation that the head of the second residual data determined in the third clock cycle of the first clock cycle group in the later period is invalid data is avoided, the process of adjusting the position of the invalid data in the second residual data in the third clock cycle is avoided, the position of the invalid data is adjusted in the front period, the data processing process in each clock cycle of the first clock cycle group is balanced, the pressure of later-period data processing is relieved, the time required by later-period data processing is shortened, and the time sequence convergence capability of the processing chip is improved.

In the embodiment of the present application, the steps S101 to S102 are all executed in the first clock cycle of the first clock cycle group.

In step S103, in the second clock cycle of the first clock cycle group, the second data is buffered in the FIFO buffer, and the buffer data in the FIFO buffer is subjected to EOP position retrieval, so as to obtain a first retrieval result.

In the embodiment of the present application, the processing chip includes a register module. The register module may sample at a preset clock period.

In the first clock cycle group, the register module enters a new clock cycle every time sampling is performed. After the first clock cycle, the register module performs a sampling operation and enters a second clock cycle of the first clock cycle group. At this time, the processing chip may buffer the second data into the FIFO buffer.

In an optional embodiment, since the second data is data transmitted by a plurality of data transmission channels, the bandwidth corresponding to the second data is a sum of bandwidths of all the data transmission channels, such as 16 × 67 bits. In order to facilitate the buffering of the second data, the processing chip may combine the second data transmitted by the multiple data transmission channels into data corresponding to one data transmission channel, and buffer the data into the FIFO buffer.

For example, the data of 16 × 67 bits (the data has a length of 16) is combined into data of 1 × 1072 bits (the data has a length of 1).

In the embodiment of the present application, the FIFO buffer satisfies the output characteristic of first-in first-out. That is, in the FIFO buffer, the data stored first will be output preferentially.

After the second data is cached in the FIFO buffer, the processing chip may perform EOP position retrieval on the cache data in the FIFO buffer to obtain a first retrieval result.

In an optional embodiment, when the processing chip performs EOP position retrieval on the cache data in the FIFO buffer, it may sequentially determine whether the data is an EOP according to the sequence corresponding to each data cached in the FIFO buffer. If the first EOP is searched, the EOP searching process is stopped, and at the moment, the processing chip obtains a first searching result indicating the position of the first EOP in the cache data in the FIFO cache. If the first EOP is not retrieved from the FIFO cache, the EOP retrieval process is terminated, and at this time, the processing chip obtains a first retrieval result indicating that the cache data in the FIFO cache does not include the EOP.

In an optional embodiment, in order to improve the efficiency of the EOP position retrieval, when performing the EOP position retrieval on the cache data in the FIFO buffer, the EOP position retrieval may be performed on the previous preset number of cache data in the FIFO buffer. The first preset number of cache data in the FIFO cache is the cache data output by the FIFO cache in the third clock cycle of the first clock cycle group.

The preset number is determined according to the data amount sent by the processing chip at the sending side in each clock cycle. For example, the processing chip on the transmitting side transmits 16 × 67 bits of data every clock cycle, and at this time, the predetermined number may be 16 × 67 bits. Here, the predetermined number is not particularly limited.

In this embodiment, the buffering step of the second data and the retrieving step of the EOP position of the buffered data are both performed in the first clock cycle of the first clock cycle group.

In step S104, in a third clock cycle of the first clock cycle group, according to the first buoy position corresponding to the second clock cycle group, the first residual data, the preset buoy, and the buffer data output by the FIFO buffer are spliced to obtain a first spliced array of the first clock cycle group, so that the position of the preset buoy in the first spliced array is the first buoy position, the data before the preset buoy in the first spliced array is valid data in the first residual data, and the data after the preset buoy in the first spliced array is the buffer data output by the FIFO buffer.

In this step, after the second clock cycle of the first clock cycle group, when the register module performs sampling again, the third clock cycle of the first clock cycle group is entered. At this time, the FIFO buffer outputs the buffered data in the third clock cycle. The processing chip may obtain first residual data and a first buoy position corresponding to a last clock cycle group (i.e., a second clock cycle group) of the first clock cycle group, so as to splice the first residual data, the preset buoy, and cache data output by the FIFO buffer in a third clock cycle according to the first buoy position, thereby obtaining a first spliced array of the first clock cycle group. For the construction of the first concatenation array, reference is made to the following description, which is not specifically described here.

The first spliced array comprises effective data in the first residual data, a preset buoy and cache data output by an FIFO (first in first out) cache. In the first spliced array, the position of a preset buoy is the position of the first buoy, data before the preset buoy is effective data in the first residual data, and data after the preset buoy is buffer data output by FIFO buffer.

The second clock cycle group is a previous clock cycle group of the first clock cycle group. The first residual data is data which is not output in the second spliced array of the second clock period group.

In this embodiment of the application, in the third clock cycle of the second clock cycle group, after determining the first residual data, the processing chip may cache the first residual data in the residual cache. In the third clock cycle of the first clock cycle group, after the FIFO buffer outputs the buffer data, the register module samples the data, and the processing chip splices the first residual data in the residual buffer, the preset buoy and the FIFO buffer output buffer data to obtain a first spliced array.

The sampling of the register module before splicing processing is used for ensuring the synchronous processing of the first residual data, the preset buoy and the output buffer data of the FIFO buffer.

The preset buoy may be a preset identifier, such as a preset character, a preset numerical value, and the like. Here, the preset float is not particularly limited.

In this embodiment of the application, when the FIFO buffers the buffered data output in the third clock cycle, the buffered data may be re-split into the data correspondingly transmitted by the multiple data channels. For example, the data of 1 × 1072bit is divided into 16 × 67 bits again.

When the FIFO buffer outputs the buffered data, the data are output according to the first-in first-out sequence. The data amount of the output buffer data in each third clock cycle is the same, that is, the data amount of the output buffer data is the preset amount.

In the embodiment of the present application, after the FIFO buffers the buffered data output in each third clock cycle, the buffered data is still buffered in the FIFO buffer, that is, the buffered data output by the FIFO buffer is not discarded when the FIFO buffer outputs the buffered data.

The bandwidth of the first splicing array is determined according to the preset data output length. The product of the predetermined data output length and the predetermined data output width is used to indicate the maximum data amount of the valid data included in each data packet. For example, if the maximum data volume of the valid data included in each data packet is preset to be valid data of 9 × 64 bits, the preset data transmission length Q is 9, and the preset data output width is 64 bits. That is, for each data packet, the processing chip on the transmitting side can split the data packet into at most 9 64-bit data packets, and transmit the data packets to the processing chip through 9 data transmission channels.

The data volume of the buffered data output by the FIFO buffer each time is the same as the data volume of the second data, i.e. 16 × 67 bit. The length L of the first concatenation array may be a sum of the depth B of the residual buffer and the data transmission channel, i.e., L = B + 16.

The residual buffer is used for storing residual data corresponding to each clock cycle group. The depth of the residual buffer is B, i.e. the length of the residual data that can be accommodated by the residual buffer is B. The depth B of the residual buffer can be determined according to the preset data output length and the number of data transmission channels, namely B is more than or equal to 16+ Q-1.

For convenience of understanding, the preset data output length is 9, i.e., Q =9, for example. The depth B of the residual buffer is greater than or equal to 16+9-1=24, i.e. the minimum depth of the residual buffer is 24. At this time, the length L =24+16=40 of the first mosaic array. That is, the length corresponding to the first concatenation array is at least 40. Taking the data size (i.e. width) of each length of data as 67 bits as an example, the residual cache can store at least 24 x 67 bits of data, and the bandwidth corresponding to the first tile array is at least 40 x 67 bits.

In this embodiment, the length of the first concatenation array, the preset data output length, and the depth of the residual cache are not specifically limited.

And for the step S105, performing EOP position retrieval on the first residual data in the first concatenation array to obtain a second retrieval result.

In this step, after the processing chips are spliced to obtain the first spliced array in the third clock cycle of the first clock cycle group, the EOP position search may be performed on the first residual data in the first spliced array, that is, the EOP position search is performed on the valid data in the first spliced array, so as to obtain a second search result.

The process of performing EOP position search on the first residual data in the first concatenated array is similar to the process of performing EOP position search on the cache data in the FIFO buffer, and the process of performing EOP position search on the first residual data in the first concatenated array is not specifically described herein.

In this embodiment of the application, the second search result may indicate a position where a first EOP in the first residual data in the first mosaic array is located, or may indicate that the first residual data in the first mosaic array does not include the EOP. Here, the second search result is not particularly limited.

In step S106, according to the first search result and the second search result, when the first concatenated array meets the preset output condition, target data is output, where the target data is valid data between the first concatenated array and the target position where the first EOP is located.

In this step, the processing chip may determine whether the first concatenated array meets the preset output condition according to the first search result and the second search result. That is, whether the first tile array hits the predetermined output condition is determined. When the first spliced array meets the preset output condition, the processing chip can determine that the preset output condition is hit, and at the moment, the processing chip performs output operation, namely the processing chip outputs the target data in the first spliced array. For the output of the above target data, the following description is provided, and no specific description is made here.

The target data is effective data between the first position of the first spliced array and the target position of the first EOP.

In an alternative embodiment, when the first tile array does not satisfy the predetermined output condition, the processing chip may determine that the predetermined output condition is not hit, and at this time, the processing chip does not perform the output operation.

In the embodiment of the present application, the steps S104 to S106 are all executed in the third clock cycle of the first clock cycle group.

The first clock cycle group comprises the first clock cycle, the second clock cycle and the third clock cycle, and the duration corresponding to each clock cycle is the same and is determined by the sampling of the register. Here, the duration corresponding to each clock cycle in the first clock cycle group is not particularly limited.

In the embodiment of the present application, the processing procedure of the processing chip on the received data is performed according to the above steps S101 to S106, and for convenience of understanding, in the embodiment of the present application, the processing procedure of the received data is only described in the first clock cycle group. As for the other clock cycle groups, the data processing procedure of the data received in the second clock cycle group can refer to the data processing procedure of the data received in the first clock cycle group, and is not specifically described here.

In an optional embodiment, according to the method shown in fig. 1, an embodiment of the present application further provides a data processing method. As shown in fig. 2, fig. 2 is a second flowchart of the data processing method according to the embodiment of the present application. In this method, the step S104 is specifically subdivided into steps S1041 to S1043.

In step S1041, in the third clock cycle of the first clock cycle group, the buffer data output by the FIFO buffer is obtained.

In this step, the FIFO buffer outputs the buffered data during the third clock cycle of the first group of clock cycles. At this time, the processing chip acquires the cache data output by the FIFO cache.

Step S1042, a first residual data and a first buoy position corresponding to the second clock cycle group are obtained.

In the embodiment of the present application, in the third clock cycle of each clock cycle group, whether the tiled array of the clock cycle group outputs data or not, the remaining data in the tiled array will be determined as the residual data corresponding to the clock cycle group. And the processing chip also calculates the buoy position corresponding to the clock cycle group according to the output condition of the spliced array of the clock cycle group and the discarding condition of the cache data in the FIFO cache of the previous clock cycle group of the clock cycle group. The buoy position is used for indicating the position of a preset buoy in a spliced array of a next clock cycle group of the clock cycle group. As for the method of determining the position of the float, the following second method of determining the position of the float is referred to, and will not be described in detail.

In a third clock cycle of the first clock cycle group, the processing chip may obtain first residual data and a first buoy position corresponding to a previous clock cycle group (i.e., the second clock cycle group) of the first clock cycle group. The first residual data may be obtained from the residual buffer.

Step S1043, filling the first residual data into the preset splicing array, filling the preset buoy into a position corresponding to the first buoy position in the preset splicing array, and filling the buffer data output by the FIFO buffer after the buoy is preset, so as to obtain a first splicing array of the first clock cycle group.

In this step, the processing chip fills first residual data corresponding to the second clock cycle group from the first position of the preset concatenation array according to the first buoy position corresponding to the second clock cycle group, and fills the preset buoy to a position corresponding to the first buoy position in the preset concatenation array according to the first buoy position. At this time, the processing chip may fill the buffer data output by the FIFO buffer after the preset buoy included in the preset spliced array is preset, so as to obtain the first spliced array of the first clock cycle group.

In this embodiment, the first residual data corresponding to the second clock cycle group may or may not include invalid data. When the first residual data comprises invalid data, the first residual data in the first spliced array only comprises valid data, the valid data of the first residual data is followed by the preset buoy, and the valid data of the first residual data is followed by the buffer data output by the FIFO buffer; and when the first residual data does not comprise invalid data, all the first residual data in the first spliced array are the preset buoy after the first residual data, and the buffer data output by the FIFO buffer is obtained after the preset buoy.

Through the steps S1041 to S1043, the processing chip may accurately splice the first residual data, the preset buoy, and the buffer data output by the FIFO buffer to obtain a first spliced array, and through the position of the first buoy, it is effectively ensured that the first spliced array does not include invalid data in the first residual data, thereby avoiding an influence of the invalid data in the first residual data on the first spliced array.

In an optional embodiment, according to the method shown in fig. 1, an embodiment of the present application further provides a data processing method. As shown in fig. 3, fig. 3 is a third schematic flow chart of the data processing method according to the embodiment of the present application. In this method, the above-described step S106 is specifically subdivided into the following steps. Namely step S1061 to step S1062.

Step S1061, when the second search result indicates the position of the first EOP in the first residual data, or when the second search result indicates that the first residual data does not include the EOP and the first search result indicates the position of the first EOP in the cache data in the FIFO buffer, obtaining effective data between the first EOP and the target position in the first concatenated array as the target data.

In the embodiment of the present application, as shown in table 1, the first search result and the second search result have the following combination of 4.

TABLE 1

In table 1, when the second search result is position 1, it indicates that the position where the first EOP in the first residual data in the first concatenation array is located is position 1, and when the second search result is-time, it indicates that the first residual data in the first concatenation array does not include the EOP. When the first retrieval result is-time, the cache data in the FIFO cache does not comprise the EOP, and when the first retrieval result is position 2, the first EOP position in the cache data in the FIFO cache is position 2.

According to the first retrieval result and the second retrieval result, the first mosaic array has at least four conditions.

In the first case, the first EOP is included in the residual data portion (i.e., all data before the buoy is preset) included in the first mosaic array, but the EOP is not included in the buffered data portion (i.e., all data after the buoy is preset) included in the first mosaic array.

The above case one corresponds to case 1 shown in table 1 above. At this time, the position where the first EOP in the first concatenation array is located is the position where the first EOP in the residual data portion is located, such as position 1 shown in table 1.

In case two, the residual data portion included in the first tile array includes the first EOP, and the cache data portion included in the first tile array includes the first EOP.

The second case corresponds to case 2 shown in table 1. At this time, the position of the first EOP in the first concatenation array is the position of the first EOP in the residual data portion.

In case three, the residual data portion included in the first tile array does not include the EOP, but the cache data portion included in the first tile array includes the location of the first EOP.

Case three corresponds to case 3 shown in table 1. At this time, the position of the first EOP in the first concatenation array may be determined according to the length of the valid data of the residual data portion included in the first concatenation array (i.e., the length of the valid data in the first residual data packet), and the position of the first EOP indicated by the first search result.

In an alternative embodiment, when the third condition occurs, the position of the first EOP in the first tile array may be represented as: the sum of the length of the valid data of the first residual data and the position indicated by the first retrieval result, e.g., length of the valid data of the first residual data + position 2.

Both position 1 and position 2 data are expressed in length. For example, when the position 2 is 2, the position of the first EOP in the buffer data output from the FIFO buffer is the end of the second 67-bit data. In addition, the position 1 and the position 2 may be expressed as the data amount of the data. For example, when the position 2 is 2, the position of the first EOP in the buffer data output from the FIFO buffer is the position of the 2 × 67 th data.

In case four, the EOP is not included in the residual data portion included in the first tile array, but the EOP is included in the buffered data portion included in the first tile array.

The case four corresponds to the case 4 shown in table 1. At this time, the EOP is not included in the first tile array.

In the embodiment of the present application, the preset output condition may be expressed as: the second retrieval result indicates the position of the first EOP in the first residual data; can also be expressed as: the second search result indicates that the first residual data does not include an EOP, and the first search result indicates a position in the buffer data in the FIFO buffer where the first EOP is located.

In an optional embodiment, when the first tile array satisfies any one of the first condition, the second condition, or the third condition, the processing chip may determine that the first tile array satisfies the preset output condition, and at this time, the processing chip may output the target data in the first tile array.

In another optional embodiment, when the first tile array satisfies the fourth condition, the processing chip may determine that the first tile array does not satisfy the preset output condition, and at this time, the processing chip may determine that the preset output condition is not hit, and the processing chip does not output data.

In an optional embodiment, when the processing chip determines that the first stitched array satisfies the preset output condition, for the first or second condition, the processing chip may obtain valid data from the first position in the first stitched array to the position where the first EOP indicated by the second search result is located, as target data.

In another optional embodiment, when the processing chip determines that the first stitched array satisfies the preset output condition, for the third case, the processing chip may obtain all valid data from the first place in the first stitched array to the position where the first EOP indicated by the first search result is located, as the target data. That is, all data included in the residual data in the first concatenated array and valid data between the first bit and the first EOP in the cache data portion are determined as target data. At this time, the target data does not include the preset buoy in the first concatenated array.

In step S1062, target data is output.

In this embodiment, the target data is all valid data included in one complete data packet sent by the processing chip on the sending side, and therefore, the processing chip outputs only valid data included in one data packet in each third clock cycle.

Through the steps S1061 to S1062, the processing chip may accurately determine the target data in the first concatenated array when the first concatenated array meets the preset output condition, so as to output the target data, improve the accuracy of the determined target data, and ensure the accuracy of the data output by the processing chip.

In an optional embodiment, according to the method shown in fig. 1, an embodiment of the present application further provides a data processing method. As shown in fig. 4, fig. 4 is a fourth flowchart illustrating a data processing method according to an embodiment of the present application. The method comprises the following steps.

Step S401, in a first clock cycle of a current first clock cycle group, respectively acquiring first data from a plurality of data transmission channels; the data obtained by each data transmission channel in the first data includes VALID identifiers corresponding to the data transmission channels.

Step S402, shifting invalid data in the first data to VALID data to obtain second data, where the VALID data is data transmitted by a data transmission channel whose VALID identifier is a first numerical value, and the invalid data is data transmitted by a data transmission channel whose VALID identifier is a second numerical value.

Step S403, in a second clock cycle of the first clock cycle group, buffering the second data into the FIFO buffer, and performing EOP position retrieval on the buffered data in the FIFO buffer to obtain a first retrieval result.

Step S404, in a third clock cycle of the first clock cycle group, according to a first buoy position corresponding to the second clock cycle group, the first residual data, the preset buoy, and the buffer data output by the FIFO buffer are spliced to obtain a first spliced array of the first clock cycle group, so that the position of the preset buoy in the first spliced array is the first buoy position, data before the preset buoy in the first spliced array is valid data in the first residual data, and data after the preset buoy in the first spliced array is the buffer data output by the FIFO buffer.

Step S405, EOP position retrieval is carried out on the first residual data in the first spliced array, and a second retrieval result is obtained.

Step S406, outputting target data when the first spliced array meets the preset output condition according to the first retrieval result and the second retrieval result, wherein the target data is effective data between the first spliced array and the target position where the first EOP is located.

The above-described steps S401 to S406 are the same as the above-described steps S101 to S106.

Step S407, count a first length of valid data in the buffer data output by the FIFO buffer in the third clock cycle, and a second length of valid data in the residual data not output in the first concatenated array.

In this embodiment of the application, in the third clock cycle of the first clock cycle group, the processing chip may count the length of valid data in the cache data output by the FIFO buffer, and record the length as the first length.

In each clock cycle group, since the buffer data in the FIFO buffer may or may not include invalid data, the length of the valid data included in the buffer data output by the FIFO buffer is also different in the third clock cycle of each clock cycle group.

In this embodiment, in the third clock cycle of the first clock cycle group, the first tile array may or may not output the target data according to a difference between matching conditions of the first tile array and a preset output condition. At this time, no matter whether the first concatenation array outputs data or not, the processing chip counts the length of valid data in the residual data which is not output in the first concatenation array, and records the length as the second length.

In an optional embodiment, when the first tile array outputs the target data in a third clock cycle of the first clock cycle group, the second length is a difference between a length of valid data in the first tile array and a length of the target data in the first tile array, which is specifically expressed as: the second length = length of valid data in the first mosaic array-length of target data in the first mosaic array.

In another optional embodiment, when the first tile array does not output data in the third clock cycle of the first clock cycle group, the second length is the length of valid data in the first tile array.

In this embodiment, after determining the first length and the second length, the processing chip may determine whether the FIFO buffer in the second clock cycle group has been discarded and a current state of the FIFO buffer in a third clock cycle of the first clock cycle group. Specifically, as shown in table 2, the following cases may be included.

TABLE 2

In the embodiment of the present application, since the step S407 is performed after the step S406, that is, after the FIFO buffer outputs the buffer data.

Step S408, if the FIFO buffer is discarded in the second clock cycle group, or the current state of the FIFO buffer is changed from empty to non-empty in the third clock cycle, the FIFO buffer is discarded when the sum of the first length and the second length is less than or equal to the preset length threshold.

In this step, when the FIFO buffer is buffered in the data discarding condition of the second clock cycle group and the current state of the FIFO buffer in the third clock cycle of the first clock cycle group matches any one of the conditions 1, 2, and 3 shown in table 2, the processing chip may calculate the sum of the first length and the second length and compare the sum with the preset length threshold. When the sum of the first length and the second length is less than or equal to the preset length threshold, the processing chip may discard the cache data in the FIFO buffer, that is, discard a preset number of cache data from the FIFO buffer.

In an alternative embodiment, when the data discard condition of the FIFO buffer in the second clock cycle and the current state of the FIFO buffer in the third clock cycle of the first clock cycle group match any one of the cases 1, 2, and 3 shown in table 2, if the sum of the first length and the second length is greater than the preset length threshold, the processing chip may determine that the discard operation on the buffered data in the FIFO buffer is not needed.

When the FIFO buffer is discarded, the amount of the buffer data discarded each time may be the preset amount.

The preset length threshold may be a depth corresponding to the residual cache. For example, when the depth of the residual buffer is 24, the preset length threshold is 24. Here, the preset length threshold is not particularly limited.

In an alternative embodiment, the above-mentioned discarding the data in the FIFO buffer is specifically indicated as performing a drop (POP) operation on the data in the FIFO buffer.

Step S409, if the FIFO buffer is not discarded in the second clock cycle group and the FIFO buffer is not cached in the third clock cycle, discarding the data of the FIFO buffer when the second length is less than or equal to the preset length threshold.

In this step, when the FIFO buffer has the data discarding condition of the second clock cycle and the current status of the FIFO buffer in the third clock cycle of the first clock cycle group matches the condition 4 shown in table 2, the processing chip may compare the second length with the preset length threshold. When the second length is less than or equal to the preset length threshold, the processing chip may discard the cache data in the FIFO buffer, that is, discard a preset number of cache data from the FIFO buffer.

In an alternative embodiment, when the data discard condition of the FIFO buffer in the second clock cycle and the current state of the FIFO buffer in the third clock cycle of the first clock cycle group match the condition 4 shown in table 2, if the second length is greater than the preset length threshold, the processing chip may determine that the discard operation on the data in the FIFO buffer is not required.

Both the above steps S408 and S409 are to discard the buffer data in the FIFO buffer, and different steps are executed for different situations. That is, when case 1, case 2, or case 3 shown in table 2 is satisfied, the above-described step S408 is executed, and when case 4 shown in table 2 is satisfied, the above-described step S409 is executed. Here, the execution of step S408 and step S409 is not particularly limited.

The steps S407 to S409 are performed in the third clock cycle of the first clock cycle group. That is, the FIFO buffer performs the data discard operation in the third clock cycle of each clock cycle group.

Through the steps S407 to S409, the processing chip may determine whether to discard the data in the FIFO buffer in each clock cycle group, and when it is ensured that the output data is discarded, it is effectively ensured that the length of the residual data corresponding to the clock cycle group does not exceed the preset length threshold, thereby ensuring that no overflow occurs in the residual buffer.

In an optional embodiment, according to the method shown in fig. 1, an embodiment of the present application further provides a data processing method. As shown in fig. 5, fig. 5 is a fifth flowchart illustrating a data processing method according to an embodiment of the present application. The method comprises the following steps.

Step S501, in a first clock cycle of a current first clock cycle group, respectively acquiring first data from a plurality of data transmission channels; the data obtained by each data transmission channel in the first data includes VALID identifiers corresponding to the data transmission channels.

Step S502, after the invalid data in the first data is shifted to VALID data, second data is obtained, where the VALID data is data transmitted by a data transmission channel whose VALID identifier is the first numerical value, and the invalid data is data transmitted by a data transmission channel whose VALID identifier is the second numerical value.

Step S503 is to cache the second data into the FIFO buffer in the second clock cycle of the first clock cycle group, and perform EOP position retrieval on the cache data in the FIFO buffer to obtain the first retrieval result.

Step S504, in a third clock cycle of the first clock cycle group, according to the first buoy position corresponding to the second clock cycle group, the first residual data, the preset buoy, and the buffer data output by the FIFO buffer are spliced to obtain a first spliced array of the first clock cycle group, so that the position of the preset buoy in the first spliced array is the first buoy position, the data before the preset buoy in the first spliced array is valid data in the first residual data, and the data after the preset buoy in the first spliced array is the buffer data output by the FIFO buffer.

Step S505, performing EOP position retrieval on the first residual data in the first concatenated array to obtain a second retrieval result.

Step S506, outputting target data when the first spliced array meets the preset output condition according to the first retrieval result and the second retrieval result, wherein the target data is effective data between the first spliced array and the target position where the first EOP is located.

The above steps S501 to S506 are the same as the above steps S101 to S106.

Step S507, obtaining data not output in the first tile array in the third clock cycle, and using the data as second residual data corresponding to the first clock cycle group.

In this step, in the third clock cycle of the first clock cycle group, no matter whether the first tile array performs data output, the processing chip will obtain the residual data that is not output in the first tile array, and obtain the second residual data corresponding to the first clock cycle group.

The manner of acquiring the first residual data corresponding to the second clock cycle group may refer to the manner of acquiring the second residual data, and will not be described in detail here.

Step S508, determining a second buoy position corresponding to the first clock cycle group according to the output condition of the first concatenated group in the third clock cycle and the discarding condition of the buffered data in the FIFO buffer in the second clock cycle group.

In this step, in a third clock cycle of the first clock cycle group, the processing chip may determine a second buoy position corresponding to the first clock cycle group according to an output condition of the first concatenated array in the third clock cycle and a discarding condition of the buffered data buffered in the FIFO in the second clock cycle group. Namely, the position of the preset buoy in the spliced array of the next clock cycle group of the first clock cycle group is determined. The determination of the position of the second buoy is described below and will not be described in detail.

Both steps S507 and S508 are performed in the third clock cycle of the first clock cycle group. That is, the residual data and float position for each clock cycle group are determined during the third clock cycle of the clock cycle group. Here, the execution order of step S507 and step S508 is not particularly limited.

Through the steps S507 and S508, the processing chip may accurately determine the second residual data and the second buoy position corresponding to the current first clock cycle group, so that in the third clock cycle of the next clock cycle group (denoted as the third clock cycle group) of the first clock cycle group, according to the second buoy position, the second residual data, the preset buoy, and the buffer data buffered in the third clock cycle of the FIFO in the third clock cycle group are spliced to obtain the third spliced array corresponding to the third clock cycle group, thereby outputting data of the third clock cycle group. The third concatenation array is obtained by referring to the first concatenation array, and is not specifically described herein.

In an optional embodiment, based on the method shown in fig. 5, an embodiment of the present application further provides a data processing method. As shown in fig. 6, fig. 6 is a sixth flowchart illustrating a data processing method according to an embodiment of the present application. In this method, step S508 is specifically subdivided into steps from step S5081 to step S5084.

In step S5081, if no data is output from the first tile array in the third clock cycle and no data is discarded from the FIFO buffer in the second clock cycle, it is determined that the second buoy position corresponding to the first clock cycle is the first buoy position.

In this step, when no data is output from the first concatenated array in the third clock cycle and no data discard is performed on the FIFO buffer in the second clock cycle group, the processing chip may determine the first buoy position as a second buoy position corresponding to the first clock cycle group. That is, the position of the preset buoy is not changed.

In step S5082, if the target data is output from the first concatenated array in the third clock cycle but the FIFO buffer is not discarded in the second clock cycle, the position indicated by the difference between the first buoy position and the third length is determined as the second buoy position corresponding to the first clock cycle, and the third length is the length of the valid data output from the first concatenated array in the third clock cycle.

In this step, when the target data is output from the first concatenated array in the third clock cycle but the FIFO buffer is not discarded in the second clock cycle, the processing chip may count the length of the valid data output from the first concatenated array in the third clock cycle of the first clock cycle (denoted as the third length), that is, count the length of the target data output in step S506, calculate a difference between the first buoy position and the third length, and determine a position indicated by the difference as the second buoy position corresponding to the first clock cycle. That is, the second buoy position can be expressed as: first buoy position-second length.

In step S5083, if no data is output in the first concatenated array in the third clock cycle but data in the FIFO buffer is discarded in the second clock cycle group, the position indicated by the value of the fourth length of the valid data in the first concatenated array is determined as the second buoy position corresponding to the first clock cycle group.

In this step, when no data is output in the first concatenated array in the third clock cycle but data of the FIFO buffer is discarded in the second clock cycle, the processing chip may determine a position indicated by a value of the fourth length of valid data in the first concatenated array as a second float position corresponding to the first clock cycle. That is, the second buoy position can be expressed as: a fourth length.

In step S5084, if the target data is output from the first concatenated array in the third clock cycle and the FIFO buffer is discarded in the second clock cycle, the position indicated by the difference between the fourth length and the third length is determined as the second float position corresponding to the first clock cycle.

In this step, when the target data is output from the first concatenated array in the third clock cycle and the data of the FIFO buffer is discarded in the second clock cycle group, the processing chip may calculate a difference between the fourth length and the third length, and determine a position indicated by the difference as a second buoy position corresponding to the first clock cycle group. That is, the second float position corresponding to the first clock cycle group is the difference between the length of the valid data in the first concatenated array and the length of the output target data, and is specifically expressed as: fourth length-third length.

The second float position may be referred to as a first float position determination method corresponding to the second clock cycle group, and the first float position determination corresponding to the second clock cycle group is not specifically described here.

For the above steps S5081 to S5084, different steps are performed according to the output condition of the first tile array in the third clock cycle and the discard condition of the buffered data of the FIFO buffer in the second clock cycle group. Here, the execution of steps S5081 to S5084 is not particularly limited.

Through the steps S5081 to S5084, the processing chip may accurately determine the position of the float corresponding to each clock cycle group, so as to indicate the position of the preset float in the concatenated array corresponding to the next clock cycle group of the current clock cycle group, and while ensuring the accuracy of the determined position of the preset float, the processing chip may make the data before the preset float in the concatenated array corresponding to the next clock cycle group only be the valid data portion in the residual data corresponding to the current clock cycle group, that is, the invalid data portion in the residual data corresponding to the current clock cycle group in the concatenated array corresponding to the next clock cycle group is covered by the buffer data output by the preset float and the FIFO buffer of the next clock cycle group, and ensure that the residual data portion in the concatenated array spliced based on the float position in the next clock cycle group does not include invalid data, the accuracy of the spliced array is improved, and the target data in the later period can be conveniently output.

Based on the same inventive concept, according to the data processing method provided by the embodiment of the present application, the embodiment of the present application further provides a data processing apparatus. As shown in fig. 7, fig. 7 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present application. The apparatus includes the following modules.

A first obtaining module 701, configured to obtain first data from multiple data transmission channels in a first clock cycle of a current first clock cycle group; the data obtained by each data transmission channel in the first data comprises a VALID identifier corresponding to the data transmission channel;

a shifting module 702, configured to shift invalid data in the first data to VALID data to obtain second data, where the VALID data is data transmitted by a data transmission channel whose VALID identifier is a first numerical value, and the invalid data is data transmitted by a data transmission channel whose VALID identifier is a second numerical value;

a first retrieving module 703, configured to cache the second data into the FIFO buffer in the second clock cycle of the first clock cycle group, and perform EOP position retrieval on the cache data in the FIFO buffer to obtain a first retrieval result;

the splicing module 704 is configured to splice the first residual data, the preset buoy, and the buffer data output by the FIFO buffer according to the first buoy position corresponding to the second clock cycle group in the third clock cycle of the first clock cycle group to obtain a first spliced array of the first clock cycle group, so that the position of the preset buoy in the first spliced array is the first buoy position, data before the preset buoy in the first spliced array is valid data in the first residual data, and data after the preset buoy in the first spliced array is buffer data output by the FIFO buffer; the second clock cycle group is a previous clock cycle group of the first clock cycle group, and the first residual data is data which is not output in a second splicing array of the second clock cycle group;

the second retrieval module 705 is configured to perform EOP position retrieval on the first residual data in the first concatenation array to obtain a second retrieval result;

and the output module 706 is configured to output target data when the first concatenated array meets a preset output condition according to the first search result and the second search result, where the target data is valid data between a first position of the first concatenated array and a target position of the first EOP.

Optionally, the output module 706 may be specifically configured to, when the second search result indicates a position where a first EOP in the first residual data is located, or when the second search result indicates that the first residual data does not include the EOP and the first search result indicates a position where the first EOP in the cache data in the FIFO buffer is located, obtain valid data between the first EOP and the target position in the first concatenation array, as target data; and outputting the target data.

Optionally, the data processing apparatus may further include:

the statistical module is used for counting a first length of effective data in the cache data output by the FIFO cache in the third clock cycle and a second length of effective data in the residual data which are not output in the first splicing array;

the first discarding module is used for discarding data of the FIFO cache when the sum of the first length and the second length is less than or equal to a preset length threshold value if the data of the FIFO cache is discarded in the second clock cycle group or the current state of the FIFO cache is changed from empty to non-empty in the third clock cycle;

and the second discarding module is used for discarding the data of the FIFO cache when the second length is less than or equal to the preset length threshold if the data of the FIFO cache is not discarded in the second clock cycle group and the data of the FIFO cache is not cached in the third clock cycle.

Optionally, the data processing apparatus may further include:

the second obtaining module is used for obtaining data which is not output in the first splicing array in the third clock cycle and is used as second residual data corresponding to the first clock cycle group;

and the determining module is used for determining a second buoy position corresponding to the first clock cycle group according to the output condition of the first spliced array in the third clock cycle and the discarding condition of the cache data in the FIFO cache in the second clock cycle group.

Optionally, the determining module may be specifically configured to determine that a second buoy position corresponding to the first clock cycle group is a first buoy position if no data is output in the first concatenation array in the third clock cycle and no data discard is performed on the FIFO buffer in the second clock cycle group;

if target data are output from the first spliced array in the third clock cycle but data discarding is not performed on the FIFO buffer in the second clock cycle, determining a position indicated by a difference value between a value of the first buoy position and a value of a third length as a second buoy position corresponding to the first clock cycle, wherein the third length is the length of valid data output from the first spliced array in the third clock cycle;

if no data is output in the first spliced array in the third clock cycle but data discarding is performed on the FIFO cache in the second clock cycle, determining the position indicated by the value of the fourth length of the effective data in the first spliced array as a second buoy position corresponding to the first clock cycle group;

and if the target data is output from the first spliced array in the third clock cycle and the data of the FIFO buffer is discarded in the second clock cycle, determining the position indicated by the difference value between the value of the fourth length and the value of the third length as the position of the second buoy corresponding to the first clock cycle.

Optionally, the splicing module 704 may be specifically configured to obtain cache data output by the FIFO buffer in a third clock cycle of the first clock cycle group;

acquiring first residual data and a first buoy position corresponding to a second clock period group;

and filling the first residual data into the preset spliced array, filling the preset buoy into a position corresponding to the position of the first buoy in the preset spliced array, and filling the buffer data output by the FIFO buffer after the buoy is preset to obtain the first spliced array of the first clock cycle group.

By the device provided by the embodiment of the application, in the first clock cycle of the current first clock cycle group, the second data is obtained by shifting the invalid data in the received first data to the valid data; caching second data into the FIFO cache in a second clock cycle of the first clock cycle group, and performing EOP position retrieval on cache data in the FIFO cache to obtain a first retrieval result; splicing the first residual data, the preset buoy and the cache data output by the FIFO cache in a third clock cycle of the first clock cycle group to obtain a first spliced array of the first clock cycle group; performing EOP position retrieval on the first residual data in the first spliced array to obtain a second retrieval result; and outputting the target data when the first spliced array meets the preset output condition according to the first retrieval result and the second retrieval result.

Based on the same inventive concept, according to the data processing method provided by the embodiment of the present application, the embodiment of the present application further provides a processing chip, which is the processing chip. The processing chip is used for executing any one of the steps shown in fig. 1-6.

In an alternative embodiment, as shown in fig. 8, the processing chip may include a chip 801 and a machine-readable storage medium 802, where the machine-readable storage medium 802 stores machine-executable instructions capable of being executed by the chip 801, and the chip 801 is caused by the machine-executable instructions to implement any of the steps shown in fig. 1 to fig. 6.

In an alternative embodiment, as shown in fig. 8, the processing chip may further include: a high-speed serial bus 803; the chip 801 and the machine-readable storage medium 802 communicate with each other via the high-speed serial bus 803.

In an alternative embodiment, as shown in FIG. 8, the chip 801 may also be communicatively coupled to chip peripherals 804 via a high-speed serial bus 803. The data transmitted by the data transmission channels are buffered in the chip peripherals 804, and the chip peripherals 804 transmit the buffered data to the chip 801 through the high-speed serial bus 803. The chip 801 converts the received serial data into parallel data based on the Interlaken protocol, and implements any one of the steps shown in fig. 1-6 according to the machine executable instructions.

Based on the same inventive concept, according to the data processing method provided in the embodiments of the present application, the embodiments of the present application further provide a machine-readable storage medium, where the machine-readable storage medium stores machine-executable instructions that can be executed by a processing chip. The processing chip is caused by machine executable instructions to implement any of the steps shown in fig. 1-6 above.

Based on the same inventive concept, according to the data processing method provided in the embodiment of the present application, the embodiment of the present application further provides a computer program product containing instructions, which when run on a computer, causes the computer to perform any one of the steps shown in fig. 1 to 6.

The high-speed Serial Bus may be a Universal Serial Bus (USB), a Serial Peripheral Interface (SPI), or the like.

The machine-readable storage medium may include a RAM (Random Access Memory) and a NVM (Non-Volatile Memory), such as at least one disk Memory. Additionally, the machine-readable storage medium may be at least one memory device located remotely from the aforementioned processing chip.

The Processing chip may be a general Processing chip, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also DSPs (Digital Signal Processing), ASICs (Application Specific Integrated circuits), FPGAs (Field Programmable Gate arrays) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components.

The chip peripheral may be an external Memory, such as a Random Access Memory (RAM) or a Static Random Access Memory (SRAM); the processing chip described above may also be used.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for embodiments of the data processing apparatus, the processing chip, the machine-readable storage medium, the computer program product, and the like, the description is relatively simple due to the data processing method embodiment, and relevant points can be referred to the partial description of the data processing method embodiment.

The above description is only for the preferred embodiment of the present application, and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A data processing method is applied to a processing chip of an inter-chip high speed transmission data protocol outer ILKN-LA, and comprises the following steps:

respectively acquiring first data from a plurality of data transmission channels in a first clock cycle of a current first clock cycle group; the data obtained by each data transmission channel in the first data comprises an effective VALID identifier corresponding to the data transmission channel;

in the second clock cycle of the first clock cycle group, caching the second data into a first-in first-out (FIFO) cache, and performing data packet End (EOP) position retrieval on the cache data in the FIFO cache to obtain a first retrieval result;

according to the first retrieval result and the second retrieval result, outputting target data when the first spliced array meets a preset output condition, wherein the target data is effective data between the first spliced array and a target position where a first EOP is located, and the preset output condition is as follows: the second retrieval result indicates the position of the first EOP in the first residual data, or the second retrieval result indicates that the first residual data does not include the EOP and the first retrieval result indicates the position of the first EOP in the cache data in the FIFO cache.

2. The method according to claim 1, wherein the step of outputting the target data when the first concatenated array meets a preset output condition according to the first search result and the second search result comprises:

when the second retrieval result indicates the position of the first EOP in the first residual data, or when the second retrieval result indicates that the first residual data does not include the EOP and the first retrieval result indicates the position of the first EOP in the cache data in the FIFO cache, acquiring effective data between the first EOP in the first spliced array and the target position as target data;

and outputting the target data.

3. The method according to claim 1 or 2, characterized in that the method further comprises:

counting a first length of effective data in the cache data output by the FIFO cache in the third clock cycle and a second length of effective data in the residual data which are not output in the first splicing array;

if the FIFO cache is subjected to data discarding in the second clock cycle group or the current state of the FIFO cache is changed from empty to non-empty in the third clock cycle, when the sum of the first length and the second length is less than or equal to a preset length threshold, the FIFO cache is subjected to data discarding;

and if the FIFO cache is not subjected to data discarding in the second clock cycle group and is not subjected to data caching in the third clock cycle, discarding the data of the FIFO cache when the second length is less than or equal to the preset length threshold.

4. The method of claim 3, further comprising:

acquiring data which is not output in the first splicing array in the third clock cycle, and taking the data as second residual data corresponding to the first clock cycle group;

and determining a second buoy position corresponding to the first clock cycle group according to the output condition of the first spliced array in the third clock cycle and the discarding condition of the cache data in the FIFO cache in the second clock cycle group.

5. The method according to claim 4, wherein the step of determining the second buoy position corresponding to the first clock cycle group according to the output condition of the first tile array in the third clock cycle and the discard condition of the buffered data in the FIFO buffer in the second clock cycle group comprises:

if no data is output in the first spliced array in the third clock cycle and no data discarding is performed on the FIFO cache in the second clock cycle, determining that a second buoy position corresponding to the first clock cycle is the first buoy position;

if the target data is output from the first concatenated array in the third clock cycle but the data of the FIFO buffer is not discarded in the second clock cycle group, determining a position indicated by a difference between the first buoy position and a third length as a second buoy position corresponding to the first clock cycle group, where the third length is a length of valid data output from the first concatenated array in the third clock cycle;

if no data is output in the first spliced array in the third clock cycle but data discarding is performed on the FIFO buffer in the second clock cycle, determining a position indicated by a value of a fourth length of valid data in the first spliced array as a second buoy position corresponding to the first clock cycle;

and if the target data is output from the first spliced array in the third clock cycle and the data of the FIFO buffer is discarded in the second clock cycle, determining the position indicated by the difference between the fourth length and the third length as a second buoy position corresponding to the first clock cycle.

6. The method according to claim 1, wherein the step of splicing the first residual data, the preset buoy and the buffer data output by the FIFO buffer according to the first buoy position corresponding to the second clock cycle group in the third clock cycle of the first clock cycle group to obtain the first spliced array of the first clock cycle group comprises:

in the third clock cycle of the first clock cycle group, obtaining the cache data output by the FIFO cache;

acquiring first residual data and a first buoy position corresponding to the second clock period group;

and filling the first residual data into a preset splicing array, filling a preset buoy into a position corresponding to the position of the first buoy in the preset splicing array, and filling the cache data output by the FIFO cache after the buoy is preset to obtain the first splicing array of the first clock cycle group.

7. A data processing apparatus, provided in a processing chip of an ILKN-LA side of an inter-chip high speed data protocol, the apparatus comprising:

the first acquisition module is used for respectively acquiring first data from the plurality of data transmission channels in a first clock cycle of the current first clock cycle group; the data obtained by each data transmission channel in the first data comprises an effective VALID identifier corresponding to the data transmission channel;

the first retrieval module is used for caching the second data into a first-in first-out (FIFO) cache in a second clock cycle of the first clock cycle group, and performing data packet End (EOP) position retrieval on cache data in the FIFO cache to obtain a first retrieval result;

an output module, configured to output target data when the first stitched array meets a preset output condition according to the first retrieval result and the second retrieval result, where the target data is valid data between a first position of the first stitched array and a target position of the first EOP, and the preset output condition is: the second retrieval result indicates the position of the first EOP in the first residual data, or the second retrieval result indicates that the first residual data does not include the EOP and the first retrieval result indicates the position of the first EOP in the cache data in the FIFO cache.

8. The apparatus according to claim 7, wherein the output module is specifically configured to, when the second search result indicates a location where a first EOP in the first residual data is located, or when the second search result indicates that the first residual data does not include an EOP, and the first search result indicates a location where a first EOP in the cache data in the FIFO buffer is located, obtain valid data between a first bit in the first concatenation array and the target location as target data; and outputting the target data.

9. The apparatus of claim 7 or 8, further comprising:

the counting module is used for counting a first length of effective data in the cache data output by the FIFO cache in the third clock period and a second length of effective data in the residual data which are not output in the first splicing array;

a first discarding module, configured to discard data of the FIFO buffer if the data of the FIFO buffer is discarded in the second clock cycle group, or a current state of the FIFO buffer changes from null to non-null in the third clock cycle, when a sum of the first length and the second length is less than or equal to a preset length threshold value, discard the data of the FIFO buffer;

and the second discarding module is configured to discard the data of the FIFO buffer if the data of the FIFO buffer is not discarded in the second clock cycle group and the data of the FIFO buffer is not cached in the third clock cycle, and discard the data of the FIFO buffer if the second length is less than or equal to the preset length threshold.

10. The apparatus of claim 9, further comprising:

a second obtaining module, configured to obtain data that is not output in the first concatenation array in the third clock cycle, where the data is used as second residual data corresponding to the first clock cycle group;

and the determining module is used for determining a second buoy position corresponding to the first clock cycle group according to the output condition of the first splicing array in the third clock cycle and the discarding condition of the cache data in the FIFO cache in the second clock cycle group.

11. The apparatus of claim 10, wherein the determining module is specifically configured to determine a second buoy position corresponding to the first clock cycle group as the first buoy position if no data is output from the first tiled array in the third clock cycle and no data is discarded from the FIFO buffer in the second clock cycle group;

if the target data is output from the first concatenated array in the third clock cycle but the FIFO buffer is not discarded in the second clock cycle, determining a position indicated by a difference between a value of the first buoy position and a value of a third length as a second buoy position corresponding to the first clock cycle, where the third length is a length of valid data output from the first concatenated array in the third clock cycle;

and if the target data is output from the first spliced array in the third clock cycle and the data of the FIFO buffer is discarded in the second clock cycle, determining the position indicated by the difference value between the value of the fourth length and the value of the third length as a second buoy position corresponding to the first clock cycle.

12. The apparatus according to claim 7, wherein the concatenation module is specifically configured to obtain the buffer data output by the FIFO buffer in a third clock cycle of the first clock cycle group;

13. A processing chip for performing the method steps of any of claims 1-6.

14. A machine-readable storage medium storing machine-executable instructions executable by a processing chip, the processing chip being caused by the machine-executable instructions to: carrying out the method steps of any one of claims 1 to 6.