CN116804977A - Inter-chip data transmission system and inter-chip data transmission method - Google Patents

Abstract

The application relates to an inter-chip data transmission system and an inter-chip data transmission method, wherein the system comprises a routing module, a flow control circuit and an inter-chip channel module, the routing module comprises a sending route and a receiving route, the flow control circuit is respectively connected with the sending route and the receiving route, and the inter-chip channel module is connected with the flow control circuit; the inter-chip channel module is used for receiving the data segment sent by the sending route and forwarding the data segment to the outside of the chip, and receiving the data segment outside the chip and forwarding the data segment to the receiving route; the flow control circuit is used for caching the data segments, controlling the number of the data segments received by the receiving route according to the credit threshold value, ensuring that the number of the remaining cacheable data segments in the caching space is known by an upstream sender in time, and solving the problem that the control of a flow control mechanism on data transmission is inaccurate and data packets are lost in the related technology.

Description

Inter-chip data transmission system and inter-chip data transmission method

Technical Field

The present application relates to the field of multi-core processors, and in particular, to an inter-chip data transmission system and an inter-chip data transmission method.

Background

To break through the limitations of integrated circuits in terms of manufacturing scale and power density, chiplet technology has been developed. The chip technology can improve the diversity of chip functions, divide a complex chip into different parts according to different functions, realize each function in a die (die) mode, and enable each die to be heterogeneous or come from different manufacturers and apply optimized products obtained by different process nodes. With the increasing number of dies in a system, inter-die network technology replaces the traditional bus technology to achieve data communication between dies. One of the key technologies of the inter-chip network is flow control, and a flow control module with buffer is generally adopted to provide buffer space for data packets, so that the bandwidth is effectively saved. The buffered flow control module can be divided into data packet buffer flow control and microchip buffer flow control according to different forces of the allocation buffer areas, wherein the conventional structure of the microchip buffer flow control is worm-hole flow control, and the worm-hole flow control adopts a mode of buffering input data into groups, so that a plurality of input data can logically use the same data channel.

Because the inter-chip network does not support data retransmission, data packets are not allowed to be lost during transmission. If the flow control mechanism does not accurately control data transmission, and when the buffer space of the downstream router on the transmission path is full, the upstream router continuously transmits data, a phenomenon of losing data packets may occur. In view of the problem that the control of the data transmission by the flow control mechanism in the related art is inaccurate, and thus the data packet is lost, no effective solution has been proposed yet.

Disclosure of Invention

In this embodiment, an inter-chip data transmission system and an inter-chip data transmission method are provided to solve the problem that in the related art, the flow control mechanism is inaccurate in controlling data transmission, resulting in missing data packets.

In a first aspect, in this embodiment, there is provided an inter-chip data transmission system, where the inter-chip data transmission system includes a routing module, a flow control circuit, and an inter-chip channel module, where the routing module includes a sending route and a receiving route, the flow control circuit is connected to the sending route and the receiving route, and the inter-chip channel module is connected to the flow control circuit;

the inter-chip channel module is used for receiving the data segment sent by the sending route and forwarding the data segment to the outside of the chip, and receiving the data segment outside the chip and forwarding the data segment to the receiving route;

the flow control circuit is used for caching the data segments and controlling the number of the data segments received by the receiving route according to the credit threshold.

In some embodiments, the flow control circuit includes a receiving flow control circuit connected to the receiving route, where the receiving flow control circuit includes an analysis module, a receiving buffer queue and a flow controller that are sequentially connected, the analysis module is connected to the inter-chip channel module, and the receiving buffer queue and the flow controller are connected to the receiving route;

The analysis module is used for analyzing the intra-chip interface format data segment sent by the inter-chip channel module into a data segment to be received;

the receiving buffer queue is used for buffering the data segment to be received;

the flow controller is used for controlling the number of the data segments to be received read from the receiving cache queue according to the credit threshold.

In some embodiments, the parsing module is further configured to determine whether the data segment to be received is valid based on a parsing result; and writing the data segment to be received into the receiving cache queue under the condition that the data segment to be received is valid and the receiving cache queue is not full.

In some embodiments, the flow controller is configured to obtain a cumulative number of data segments buffered in the receive buffer queue from a preset time, and a cumulative number of credit pulses sent by the receive route from the preset time;

and under the condition that the difference value between the accumulated number of the data segments and the accumulated number of the credit pulses meets the requirement of the credit threshold, the receiving route is used for sequentially reading the data segments to be received from the receiving buffer queue according to the storage sequence and sending corresponding credit pulses to the flow controller.

In some embodiments, the flow control circuit comprises a transmission flow control circuit connected with the transmission route, the transmission flow control circuit comprises a packaging module and a transmission buffer queue which are sequentially connected, the packaging module is connected with the transmission route, and the transmission buffer queue is connected with the inter-chip channel module;

the packaging module is used for packaging the data segment to be transmitted into an intra-chip interface format data segment;

the sending buffer queue is used for buffering the intra-chip interface format data segment;

and the inter-chip channel module is used for sending a read request to the sending cache queue, sequentially reading the intra-chip interface format data segments according to a storage sequence, and sending corresponding credit pulses to the sending route.

In some embodiments, the transmission flow control circuit is configured to obtain an accumulated number of data segments buffered in the transmission buffer queue from a preset time, and an accumulated number of credit pulses received by the transmission route from the preset time;

and the sending route is used for sending the data segment to be sent to the packaging module under the condition that the difference value between the accumulated number of the data segments and the accumulated number of the credit pulses meets the requirement of the credit threshold value.

In some embodiments, the inter-chip channel module is connected to at least two flow control circuits through a multiplexer, and the inter-chip data transmission system further comprises a priority arbitration module;

the priority arbitration module is used for determining the transmission priority of the data segment to be transmitted under the condition that the data segment to be transmitted exists in the at least two flow control circuits;

and the multiplexer is used for transmitting the data segment to be transmitted with high priority to the inter-chip channel module according to the transmission priority.

In some of these embodiments, the flow control circuit is implemented by a field programmable gate array or a dedicated chip.

In a second aspect, in this embodiment, there is provided an inter-chip data transmission method, where the method is applied to the inter-chip data transmission system in the first aspect, and the method includes:

the flow control circuit obtains the accumulated number of data segments to be received, which are cached from a preset time, and the accumulated number of credit pulses sent by the receiving route from the preset time;

and the flow control circuit sends the data segment to be received to the receiving route under the condition that the difference value between the accumulated number of the data segment to be received and the accumulated number of the credit pulse meets the requirement of the credit threshold.

In some embodiments, the inter-chip channel module is connected to at least two flow control circuits through a multiplexer, the inter-chip data transmission system further comprises a priority arbitration module, and the method further comprises:

the priority arbitration module performs priority arbitration based on the data type of the data segment to be sent under the condition that the data segment to be sent exists in the at least two flow control circuits;

the priority arbitration module performs priority arbitration on the data segment to be sent based on the serial number of the flow control circuit corresponding to the data segment to be sent under the condition that the data types of the data segment to be sent meet the high priority condition;

based on the result of the priority arbitration, the multiplexer sends the corresponding data segment to be sent to the inter-chip channel module.

Compared with the related art, the inter-chip data transmission system provided in the embodiment comprises a routing module, a flow control circuit and an inter-chip channel module, the data segments to be transmitted are obtained through the transmission route in the routing module, the data segments to be transmitted are forwarded to the outside of the chip through the inter-chip channel module, the data segments outside the chip are received and forwarded to the corresponding receiving route, the data segments to be transmitted and the data segments to be received are cached through the flow control circuit, the number of the data segments received by the receiving route is controlled according to the credit threshold, namely, the receiving route is informed to sequentially receive the cached data segments and timely release the corresponding credit value only under the condition that the difference between the cached number of the data segments to be received and the received number of the data segments meets the credit threshold range, the number of the remaining cacheable data segments in the cache space is timely known by an upstream sender, the upstream sender can not continuously transmit data any more under the condition that the cache space is full, and the problem that the flow control mechanism in the related art is inaccurate in controlling the data transmission and the lost data packets is solved.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the other features, objects, and advantages of the application.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:

FIG. 1 is a schematic diagram of an inter-chip data transmission system according to some embodiments of the present application;

FIG. 2 is a schematic diagram of connections of an inter-chip channel module, a receive flow control circuit, and a receive route according to some embodiments of the application;

FIG. 3 is a schematic diagram of signal interactions of a receive flow control circuit with a receive route according to some embodiments of the application;

FIG. 4 is a schematic diagram of connections of an inter-chip channel module, a transmit flow control circuit, and a transmit route according to some embodiments of the application;

FIG. 5 is a schematic diagram of signal interactions of a transmit flow control circuit with a transmit route according to some embodiments of the application;

FIG. 6 is a schematic diagram of an inter-chip data transfer system including a priority arbitration module according to some embodiments of the present application;

fig. 7 is a connection diagram of an inter-chip data transmission system according to some preferred embodiments of the present application;

FIG. 8 is a flow chart of a method of inter-chip data transmission in accordance with some embodiments of the application;

fig. 9 is a flow chart of an inter-chip data transfer method based on priority arbitration in accordance with some embodiments of the application.

Detailed Description

The present application will be described and illustrated with reference to the accompanying drawings and examples for a clearer understanding of the objects, technical solutions and advantages of the present application. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

Unless defined otherwise, technical or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms "a," "an," "the," "these" and similar terms in this application are not intended to be limiting in number, but may be singular or plural. The terms "comprising," "including," "having," and any variations thereof, as used herein, are intended to encompass non-exclusive inclusion; for example, a process, method, and system, article, or apparatus that comprises a list of steps or modules (units) is not limited to the list of steps or modules (units), but may include other steps or modules (units) not listed or inherent to such process, method, article, or apparatus. The terms "connected," "coupled," and the like in this disclosure are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The term "plurality" as used herein means two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., "a and/or B" may mean: a exists alone, A and B exist together, and B exists alone. Typically, the character "/" indicates that the associated object is an "or" relationship. The terms "first," "second," "third," and the like, as referred to in this disclosure, merely distinguish similar objects and do not represent a particular ordering for objects.

Fig. 1 is a schematic diagram of an inter-chip data transmission system according to some embodiments of the application. The inter-chip data transmission system is located inside the die 10 and comprises a routing module 12, a flow control circuit 14 and an inter-chip channel module 16, wherein the routing module 12 comprises a sending route 121 and a receiving route 122, the flow control circuit 14 is respectively connected with the sending route 121 and the receiving route 122, and the inter-chip channel module 16 is connected with the flow control circuit 14. The inter-chip channel module 16 is configured to receive the data segment sent by the sending route 121 and forward the data segment to the outside of the chip of the die 10, and receive the data segment to the receiving route 122; the flow control circuit 14 is configured to buffer the data segments and control the number of data segments received by the receive route 122 based on the credit threshold.

It will be appreciated by those of ordinary skill in the art that the configuration shown in fig. 1 is merely illustrative and is not intended to limit the configuration of the inter-chip data transmission system described above. For example, the inter-chip data transfer system may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1. For example, a multi-core processor may include multiple dies 10, with data being transferred between the multiple dies 10 via the inter-chip data system of the present embodiment. Each flow control circuit 14 may correspond to a transmit route 121 and a receive route 122, each inter-chip channel module 16 may correspond to one or more flow control circuits 14, and one or more inter-chip channel modules 16 may be included in each die 10.

Wherein the Die is one Die in a multi-core processor employing Chiplet technology, also known as Die. The inter-chip channel module is an interface channel for data transmission between the dies, and can be a serial or parallel interface for data transmission between different dies, including corresponding transmission protocols, data formats, and the like. The sending route is used for transmitting the data to be sent to the inter-chip channel module according to a predetermined transmission path and then forwarding the data to other tube cores; the receiving route is used for receiving data to be received by the inter-chip channel module from other dies.

Because the inter-chip channel modules of different dies transmit data through inter-chip data channels, and the routing modules in the same die transmit data to the inter-chip channel modules through the flow control circuit, the transmission rates of the two may be different, so the flow control circuit can store the data segments to be received and transmitted by setting a buffer, and the buffer can be an asynchronous FIFO, so as to ensure the correct transmission of the data segments under the condition of different data transmission rates. In addition, the flow control circuit may further control the number of data segments received by the receive route according to a preset credit threshold, which may be equal to the depth of the asynchronous FIFO. When the difference between the number of data segments to be received and the number of received data segments buffered in the asynchronous FIFO is less than the credit threshold, it indicates that the asynchronous FIFO has remaining buffer space, and the upstream route may continue to send data. The flow control circuit of this embodiment may be implemented in a hardware programming language such as Verilog, etc.

According to the inter-chip data transmission system provided by the embodiment, the data segments to be transmitted are obtained through the transmission route in the routing module, the data segments to be transmitted are forwarded to the outside of the chip through the inter-chip channel module, the data segments outside the chip are received and forwarded to the corresponding receiving route, the data segments to be transmitted and the data segments to be received are cached through the flow control circuit, the number of the data segments received by the receiving route is controlled according to the credit threshold, namely, the receiving route is informed to sequentially receive the cached data segments and timely release the corresponding credit value only under the condition that the difference value between the cached number of the data segments to be received and the number of the received data segments meets the credit threshold range, the situation that the number of the residual cacheable data segments in the cache space is known by an upstream sender in time is guaranteed, the upstream sender can not continuously transmit data any more is solved, and the problem that a flow control mechanism in the related art is inaccurate in controlling data transmission, and data packets are lost is solved.

In some embodiments, the flow control circuit includes a receive flow control circuit coupled to the receive route. Fig. 2 is a schematic diagram illustrating connection of an inter-chip channel module, a receiving flow control circuit, and a receiving route according to some embodiments of the present application. The receive flow control circuit 142 includes an analysis module 1421, a receive buffer queue 1422, and a flow controller 1423, which are sequentially connected, the analysis module 1421 is connected to the inter-chip channel module 16, and the receive buffer queue 1422 and the flow controller 1423 are connected to the receive route 122. The parsing module 1421 is configured to parse the intra-chip interface format data segment sent by the inter-chip channel module 16 into a data segment to be received; the receive buffer queue 1422 is used to buffer the data segment to be received; the flow controller 1423 is configured to control the number of data segments to be received read from the receive buffer queue 1422 according to the credit threshold.

According to the structure of the multi-core processor, the inter-chip channel modules of different dies are transmitted through inter-chip data channels, and the routing module in the same die performs data transmission through the flow control circuit to the inter-chip channel modules, so that the transmission rates and the data formats of the inter-chip channel modules may be different. The asynchronous FIFO of the above embodiment is used to solve the difference problem of the transmission rate, and the parsing module in this embodiment may be used to solve the difference problem of the data format, and parse the intra-chip interface format data segment obtained by the inter-chip channel module into the data segment to be received. The intra-chip interface format refers to a transmission format used when data is transmitted in the same die, specifically, the intra-chip interface format data segment may be 160bit fixed format data, which is as follows:

157 th bit: a subnet flag bit identifying the source route (send/receive) of the data segment;

156 th bit: a valid flag bit identifying whether the data segment is valid (carrying data);

155 th to 28 th bit: data, original data;

25 th to 24 th bit: the QID flag bit is used for identifying a flow control circuit sequence number corresponding to the source of the data segment under the condition that the inter-chip channel module of the sender of the data segment corresponds to a plurality of flow control circuits;

23 th to 16 th bit: the yummy flag bit identifies credit signals for the receive routes and the transmit routes corresponding to the plurality of flow control circuits.

The analyzed data segment to be received only keeps the original data of 155 th to 28 th bits.

After the parsing module parses the intra-chip interface format data segment into the data segment to be received, the data segment to be received is stored in a receiving buffer queue, where the receiving buffer queue may be an asynchronous FIFO. The flow controller controls the number of data segments read from the receive buffer queue according to a credit threshold equal to the depth of the asynchronous FIFO. The flow controller can count the number of data segments to be received which are accumulated and buffered in the receiving buffer queue from the end time of resetting, and accumulate the number of the received data segments, and when the difference value of the number of the data segments to be received and the number of the data segments to be received is smaller than the credit threshold value, one data segment to be received can be read from the receiving buffer queue according to the storage sequence, so that one data reception is completed.

According to the inter-chip data transmission system provided by the embodiment, the intra-chip interface format data segment is analyzed into the data segment to be received through the analysis module, so that the problem of format difference between the original data and the intra-chip interface format data segment is solved, the receiving route can directly acquire the analyzed original data, the data processing efficiency of the data transmission and receiving route is improved, and the storage space of the receiving cache queue is reduced; meanwhile, the data source information and the validity information of the data segment to be received are acquired through an analysis process, and a reference basis is provided for subsequent caching and receiving of the data segment to be received; the data segment to be received is cached through a receiving cache queue, and correct receiving of the data is ensured under the condition that the inter-chip data transmission rate is different from the intra-chip data transmission rate; the flow controller controls the number of received data segments according to the credit threshold, so that the availability of a buffer space is ensured, the buffer and the receiving of the data segments in the data transmission process are precisely controlled, and the reliability of the data transmission is ensured.

Further, the analysis module is further used for determining whether the data segment to be received is valid or not based on the analysis result; and writing the data segment to be received into the receiving buffer queue under the condition that the data segment to be received is valid and the receiving buffer queue is not full.

The analysis module determines whether the data segment carries valid data according to 156bit of the intra-chip interface format data segment; and determining a flow control circuit sequence number corresponding to the source of the data segment according to the 25 th bit to the 24 th bit, determining a credit value of a transmission route corresponding to the flow control circuit according to the 23 rd bit to the 16 th bit, and determining the credit validity of the data segment when the credit value is 1. When it is determined that the data segment carries valid data and has credit validity, the data segment to be received may be determined to be valid. When the write enable signal received by the receive buffer queue is valid, it may be determined that the receive buffer queue is not full, and at this time, the data segment to be received may be written into the receive buffer queue.

According to the inter-chip data transmission system provided by the embodiment, the validity of the data segment to be received is obtained through the analysis module, and the validity of the data segment to be received is used as a precondition for writing into the receiving buffer queue, so that the correctness of each data segment in the receiving buffer queue is ensured; and generating a corresponding effective signal according to the effectiveness, and providing a data basis for determining whether the receiving route meets the data receiving condition or not and whether the credit threshold is met or not according to the accumulated number of the effective signal statistical data segments.

In some embodiments, the flow controller is configured to obtain a cumulative number of data segments buffered in the receive buffer queue from a preset time, and a cumulative number of credit pulses sent by the receive route from the preset time; and under the condition that the difference value between the accumulated number of the data segments and the accumulated number of the credit pulses meets the requirement of the credit threshold, the receiving route is used for sequentially reading the data segments to be received from the receiving buffer queue according to the storage sequence and sending the corresponding credit pulses to the flow controller.

Fig. 3 is a schematic diagram illustrating signal interaction between a receiving flow control circuit and a receiving route according to some embodiments of the present application, as shown in fig. 3, an intra-chip interface format Data segment data_in_f is parsed into a Data segment to be received by a parsing module 1421; in the parsing process, the parsing module 1421 obtains whether the valid flag bit and the yummy flag bit in the intra-chip interface format data segment are valid, and buffers the data segment to be received into the receive buffer queue 1422 when both are valid and the write enable signal wen is valid.

The flow controller 1423 may count the cumulative count value of the vailidin signal and the cumulative count value of the yummyOut signal since the end of the reset. When the receiving buffer queue 1422 buffers a data segment to be received, a vaildin signal is sent to the receiving route 122, so that the accumulated number of the data segments buffered by the receiving buffer queue 1422 is equal to the accumulated count value of the vaildin signal; when the receive route 122 reads a segment of data to be received from the receive buffer queue 1422, a yummy out signal is sent to the flow controller 1423, so that the cumulative number of credit pulses sent by the receive route 122 is equal to the cumulative count value of the yummy out signal.

The flow controller 1423 calculates the difference between the cumulative count value of the vailidin signal and the cumulative count value of the yummycout signal, and when the difference is greater than 0 and less than the credit threshold (the credit threshold is equal to the depth of the receive buffer queue), it indicates that the data transmission is within the range specified by the credit protocol, and at this time, a read FIFO data signal is generated to the receive buffer queue 1422, the receive route 122 reads a data segment dataIn to be received from the receive buffer queue 1422, and sends a credit pulse yummycout corresponding to the data segment to the flow controller 1423, so as to complete a credit data reception. The data segment to be received dataIn is the first data segment to be received of the receive buffer queue 1422. And when the count difference value of the two signals is not in the credit threshold range, returning to error, and continuing when the data transmission waits for the flow control credit to meet the credit threshold condition, and repeating the operation.

According to the inter-chip data transmission system provided by the embodiment, the accumulated number of the data segments cached in the receiving cache queue and the accumulated number of the credit pulses sent by the receiving route are obtained through the flow controller, the data segments stored in the receiving cache queue are determined according to the difference value of the accumulated number of the data segments and the accumulated number of the credit pulses, the receiving route can be determined to be not empty and not full under the condition that the data segments are larger than 0 and smaller than the credit threshold, the receiving route can read the data segments to be received in sequence normally according to the caching order, and the sender can send data to the receiving route normally, namely, the caching and the transmission of the data are controlled through the vailin signal and the yummyOut signal in the flow control circuit, so that the reliability of data transmission is ensured.

In some embodiments, the flow control circuit includes a transmission flow control circuit connected to the transmission route, and please refer to fig. 4, which is a schematic diagram illustrating connection between the inter-chip channel module, the transmission flow control circuit, and the transmission route according to some embodiments of the present application. The transmission flow control circuit 141 comprises an encapsulation module 1412 and a transmission buffer queue 1411 which are connected in sequence, the encapsulation module 1412 is connected with the transmission route 121, and the transmission buffer queue 1411 is connected with the inter-chip channel module 16; the encapsulation module 1412 is configured to encapsulate the data segment to be sent into an intra-chip interface format data segment; the sending buffer queue 1411 is used for buffering intra-chip interface format data segments; the inter-chip channel module 16 is configured to send a read request to the send buffer queue 1411, sequentially read the intra-chip interface format data segments according to the storage order, and send a corresponding credit pulse to the send route 121.

The encapsulation module has opposite functions to the analysis module, and can encapsulate the original data to be sent according to the format of the on-chip interface format data segment. And under the condition that the data segment to be transmitted is determined to be valid, the valid flag bit and the corresponding yummy flag position are valid. And under the condition that the sending cache queue is not full, writing the encapsulated intra-chip interface format data segment into the sending cache queue. And the inter-chip channel module initiates a data reading request to the sending buffer queue according to the data transmission rate of the inter-chip channel module, reads the first intra-chip interface format data segment in the sending buffer queue, and sends a corresponding credit pulse to the sending route so as to inform the sending route that one data segment is received.

According to the inter-chip data transmission system provided by the embodiment, the data segment to be transmitted is encapsulated into the intra-chip interface format data segment through the encapsulation module, so that the problem of format difference between original data and the intra-chip interface format data segment is solved, and the inter-chip channel module can acquire source information and validity information of the data segment as reference basis for subsequent transmission to outside the chip while acquiring the original data; the data segment in the intra-chip interface format is cached by the sending cache queue, and the correct sending of the data is ensured under the condition that the inter-chip data transmission speed is different from the intra-chip data transmission speed; and sequentially reading the sending buffer queues through the inter-chip channel module, sending corresponding credit pulses to the sending route, providing accurate data receiving information for the sending route, and providing a data basis for counting the accumulated number of the credit pulses of the sending route.

In some embodiments, the transmission flow control circuit is configured to obtain an accumulated number of data segments buffered in the transmission buffer queue from a preset time, and an accumulated number of credit pulses received by the transmission route from the preset time; and under the condition that the difference value between the data segment accumulation number and the credit pulse accumulation number meets the requirement of the credit threshold, the sending route is used for sending the data segment to be sent to the packaging module.

Fig. 5 is a signal interaction diagram of a sending flow control circuit and a sending route according to some embodiments of the present application, and as shown in fig. 5, from the end of the reset, the sending flow control circuit 141 obtains an accumulated count value of the vaildOut signal and an accumulated count value of the yummyIn signal. When the encapsulation module 1412 determines that a data segment to be sent is valid, a vaildOut signal is sent to the sending buffer queue 1411, and the encapsulated data segment to be sent is written into the sending buffer queue 1411, so that the accumulated number of data segments buffered in the sending buffer queue 1411 is equal to the accumulated count value of the vaildOut signal; when the inter-chip channel module reads a data segment from transmit buffer queue 1411, a yummyIn signal is sent to transmit route 121 so that the cumulative number of credit pulses received by transmit route 121 is equal to the cumulative count value of the yummyIn signal.

The transmission flow control circuit 141 calculates the difference between the cumulative count value of the vaildOut signal and the cumulative count value of the yummyIn signal, and when the value is greater than 0 and less than the credit threshold, it indicates that the data transmission is within the range specified by the credit protocol, at this time, the write enable signal wen is sent to the transmission buffer queue 1411, and when the vaildOut signal is valid, the encapsulated on-chip format data segment wdata is written into the transmission buffer queue 1411; when the inter-chip channel module initiates the read request signal ren and the transmit buffer queue 1411 is not empty, the first intra-chip interface format data segment in the transmit buffer queue 1411 is transmitted to the inter-chip channel module, and the inter-chip channel module sends a corresponding yummyIn pulse signal to the transmit route 121 to inform the transmit route that a data segment has been received. When the vaildOut and yummyIn pulse signal count values do not meet the credit threshold specified by the flow control credit protocol, the transmit route 121 stops transmitting data to the encapsulation module 1412 and returns error until the credit threshold is met, and continues transmitting data.

According to the inter-chip data transmission system, the transmission flow control circuit is used for acquiring the accumulated number of data segments cached in the transmission cache queue and the accumulated number of credit pulses received by the transmission route, the data segments stored in the transmission cache queue are determined according to the difference between the accumulated number of data segments and the accumulated number of credit pulses, the transmission route can be used for determining that the transmission cache queue is not empty and not full under the condition that the data segments are larger than 0 and smaller than a credit threshold, the transmission route can normally write the data segments into the transmission cache queue, and a receiver can also sequentially read the data segments in the cache queue according to the caching order, namely, the caching and the transmission of data are controlled through a vaildOut signal and a yummyIn signal in the flow control circuit, and the reliability of data transmission is ensured.

In some embodiments, referring to fig. 6, a schematic diagram of an inter-chip data transmission system including a priority arbitration module according to some embodiments of the present application is shown. The inter-chip channel module 16 is connected to at least two flow control circuits 14 via a multiplexer 183, and the inter-chip data transfer system further comprises a priority arbitration module 181. The priority arbitration module 181 is configured to determine a transmission priority of the data segment to be transmitted in a case where there are at least two flow control circuits 14; the multiplexer 183 is configured to send the data segment to be sent with high priority to the inter-chip channel module 16 according to the sending priority.

In the present embodiment, one flow control circuit 14 corresponds to one transmission route 121 and one reception route 122, and one inter-chip channel module 16 corresponds to four flow control circuits 14. In the case where there are at least two transmission buffer queues in the four flow control circuits 14 simultaneously in-chip interface format data segments to be transmitted, the priority arbitration module 181 determines the transmission priority according to the data type of the in-chip interface format data segments to be transmitted, which generally includes a response type and a request type, and the data type can be acquired through a flag bit preset in the in-chip interface format data segments. For example, the transmission priority of the data segment of the acknowledgement type may be set high. Further, if there are multiple transmit buffer queues in the same flow control circuit 14, and the data segment to be transmitted has both a request type data segment and a response type data segment, priority arbitration is performed in the flow control circuit 14, for example, the transmission priority of the request type data segment may be set to be high. The data segment is then priority arbitrated with the data segment to be sent in the other flow control circuit 14.

If the multiple intra-chip interface format data segments to be transmitted are all of the response type, the transmission priority may also be determined according to the sequence number of the flow control circuit 14 in which the data segment is located. For example, if the serial numbers of the four flow control circuits 14 are Quacfg- > Qua1- > Qua2- > Qua3, respectively, the transmission priority may be set in this order. The multiplexer 183 transmits the intra-chip interface format Data segment data_in_f having a high priority to the inter-chip channel module 16 according to the transmission priority.

In the inter-chip data transmission system of the embodiment, the priority arbitration module determines the transmission priority of a plurality of data segments to be transmitted, and the multiplexer transmits the data segment with the highest transmission priority in the intra-chip interface format to the inter-chip channel module, so that a plurality of flow control circuits are allowed to occupy time slots instead of time division multiplexing.

In some embodiments, the flow control circuit is implemented by a field programmable gate array or a dedicated chip. For example, the structure and the functional module of the flow control circuit can be realized by using Verilog hardware description language, after simulation verification, a hardware circuit corresponding to the structure and the functional module of the flow control circuit is realized by using a special chip or a field programmable gate array FPGA, so as to realize the data transmission flow control of the inter-chip data transmission system in the above embodiment, improve the design efficiency of the flow control circuit, and shorten the design period.

The present embodiment is described and illustrated below by way of preferred embodiments. Fig. 7 is a connection diagram of the inter-chip data transmission system of the preferred embodiment. As shown in fig. 7, the inter-chip data transmission system includes an inter-chip channel module 16, a priority arbitration module 181, a multiplexer 183, a demultiplexer 185, and a plurality of flow control circuits 14 and corresponding transmission routes 121, 122. Each flow control circuit 14 includes a transmit flow control circuit 141 and a receive flow control circuit 142, which are respectively connected to the transmit route 121 and the receive route 122. The multiplexer 183 is connected to each of the transmission flow rate control circuits 141, and the demultiplexer 185 is connected to each of the reception flow rate control circuits 142. The number of flow control circuits 14 may be set according to the internal structure of the die.

When each transmission route has a data segment to be transmitted, transmitting the data segment to be transmitted to a corresponding encapsulation module, and converting the data segment to be transmitted into an intra-chip interface format data segment; the transmission flow control circuit corresponding to the transmission route obtains the accumulated count value of the vaildOut signal and the accumulated count value of the yummyIn signal from the reset ending time, calculates the difference value between the accumulated count value of the vaildOut signal and the accumulated count value of the yummyIn signal, when the value is larger than 0 and smaller than the credit threshold, the data transmission is indicated to be in the credit protocol stipulated range, at the moment, a write-in enabling signal is transmitted to the transmission buffer queue, and when the vaildOut signal is valid, the encapsulated in-chip interface format data segment wdata is written into the transmission buffer queue.

After the inter-chip channel module initiates a read request, if there are intra-chip interface format data segments to be transmitted in the multiple transmission buffer queues, the priority arbitration module determines the intra-chip interface format data segment with the highest transmission priority according to preset arbitration rules, the multiplexer transmits the intra-chip interface format data segment to the inter-chip channel module, and the inter-chip channel module transmits a corresponding yummyIn pulse signal to a transmission route corresponding to the data segment so as to inform the transmission route that one data segment is received. When the vaildOut and yummyIn pulse signal count values do not meet the credit threshold specified by the flow control credit protocol, the sending route stops sending data to the encapsulation module and returns error until the credit threshold is met, and the sending of the data is continued.

When the inter-chip channel module has an intra-chip interface format data segment to be transmitted to a corresponding receiving route, the intra-chip interface format data segment is transmitted to a demultiplexer, the corresponding receiving route is determined by the demultiplexer according to the content of address bits in the intra-chip interface format data segment, and the intra-chip interface format data segment is transmitted to a corresponding analyzing module. And analyzing the intra-chip interface format data segment into a data segment to be received through an analysis module, and in the analysis process, acquiring whether a valid flag bit and a yummy flag bit in the intra-chip interface format data segment are valid or not by the analysis module, and caching the data segment to be received into a receiving cache queue when both the valid flag bit and the yummy flag bit are valid and the write enable signal is valid.

The flow controller calculates the difference between the accumulated count value of the vaildIn signal and the accumulated count value of the yummyOut signal from the reset end time, when the value is larger than 0 and smaller than the credit threshold, the data transmission is indicated to be in the credit protocol stipulated range, a read FIFO data signal is generated to a receiving buffer queue at the moment, the receiving route reads a data segment dataIn to be received from the receiving buffer queue, and credit pulse yummyOut corresponding to the data segment is sent to the flow controller, so that one credit data reception is completed. And when the count difference value of the two signals is not in the credit threshold range, returning to error, and continuing when the data transmission waits for the flow control credit to meet the credit threshold condition, and repeating the operation.

In the inter-chip data transmission system of the embodiment, the priority arbitration module determines the transmission priority of a plurality of data segments to be transmitted under the condition of data transmission, and the multiplexer transmits the corresponding inter-chip interface format data segments to the inter-chip channel module, so that the data transmission rate is improved, and the network bandwidth is saved; the transmission flow control circuit determines the number of data segments stored in the transmission buffer queue, precisely controls the buffer and transmission of data, and ensures the reliability of data transmission; under the condition of data reception, the data to be received is distributed to the corresponding flow control circuit through the demultiplexer, the number of data segments stored in the receiving buffer queue is determined through the flow controller, the buffering and the transmission of the data are accurately controlled, and the reliability of data transmission is ensured.

In some embodiments, the present application further provides an inter-chip data transmission method, which may be applied to the inter-chip data transmission system in the foregoing embodiments. Fig. 8 is a flow chart of an inter-chip data transfer method according to some embodiments of the application. As shown in fig. 8, the flow includes the steps of:

in step S801, the flow control circuit obtains the accumulated number of data segments to be received buffered from the preset time, and the accumulated number of credit pulses sent by the receiving route from the preset time.

In this embodiment, the flow control circuit includes a receive buffer queue, where the receive buffer queue may buffer the data segment sent by the inter-chip channel module for reading by the receive route. The depth of the receive cache queue may be equal to the credit threshold. From the end of the reset, when the receiving buffer queue buffers a data segment to be received, a vailidin signal may be sent to the receiving route, and when the receiving route reads a data segment to be received from the receiving buffer queue, a yummy out signal may be sent to the flow controller. Therefore, the accumulated number of the data segments to be received, which are cached in the receiving cache queue, is equal to the accumulated count value of the vailidin signal; the cumulative number of credit pulses sent by the receiving route is equal to the cumulative count value of the yummycout signal.

In step S802, the flow control circuit sends the data segment to be received to the receiving route if the difference between the accumulated number of data segments to be received and the accumulated number of credit pulses meets the requirement of the credit threshold.

When the difference value between the accumulated count value of the vailidin signal and the accumulated count value of the yummy out signal is greater than 0 and smaller than the credit threshold value, the difference value indicates that the receiving buffer queue is not full and empty, the first data segment to be received in the receiving buffer queue can be sent to the receiving route, and the receiving route sends the credit pulse yummy out corresponding to the data segment to the flow controller, so that one time of credit data receiving is completed. And when the count difference value of the two signals is not in the credit threshold range, returning to error, and continuing when the flow control credit meets the credit threshold condition.

Through the steps S801 to S802, the accumulated number of the data segments to be received buffered from the preset time and the accumulated number of the credit pulses sent by the receiving route from the preset time are obtained through the flow control circuit and used as a data basis for judging the number of the data segments in the receiving buffer queue; under the condition that the difference value between the accumulated number of the data segments to be received and the accumulated number of the credit pulses meets the requirement of the credit threshold, the flow control circuit sends the data segments to be received to the receiving route, so that the availability of the buffer space of the receiving buffer queue is ensured, the buffering and receiving of the data segments in the data transmission process are accurately controlled, and the reliability of the data transmission is ensured.

In some of these embodiments, the inter-chip channel module is coupled to the at least two flow control circuits via a multiplexer, and the inter-chip data transmission system further comprises a priority arbitration module. FIG. 9 is a flow chart of a priority arbitration based inter-chip data transfer method according to some embodiments of the present application, as shown in FIG. 9, the flow includes the steps of:

step S901, in the case that at least two flow control circuits have a data segment to be sent, the priority arbitration module performs priority arbitration based on the data type of the data segment to be sent;

in this embodiment, one flow control circuit corresponds to one transmission route and one reception route, and one inter-chip channel module corresponds to at least two flow control circuits. When there are at least two transmission buffer queues in the flow control circuit and there is an intra-chip interface format data segment to be transmitted, the priority arbitration module may determine the transmission priority according to the data type of the intra-chip interface format data segment, where the data type may include a response type and a request type, and the data type may be acquired through a flag bit preset in the intra-chip interface format data segment. For example, the transmission priority of the data segment of the acknowledgement type may be set high.

Step S902, under the condition that the data types of the data segments to be transmitted meet the high priority condition, a priority arbitration module arbitrates the priority of the data segments to be transmitted based on the serial numbers of the flow control circuits corresponding to the data segments to be transmitted;

further, if the plurality of intra-chip interface format data segments to be transmitted all meet the high priority condition, the transmission priority may also be determined according to the sequence number of the flow control circuit where the data segment is located. For example, if the inter-chip channel module corresponds to four flow control circuits, and the serial numbers are Quacfg- > Qua1- > Qua2- > Qua3, respectively, the transmission priority may be set according to the sequence.

In step S903, based on the result of the priority arbitration, the multiplexer sends the corresponding data segment to be sent to the inter-chip channel module.

The multiplexer sends the intra-chip interface format data segment with the highest priority to the inter-chip channel module according to the result of the priority arbitration, and the inter-chip channel module can send a corresponding credit pulse signal to the corresponding flow control circuit.

Through the steps S901 to S903, a priority determining manner of determining the sending sequence of the plurality of data segments to be sent is provided by performing priority arbitration by the priority arbitration module based on the data type of the data segments to be sent when at least two flow control circuits have the data segments to be sent; the priority arbitration module performs priority arbitration on the data segment to be transmitted based on the serial number of the flow control circuit corresponding to the data segment to be transmitted under the condition that the data types of the data segment to be transmitted meet the high priority condition, and gives another priority determination mode; the multi-path selector sends the corresponding data segment to be sent to the inter-chip channel module based on the result of priority arbitration, so that a plurality of flow control circuits are allowed to preempt time slots instead of time division multiplexing, the multi-path selector has the advantages of high transmission rate and bandwidth saving, and the problems of data transmission bandwidth waste and slow data transmission caused by time division multiplexing are avoided.

It should be noted that the steps illustrated in the above-described flow or flow diagrams of the figures may be performed in a computer system, such as a set of computer-executable instructions, and that, although a logical order is illustrated in the flow diagrams, in some cases, the steps illustrated or described may be performed in an order other than that illustrated herein.

It should be noted that, specific examples in this embodiment may refer to examples described in the foregoing embodiments and alternative implementations, and are not described in detail in this embodiment.

It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to be limiting. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure in accordance with the embodiments provided herein.

It is to be understood that the drawings are merely illustrative of some embodiments of the present application and that it is possible for those skilled in the art to adapt the present application to other similar situations without the need for inventive work. In addition, it should be appreciated that while the development effort might be complex and lengthy, it will nevertheless be a routine undertaking of design, fabrication, or manufacture for those of ordinary skill having the benefit of this disclosure, and further having the benefit of this disclosure.

The term "embodiment" in this disclosure means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive. It will be clear or implicitly understood by those of ordinary skill in the art that the embodiments described in the present application can be combined with other embodiments without conflict.

The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the patent claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.

Claims (10)

1. The inter-chip data transmission system is characterized by comprising a routing module, a flow control circuit and an inter-chip channel module, wherein the routing module comprises a sending route and a receiving route, the flow control circuit is respectively connected with the sending route and the receiving route, and the inter-chip channel module is connected with the flow control circuit;

The inter-chip channel module is used for receiving the data segment sent by the sending route and forwarding the data segment to the outside of the chip, and receiving the data segment outside the chip and forwarding the data segment to the receiving route;

the flow control circuit is used for caching the data segments and controlling the number of the data segments received by the receiving route according to the credit threshold.

2. The inter-chip data transmission system according to claim 1, wherein the flow control circuit comprises a receiving flow control circuit connected with the receiving route, the receiving flow control circuit comprises an analysis module, a receiving buffer queue and a flow controller which are sequentially connected, the analysis module is connected with the inter-chip channel module, and the receiving buffer queue and the flow controller are connected with the receiving route;

the analysis module is used for analyzing the intra-chip interface format data segment sent by the inter-chip channel module into a data segment to be received;

the receiving buffer queue is used for buffering the data segment to be received;

the flow controller is used for controlling the number of the data segments to be received read from the receiving cache queue according to the credit threshold.

3. The system for transmitting data between chips as defined in claim 2, wherein,

The analysis module is further used for determining whether the data segment to be received is valid or not based on an analysis result; and writing the data segment to be received into the receiving cache queue under the condition that the data segment to be received is valid and the receiving cache queue is not full.

4. The system for transmitting data between chips as defined in claim 2, wherein,

the flow controller is used for obtaining the accumulated number of data segments cached by the receiving cache queue from a preset time and the accumulated number of credit pulses sent by the receiving route from the preset time;

and under the condition that the difference value between the accumulated number of the data segments and the accumulated number of the credit pulses meets the requirement of the credit threshold, the receiving route is used for sequentially reading the data segments to be received from the receiving buffer queue according to the storage sequence and sending corresponding credit pulses to the flow controller.

5. The inter-chip data transmission system according to claim 1, wherein the flow control circuit comprises a transmission flow control circuit connected with the transmission route, the transmission flow control circuit comprises an encapsulation module and a transmission buffer queue which are sequentially connected, the encapsulation module is connected with the transmission route, and the transmission buffer queue is connected with the inter-chip channel module;

The packaging module is used for packaging the data segment to be transmitted into an intra-chip interface format data segment;

the sending buffer queue is used for buffering the intra-chip interface format data segment;

and the inter-chip channel module is used for sending a read request to the sending cache queue, sequentially reading the intra-chip interface format data segments according to a storage sequence, and sending corresponding credit pulses to the sending route.

6. The system for transmitting data between chips as defined in claim 5, wherein,

the sending flow control circuit is used for obtaining the accumulated number of data segments cached by the sending cache queue from a preset time and the accumulated number of credit pulses received by the sending route from the preset time;

and the sending route is used for sending the data segment to be sent to the packaging module under the condition that the difference value between the accumulated number of the data segments and the accumulated number of the credit pulses meets the requirement of the credit threshold value.

7. The inter-chip data transmission system of claim 1, wherein the inter-chip channel module is connected to at least two flow control circuits through a multiplexer, the inter-chip data transmission system further comprising a priority arbitration module;

The priority arbitration module is used for determining the transmission priority of the data segment to be transmitted under the condition that the data segment to be transmitted exists in the at least two flow control circuits;

and the multiplexer is used for transmitting the data segment to be transmitted with high priority to the inter-chip channel module according to the transmission priority.

8. The inter-chip data transmission system of claim 1, wherein the flow control circuit is implemented by a field programmable gate array or a dedicated chip.

9. An inter-chip data transmission method, wherein the method is applied to the inter-chip data transmission system as claimed in any one of claims 1 to 8, the method comprising:

the flow control circuit obtains the accumulated number of data segments to be received, which are cached from a preset time, and the accumulated number of credit pulses sent by the receiving route from the preset time;

and the flow control circuit sends the data segment to be received to the receiving route under the condition that the difference value between the accumulated number of the data segment to be received and the accumulated number of the credit pulse meets the requirement of the credit threshold.

10. The method of inter-chip data transmission according to claim 9, wherein the inter-chip channel module is connected to at least two flow control circuits through a multiplexer, the inter-chip data transmission system further comprising a priority arbitration module, the method further comprising:

The priority arbitration module performs priority arbitration based on the data type of the data segment to be sent under the condition that the data segment to be sent exists in the at least two flow control circuits;

the priority arbitration module performs priority arbitration on the data segment to be sent based on the serial number of the flow control circuit corresponding to the data segment to be sent under the condition that the data types of the data segment to be sent meet the high priority condition;

based on the result of the priority arbitration, the multiplexer sends the corresponding data segment to be sent to the inter-chip channel module.