CN113806247A - Device and method for flexibly using data cache in 5G communication chip - Google Patents
Device and method for flexibly using data cache in 5G communication chip Download PDFInfo
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Abstract
The invention relates to a device for flexibly using data cache in a 5G communication chip, which comprises: the device comprises a cache allocation control unit, a shared cache unit, a plurality of 5GNR protocol acceleration modules and a bus; the shared cache unit comprises a plurality of cache units; the cache allocation control unit allocates the cache units in the shared cache unit to the 5GNR protocol acceleration modules for use. The special cache units in the 5GNR protocol acceleration modules in the traditional scheme are extracted to form a shared cache module which can be flexibly configured, so that the cache utilization rate and the utilization flexibility of the 5G communication acceleration modules are improved, meanwhile, the data interaction efficiency among the acceleration modules can be improved, the data interaction time delay is reduced, the data cache units can be flexibly distributed in a plurality of acceleration modules as required, and the data cache units do not need to be fixed in a certain acceleration module.
Description
Technical Field
The invention relates to the technical field of 5G communication, in particular to a device and a method for flexibly using data cache in a 5G communication chip.
Background
In a 5G NR (New Radio) wireless communication baseband processing SOC chip, many hard acceleration modules are used to process NR protocols, such as data processing and protocol parsing tasks of LDPC codec. These data processing and protocol parsing processes generally include a large number of memory cells as data buffers in order to increase the processing speed and efficiency within the chip. Currently, a common data cache unit is a module internal cache serving a certain acceleration module. The method has the advantages that the protocol or the calculation acceleration module using the cache is in exclusive possession of the cache and has no competition. But at the worst, when the computing module is not used, the cache modules inside the modules cannot be shared to other required modules for use, which causes resource idle, because the area occupied by the SRAM (static random access memory) unit commonly used by the cache modules and the power consumption still account for a large proportion in the 5G communication chip.
Therefore, there is a need in the art for a technical solution for flexibly allocating and using data cache units used inside an acceleration module of a 5G NR protocol.
Disclosure of Invention
The invention aims to provide a device and a method for flexibly using data cache in a 5G communication chip, which are used for solving the problem of resource waste caused by idle cache modules in the existing modules.
In order to achieve the purpose, the invention provides the following scheme:
an apparatus for flexible use of data caching in a 5G communication chip, the apparatus comprising:
the system comprises a cache allocation control unit, a shared cache unit, a plurality of 5G NR protocol acceleration modules and a bus;
one end of the cache allocation control unit is connected with one end of the shared cache unit, and the other end of the cache allocation control unit is connected with the bus;
the other end of the shared cache unit is connected with one end of the plurality of 5G NR protocol acceleration modules;
the other ends of the plurality of 5G NR protocol acceleration modules are connected with the bus;
the shared cache unit comprises a plurality of cache units;
the cache allocation control unit allocates the cache units in the shared cache unit to the 5G NR protocol acceleration modules for use.
Alternatively to this, the first and second parts may,
the shared cache unit further comprises: a data selector unit;
the data selector unit is respectively connected with the plurality of cache units, the cache allocation control unit and the plurality of 5GNR protocol acceleration modules.
Alternatively to this, the first and second parts may,
the shared cache unit further comprises: a plurality of data ports;
one end of each of the plurality of data ports is connected with the data selection unit, and the other end of each of the plurality of data ports is connected with the plurality of 5G NR protocol acceleration modules; the data ports are used for carrying out data transmission with the 5G NR protocol acceleration modules; from which cache unit the data originates is selected by the data selector unit.
Alternatively to this, the first and second parts may,
the data ports are compatible with a plurality of data transmission modes.
Alternatively to this, the first and second parts may,
the device further comprises:
and the system shared cache is connected with the bus.
Alternatively to this, the first and second parts may,
the device further comprises:
and the system CPU is connected with the bus.
A method for using a device for flexibly using data cache in a 5G communication chip comprises the following steps:
and allocating the plurality of buffer units to the plurality of 5G NR protocol acceleration modules by using the buffer allocation control unit.
Alternatively to this, the first and second parts may,
the allocating, by the cache allocation control unit, the plurality of cache units to the plurality of 5G NR protocol acceleration modules specifically includes:
and controlling the data selection unit to distribute the buffer units to the 5G NR protocol acceleration modules by using the buffer distribution control unit.
Alternatively to this, the first and second parts may,
the control of the data selection unit by the cache allocation control unit to allocate the cache units to the 5GNR protocol acceleration modules specifically includes:
transmitting the configuration information to a cache allocation control unit through a bus;
transmitting the configuration information to a data selector unit through the cache allocation control unit; and enabling the control selector unit to distribute a plurality of cache units to a plurality of 5G NR protocol acceleration modules according to the configuration information.
Alternatively to this, the first and second parts may,
the configuration information includes: the cache starting address occupied by each 5G NR protocol acceleration module and the cache size occupied by each protocol acceleration module.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the embodiment of the invention extracts the special cache units in each 5G NR protocol acceleration module in the traditional scheme to form a sharing cache module which can be flexibly configured, thereby improving the cache utilization rate and the utilization flexibility of the 5G communication acceleration module, simultaneously improving the data interaction efficiency among the acceleration modules, reducing the data interaction time delay, flexibly distributing the data cache units in a plurality of acceleration modules according to the requirements and not fixing the data cache units in a certain acceleration module. By sharing the cache unit among different acceleration modules, the efficiency of data exchange and transmission among the acceleration modules is improved.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of an apparatus for flexibly using a data cache in a 5G communication chip according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of an internal structure of a shared cache unit of an apparatus for flexibly using data cache in a 5G communication chip according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In a 5G NR (New Radio) wireless communication baseband processing SOC chip, many hard acceleration modules are used to process NR protocols, such as data processing and protocol parsing tasks of LDPC codec. In order to increase the processing speed and efficiency in the chip, these data processing and protocol parsing processes generally include a large number of memory cells as data buffers. Currently, a common data cache unit is a module internal cache serving a certain acceleration module. The method has the advantages that the protocol or the calculation acceleration module using the cache is in exclusive possession of the cache and has no competition. But at the worst, when the computing module is not used, the cache modules inside the modules cannot be shared to other required modules for use, which causes resource idle, because the area occupied by the SRAM (static random access memory) unit commonly used by the cache modules and the power consumption still account for a large proportion in the 5G communication chip.
Specifically, a series of hard acceleration modules are generally adopted inside the existing 5G communication processing chip to perform hard acceleration on various algorithms or processing flows related to the NR protocol. Meanwhile, in order to improve the data caching efficiency, SRAM units with different sizes are placed in each acceleration module according to the requirement to realize the data caching function. The conventional data caching scheme described above has two disadvantages:
(1) the cache module in the acceleration module can only be used by the module, and other modules cannot be shared and shared.
(2) The cache size inside the acceleration module cannot be changed after the design is realized, and the condition that the cache size requirement is changed due to algorithm evolution and requirement change in the practical process of the chip cannot be adapted.
The invention aims to provide a device and a method for flexibly using data cache in a 5G communication chip, which aim to solve the problem of resource waste caused by idle cache modules in the existing modules, and flexibly allocate and use a data cache unit used in an acceleration module for 5G NR protocol processing in the chip, thereby improving the utilization efficiency of cache resources and the processing efficiency of the protocol acceleration module.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
The first embodiment is as follows:
as shown in fig. 1, an embodiment of the present invention provides an apparatus for flexibly using a data cache in a 5G communication chip, where the apparatus includes: the system comprises a cache allocation control unit, a shared cache unit, a plurality of 5G NR protocol acceleration modules and a bus;
one end of the cache allocation control unit is connected with one end of the shared cache unit, and the other end of the cache allocation control unit is connected with the bus;
the other end of the shared cache unit is connected with one end of the plurality of 5G NR protocol acceleration modules;
the other ends of the plurality of 5G NR protocol acceleration modules are connected with the bus;
the shared cache unit comprises a plurality of cache units;
the cache allocation control unit allocates the cache units in the shared cache unit to the 5G NR protocol acceleration modules for use.
Referring to fig. 1, the protocol hard accelerator modules capable of sharing data cache in the embodiment are represented by 5G NR protocol acceleration modules 1 to 3, but the present invention can share cache among more acceleration modules, and is not limited to 3. These 5G NR protocol acceleration modules are typically connected to a bus within the system through a bus interface.
The flexible use of the data cache in the 5G communication chip is realized by the cache allocation control unit in the figure 1. The cache allocation control unit is configured by system CPU software through bus access, and the size of the cache which can be occupied by each accelerator module and the starting address of the occupied range can be configured through the interface. The configuration steps are as follows:
the control software writes the following information into the register set 1 of the buffer allocation control unit according to the need of protocol analysis:
the cache start address occupied by the 5G NR protocol acceleration module 1;
the buffer size occupied by the 5G NR protocol acceleration module 1;
the control software writes the following information into the register set 2 of the cache allocation control unit as required by the protocol analysis:
5, a cache initial address occupied by the GNR protocol acceleration module 2;
5, the buffer size occupied by the GNR protocol acceleration module 2;
and in the same way, performing cache allocation on all 5GNR protocol analysis modules.
As shown in fig. 2, the shared cache unit further includes: a data selector unit;
the data selector unit is respectively connected with the plurality of cache units, the cache allocation control unit and the plurality of 5GNR protocol acceleration modules.
The shared cache unit provided in this embodiment further includes: a plurality of data ports;
one end of each of the plurality of data ports is connected with the data selection unit, and the other end of each of the plurality of data ports is connected with the plurality of 5GNR protocol acceleration modules; the data ports are used for carrying out data transmission with the 5GNR protocol acceleration modules; from which cache unit the data originates is selected by the data selector unit.
Specifically, as can be seen from fig. 2, the shared cache unit provided in the embodiment of the present invention is composed of a plurality of data ports (1 to m), 1 MUX data selector unit, and a plurality of cache units (1 to n). The specific function of each part is as follows:
data ports 1 to m:
these data ports are data ports connected to respective 5GNR protocol acceleration modules. The 5GNR protocol acceleration module in charge of interfacing carries out data transmission, and the specific data transmission mode can be determined according to the data transmission mode required by each 5GNR protocol acceleration module, and is not limited to a certain transmission or signal interface. The data of these data ports are originated from the respective buffer unit modules 1 to n shown in fig. 2, and specifically, from which buffer unit is controlled by the MUX unit.
MUX data selector unit:
this unit completes the direct path multiplexing and connection from the plurality of buffer units 1 to n to the plurality of data ports 1 to m. Multiplexing and connection are controlled by receiving information of the buffer allocation control unit.
A buffer allocation control unit:
the unit provides a bus configuration interface, receives configuration and control information transmitted from the bus port, and transmits the control information to the MUX data selector unit to realize control and switching of data paths. For example, the control software may allocate cache location 2 to data port 1 by writing 0x21 to the data path control register 1 of the cache allocation control unit. The control allocation of the other buffers is similar to this.
Cache units 1 to n:
the cache units are realized by a plurality of SRAM or other types of on-chip memory modules according to design requirements, and are used for storing specific cache data and performing data reading and writing operations according to addresses and related control information sent by ports.
As an alternative implementation, the plurality of data ports are compatible with a plurality of data transmission modes. The device further comprises:
and the system shared cache is connected with the bus.
There is also typically a system common cache module within the SOC system, as shown in the upper right block of fig. 1. The module is completely different from the shared cache unit provided by the invention, the system common cache module shown in fig. 1 is an on-chip cache module which can be accessed by all modules connected to the bus through the bus, and the shared cache module provided by the invention is a cache module which can be directly accessed by only specific accelerator modules through specific data interfaces, and does not need to pass through bus ports, thereby reducing access delay.
The device for flexibly using the data cache in the 5G communication chip provided by the embodiment of the invention further comprises:
and the system CPU is connected with the bus. For overall control and address allocation.
The embodiment of the invention also provides a use method of the device for flexibly using the data cache in the 5G communication chip, which comprises the following steps:
and allocating the plurality of buffer units to the plurality of 5G NR protocol acceleration modules by using the buffer allocation control unit.
Specifically, the method comprises the following steps:
the embodiment of the invention utilizes the cache allocation control unit to control the data selection unit to allocate the cache units to the 5GNR protocol acceleration modules.
The method comprises the following specific steps:
s1, transmitting the configuration information to the buffer allocation control unit through the bus; the configuration information includes: the cache starting address occupied by each 5GNR protocol acceleration module and the cache size occupied by each protocol acceleration module.
S2, transmitting the configuration information to a data selector unit through the buffer allocation control unit; and enabling the control selector unit to distribute the cache units to the 5G NR protocol acceleration modules according to the configuration information.
The scheme provided by the embodiment has the characteristics that the special cache units in each 5G NR protocol acceleration module in the traditional scheme are extracted to form a flexibly configurable shared cache module, so that the cache utilization rate and the utilization flexibility of the 5G NR protocol acceleration module are improved, meanwhile, the data interaction efficiency among the acceleration modules can be improved, and the data interaction delay is reduced. The method can analyze the collected debugging data in real time in the chip and transmit the analysis result out of the chip, thereby saving the on-chip storage space brought by acquisition and caching of a large amount of protocol data and improving the debugging and protocol analysis efficiency by adopting a field real-time analysis method.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (10)
1. An apparatus for flexible use of data caching in a 5G communication chip, the apparatus comprising: the system comprises a cache allocation control unit, a shared cache unit, a plurality of 5G NR protocol acceleration modules and a bus;
one end of the cache allocation control unit is connected with one end of the shared cache unit, and the other end of the cache allocation control unit is connected with the bus;
the other end of the shared cache unit is connected with one end of the plurality of 5G NR protocol acceleration modules;
the other ends of the plurality of 5G NR protocol acceleration modules are connected with the bus;
the shared cache unit comprises a plurality of cache units;
the cache allocation control unit allocates the cache units in the shared cache unit to the 5G NR protocol acceleration modules for use.
2. The apparatus as claimed in claim 1, wherein the shared buffer unit further comprises: a data selector unit;
the data selector unit is respectively connected with the plurality of cache units, the cache allocation control unit and the plurality of 5GNR protocol acceleration modules.
3. The apparatus as claimed in claim 2, wherein the shared buffer unit further comprises: a plurality of data ports;
one end of each of the plurality of data ports is connected with the data selection unit, and the other end of each of the plurality of data ports is connected with the plurality of 5G NR protocol acceleration modules; the data ports are used for carrying out data transmission with the 5G NR protocol acceleration modules; from which buffer unit the data originates is selected by the data selector unit.
4. The apparatus as claimed in claim 3, wherein the data ports are compatible with multiple data transmission modes.
5. The apparatus of claim 1, wherein the apparatus further comprises:
and the system shared cache is connected with the bus.
6. The apparatus of claim 1, wherein the apparatus further comprises:
and the system CPU is connected with the bus.
7. Use of the apparatus for flexible use of data buffer in 5G communication chip according to any of claims 1 to 6, wherein the method comprises:
and allocating the plurality of buffer units to the plurality of 5G NR protocol acceleration modules by using the buffer allocation control unit.
8. The method as claimed in claim 7, wherein the step of allocating the plurality of buffer units to the plurality of 5GNR protocol acceleration modules by the buffer allocation control unit comprises:
and controlling the data selection unit to distribute the buffer units to the 5G NR protocol acceleration modules by using the buffer distribution control unit.
9. The method as claimed in claim 8, wherein the step of controlling the data selection unit to allocate the plurality of buffer units to the plurality of 5G NR protocol acceleration modules by the buffer allocation control unit comprises:
transmitting the configuration information to a cache allocation control unit through a bus;
transmitting the configuration information to a data selector unit through the cache allocation control unit; and enabling the control selector unit to distribute the cache units to the 5G NR protocol acceleration modules according to the configuration information.
10. The method as claimed in claim 9, wherein the configuration information includes: the cache starting address occupied by each 5G NR protocol acceleration module and the cache size occupied by each protocol acceleration module.
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