CN113795048A

CN113795048A - Power processing method, communication device, chip and module equipment thereof

Info

Publication number: CN113795048A
Application number: CN202111260458.7A
Authority: CN
Inventors: 杨扬; 朱志辉; 谭舒
Original assignee: Unisoc Chongqing Technology Co Ltd
Current assignee: Unisoc Chongqing Technology Co Ltd
Priority date: 2021-10-27
Filing date: 2021-10-27
Publication date: 2021-12-14
Anticipated expiration: 2041-10-27
Also published as: CN113795048B

Abstract

The application discloses a power processing method, a communication device, a chip and module equipment thereof. The method comprises the following steps: receiving a first primary synchronization signal PSS of a cell to be accessed; carrying out correlation operation on the first PSS and a local PSS to obtain a first correlation power sequence; determining a first shift factor according to the first correlation power sequence; and performing shift processing on the first correlation power sequence according to the first shift factor to obtain a first node power sequence. By implementing the method provided by the embodiment of the application, the shifting factor can be calculated in real time according to the received PSS, so that the accuracy of the first node power sequence is improved, the position of the PSS of the cell to be accessed is determined, and the downlink synchronization with the cell to be accessed is completed.

Description

Power processing method, communication device, chip and module equipment thereof

Technical Field

The present application relates to the field of communications technologies, and in particular, to a power processing method, a communication device, a chip, and a module device thereof.

Background

In the cell search process, the terminal device may receive a Primary Synchronization Signal (PSS) from a cell to be accessed, and obtain a physical layer identifier of the cell to be accessed and complete downlink synchronization by determining a position of the PSS. The terminal device may perform correlation operation on the PSS received from the cell to be accessed and the local PSS, so as to determine the location of the cell PSS to be accessed through the location of the node power value exceeding the threshold value. Since the bit width of the correlation power sequence obtained after the correlation operation is wide, a shift factor is usually configured through software to shift the correlation power sequence and store the shifted node power value. However, the shifting factor configured by software hardly considers different scenarios, and the shifted node power value may be inaccurate, so that the position of the cell PSS to be accessed cannot be determined by the node power value exceeding the threshold value in the node power values, and further downlink synchronization with the cell to be accessed cannot be completed.

Therefore, how to improve the accuracy of the node power value in the shift storage process becomes a hot problem of current research.

Disclosure of Invention

The application discloses a power processing method, a communication device, a chip and module equipment thereof, which can calculate a shift factor in real time according to a received PSS, thereby improving the accuracy of a first node power sequence, determining the position of a cell PSS to be accessed, and further completing downlink synchronization with the cell to be accessed.

In a first aspect, the present application provides a power processing method, including: receiving a first primary synchronization signal PSS of a cell to be accessed; carrying out correlation operation on the first PSS and a local PSS to obtain a first correlation power sequence; determining a first shift factor according to the first correlation power sequence; and performing shift processing on the first correlation power sequence according to the first shift factor to obtain a first node power sequence.

In one implementation, obtaining a maximum power value in the first correlation power sequence; and determining a first shift factor based on the maximum power value.

In one implementation, a second shift factor is determined according to the first node power sequence; updating the first shifting factor according to the first shifting factor and the second shifting factor to obtain an updated first shifting factor; receiving a second PSS of the cell to be accessed; performing correlation operation on the second PSS and a local PSS to obtain a second correlation power sequence; shifting the third related power sequence according to the updated first shifting factor to obtain a second node power sequence; wherein the third correlation power sequence is a sum of the first correlation power sequence and the second correlation power sequence.

In one implementation, the second shifting factor is updated according to the second node power sequence.

In one implementation, the first correlation power sequence is shifted according to the second shift factor to obtain a third node power sequence; wherein the second node power sequence and the third node power sequence each include a plurality of power values; carrying out arithmetic mean operation on corresponding power values in the second node power sequence and the third node power sequence to obtain a fourth node power sequence; and updating the second shift factor according to the fourth node power sequence.

In one implementation, obtaining a maximum power value in the first node power sequence; the second shift factor is determined based on the maximum power value.

In one implementation, the updated first shift factor is a sum of the second shift factor and the first shift factor.

In a second aspect, the present application provides a communication device for implementing the units of the method in the first aspect and any possible implementation manner thereof.

In a third aspect, the present application provides a communication device comprising a processor configured to perform the method of the first aspect and any possible implementation manner thereof.

In a fourth aspect, the present application provides a communication device comprising a processor and a memory for storing computer-executable instructions; the processor is configured to invoke the program code from the memory to perform the method of the first aspect and any possible implementation thereof.

In a fifth aspect, the present application provides a chip, configured to receive a first primary synchronization signal PSS of a cell to be accessed; carrying out correlation operation on the first PSS and a local PSS to obtain a first correlation power sequence; determining a first shift factor according to the first correlation power sequence; and performing shift processing on the first correlation power sequence according to the first shift factor to obtain a first node power sequence.

In a sixth aspect, the present application provides a module device, which includes a communication module, a power module, a storage module, and a chip module, wherein: the power module is used for providing electric energy for the module equipment; the storage module is used for storing data and instructions; the communication module is used for carrying out internal communication of the module equipment or is used for carrying out communication between the module equipment and external equipment; this chip module is used for: receiving a first primary synchronization signal PSS of a cell to be accessed; carrying out correlation operation on the first PSS and a local PSS to obtain a first correlation power sequence; determining a first shift factor according to the first correlation power sequence; and performing shift processing on the first correlation power sequence according to the first shift factor to obtain a first node power sequence.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is an architecture diagram of a communication system according to an embodiment of the present application;

fig. 2 is a flowchart of a power processing method according to an embodiment of the present application;

FIG. 2A is a flow chart of a PSS sample counter according to an embodiment of the present disclosure;

FIG. 3 is a flow chart of another power processing method provided by an embodiment of the present application;

fig. 3A is a schematic structural diagram of a cache provided in the present embodiment;

FIG. 3B is a diagram illustrating a storage format of shifting factors according to an embodiment of the present application;

fig. 3C is a timing diagram of reading and writing of a cache according to an embodiment of the present disclosure;

FIG. 4 is a flow chart of another power processing method provided in the embodiments of the present application;

fig. 5 is a schematic structural diagram of a communication device according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of another communication device according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a module apparatus according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is an architecture diagram of a communication system according to an embodiment of the present disclosure. As shown in fig. 1, the communication system may include a terminal device 101 and a network device 102. In this embodiment, the terminal device 101 is within the coverage of the network device 102, the cell served by the network device 102 includes the cell to be accessed mentioned in this embodiment, and the oval area in fig. 1 may represent the coverage area of the cell to be accessed. It should be noted that the number of the terminal devices 101 and the network devices 102 shown in fig. 1 is only for example and is not limited to the present application.

The terminal device 101 may receive the PSS from the cell to be accessed, and perform a correlation operation on the PSS and the local PSS to obtain a first correlation power sequence. When the PSS of the cell to be accessed is the first PSS received by the terminal device, that is, the first PSS is received, the terminal device may perform correlation operation on the first PSS and the local PSS to obtain a first correlation power sequence, and determine a first shift factor; and shifting the first related power sequence according to the first shifting factor to obtain a first node power sequence so as to output a node power value exceeding a threshold value in the first node power sequence.

When the PSS of the cell to be accessed is a non-first PSS received by the terminal device, that is, a second PSS is received, and the terminal device may perform correlation operation on the second PSS and the local PSS to obtain a second correlation power sequence; shifting the third related power sequence by acquiring the updated first shifting factor to obtain a second node power sequence; shifting the first related power sequence by acquiring a second shifting factor to obtain a third node power sequence; and performing arithmetic mean operation on corresponding power values in the second node power sequence and the third node power sequence to obtain a fourth node power sequence, thereby outputting the node power value exceeding the threshold value in the fourth node power sequence. The second shift factor may be determined by a first node power sequence, and the third correlation power sequence is a sum of the first correlation power sequence and the second correlation power sequence.

By outputting the node power value exceeding the threshold value in the node power sequence (such as the first node power sequence) after the first PSS sample shift processing and the node power sequence (such as the fourth node power sequence) after the non-first PSS sample shift processing, the position of the node power value can be used as a candidate position of the cell PSS to be accessed, so that the candidate position can be further screened, and the position of the cell to be accessed is further determined.

The terminal device 101 is an entity, such as a mobile phone, on the user side for receiving or transmitting signals. A terminal device may also be referred to as a terminal (terminal), a User Equipment (UE), a Mobile Station (MS), a Mobile Terminal (MT), etc. The terminal device may be a mobile phone (mobile phone), a wearable device, a tablet (Pad), a computer with wireless transceiving function, a Virtual Reality (VR) terminal device, an Augmented Reality (AR) terminal device, a wireless terminal in industrial control (industrial control), a wireless terminal in self-driving (self-driving), a wireless terminal in remote surgery (remote surgery), a wireless terminal in smart grid (smart grid), a wireless terminal in transportation safety (transportation safety), a wireless terminal in city (city), a wireless terminal in smart home (smart home), a device for supporting enhanced Machine-Type communication (eMTC), and/or a Long Term Evolution (LTE) terminal supporting universal mobile communication technology, and so on. The embodiment of the present application does not limit the specific technology and the specific device form adopted by the terminal device.

The network device 102 is an entity on the network side for transmitting or receiving signals. For example, the network device may be an evolved NodeB (eNB), a transmission point (TRP), a next generation base station (gNB) in the NR system, a base station in other future mobile communication systems, or an access node in a wireless fidelity (WiFi) system. The embodiments of the present application do not limit the specific technologies and the specific device forms used by the network devices.

It should be noted that the technical solutions of the embodiments of the present application can be applied to various communication systems. For example: a Long Term Evolution (LTE) system, a 5th generation (5G) mobile communication system, and a 5G New Radio (NR) system. Optionally, the method of the embodiment of the present application is also applicable to various future communication systems, such as a 6G system or other communication networks.

Referring to fig. 2, fig. 2 is a flowchart illustrating a power processing method according to an embodiment of the present disclosure. The power processing method may be implemented by the terminal device, or may be implemented by a chip in the terminal device. As shown in fig. 2, the power processing method includes, but is not limited to, the following steps S201 to S203.

Step S201, the terminal device receives a first primary synchronization signal PSS of a cell to be accessed.

In the cell search process, in order to acquire the physical identifier of the cell to be accessed and complete downlink synchronization with the cell to be accessed, the terminal device may determine the position of the PSS of the cell to be accessed by receiving the PSS of the cell to be accessed and performing a series of operations on the PSS and a local PSS, so as to acquire the physical identifier of the cell to be accessed and complete downlink synchronization with the cell to be accessed.

The first PSS may be any segment of signal in the PSS of the cell to be accessed. Optionally, the terminal device may receive the PSS segment of the cell to be accessed through a time window with a fixed length (e.g., 5ms) to obtain a first PSS sample (i.e., the first PSS mentioned above), a second PSS sample (i.e., the second PSS mentioned below), a third PSS sample, and so on. Optionally, the terminal device may receive multiple PSS samples to obtain more PSS data of the cell to be accessed, so that subsequent calculation and screening may be more accurate. For example: if the PSS sample received by the terminal equipment contains the peak data of the PSS of the cell to be accessed, the possibility of outputting a power node value exceeding a threshold value in the shifting processing process of the PSS sample is high; if the PSS sample received by the terminal device does not contain the peak data of the PSS of the cell to be accessed, the probability of outputting the node power value exceeding the threshold value in the shifting process of the PSS sample is low. By receiving the PSS of the cell to be accessed in a segmented manner, each segment of PSS sample and the local PSS can be respectively subjected to correlation operation, so that the node power value exceeding the threshold value after operation is reserved, and the node power value smaller than the threshold value is eliminated, thereby being beneficial to determining the power value of the PSS position of the cell to be accessed from the positions of the node power values.

It should be noted that, after receiving the PSS of the cell to be accessed, the terminal device may perform preprocessing on the PSS. Wherein, the pre-processing of the PSS may include: direct Current (DC) cancellation and Delayed Automatic Gain Control (DAGC) adjustment to eliminate noise, interference, and the like in the PSS, thereby obtaining a clearer PSS; the pre-processing of the PSS may further comprise: the PSS is subjected to Inverse Fast Fourier Transform (IFFT) conversion, thereby acquiring an IFFT frequency domain sequence of the PSS.

Optionally, the terminal device may pre-configure the frequency offset branch for the first PSS. The number of frequency offset branches and the offset thereof can be configured in advance. For example, the terminal device may configure 1 or 3 frequency offset branches for the first PSS; the terminal device may also configure each frequency offset branch to be offset leftward by 5 bits, which is not limited in this application. It should be noted that, how many frequency offset branches are configured for the first PSS by the terminal device, that is, how many paths of data (i.e., frequency domain sequences) can be obtained. For example, the terminal device is configured with 3 frequency offset branches, and then 3 paths of data can be obtained.

Optionally, as shown in fig. 2A, the terminal device may determine whether the received PSS is the first PSS sample through the PSS sample counter. Wherein, the value of the PSS sample counter may be increased by 1 every time the terminal device receives one PSS sample. Optionally, the terminal device may initialize a value of the PSS sample counter when starting up, and set a number threshold value for the PSS sample counter. Exemplarily, when the PSS is received for the first time after the terminal device is turned on, the PSS may be determined as a first PSS sample; upon receiving the PSS a second time after the terminal device is powered on, the PSS may be determined to be a second PSS sample, which belongs to the non-first PSS sample. It should be noted that, when the number of PSS samples received by the terminal device reaches the threshold value of the number of PSS sample counters, the value of the PSS sample counter may be cleared, that is, the value of the PSS sample counter is initialized again. It can be understood that, after the value of the PSS sample counter is cleared, the next PSS sample received by the terminal device may be the first PSS sample.

It should be noted that, since the first PSS sample and the non-first PSS sample are processed in different manners, the embodiments of the present application will describe in detail the processing manner of the first PSS sample (see the relevant steps in the embodiments corresponding to fig. 2 and fig. 3) and the processing manner of the non-first PSS sample (see the relevant steps in the embodiments corresponding to fig. 4), respectively.

Step S202, the terminal device performs correlation operation on the first PSS and the local PSS to obtain a first correlation power sequence.

The local PSS may be the PSS of the current serving cell of the terminal device or the PSS of the historically accessed serving cell. Optionally, the terminal device may obtain the local PSS by obtaining the PSS stored in the storage device. Optionally, the local PSS may be a frequency domain sequence, so as to perform correlation operation on the frequency domain sequence of the local PSS and the frequency domain sequence of the first PSS. It should be noted that, before performing a correlation operation on the local PSS and the PSS received from the cell to be accessed, the local PSS may be preprocessed. For example: and generating a local PSS sequence and zero padding the local PSS sequence so as to enable the local PSS sequence to reach the required length under the condition that the length of the local PSS sequence is insufficient, so that correlation operation can be carried out on the received PSS. Illustratively, when the local PSS is less than 1024 bits long, the local PSS may be zero-padded to 1024 bits.

Optionally, network identity2 (NID)⁽²⁾) May be used to indicate the local PSS, the NID⁽²⁾The value of (a) may be 0, 1 or2, i.e. at most 3 local PSS's may exist. Wherein the NID⁽²⁾May be an identifier in a Physical Cell Identifier (PCI). It should be noted that the PCI may be used to identify a cell in the physical layer. The terminal device may pass a network identity1 (NID) through network identifier one⁽¹⁾) And NID⁽²⁾The PCI is determined. In one implementation, PCI-3 NID⁽¹⁾+NID⁽²⁾See in particular the description in standard 38.211. Wherein NID1 is obtained from SSS, NID⁽²⁾Can be obtained from PSS. The network identifier may also be referred to as a network identification code. PCI may be expressed as

NID⁽¹⁾Can be expressed as

NID⁽²⁾Can be expressed as

For example, when there are multiple local PSS, for example, there are 3 local PSS, the terminal device may perform correlation operation on the received first PSS and the 3 local PSS respectively, to determine one or more local PSS which are most similar to the received first PSS from the 3 local PSS, that is, after performing the relocation process, there are one or more local PSS corresponding to the node power value exceeding the threshold value, so as to obtain the physical cell identifier corresponding to the one or more local PSS through the related data of the local PSS, so as to determine the possible location of the received first PSS.

Step S203, the terminal device determines a first shifting factor according to the first correlation power sequence.

Since the correlation operation may be a sliding correlation, i.e. the terminal device may correlate the local PSS frequency domain sequence segment with the frequency domain sequence of the first PSS. For example, the terminal device may sequentially slide the local PSS frequency domain sequence by a length of 5ms to perform correlation operation with the frequency domain sequence of the first PSS. For example: if the total length of the frequency domain sequence of the local PSS is 15ms, the local PSS may be divided into 3 segments of frequency domain sequences with a length of 5ms, and the 3 segments of frequency domain sequences are respectively subjected to correlation operation with the frequency domain sequence of the first PSS once.

Optionally, in the presence of 3 local PSS, the first PSS may be respectively sliding-correlated with the first local PSS to obtain a correlated power sequence 1, sliding-correlated with the second local PSS to obtain a correlated power sequence 2, and sliding-correlated with the third local PSS to obtain a correlated power sequence 3; the first correlation power sequence may be a sequence set of a correlation power sequence 1, a correlation power sequence 2, and a correlation power sequence 3. That is, the first correlation power sequence may include three sets of correlation power sequences, and each set of correlation power sequences may include a plurality of power values. And then, shifting each group of the related power sequences in the first related power sequences respectively to determine one or more groups of related power sequences most related to the first PSS, namely one or more local PSS.

It should be noted that, the embodiment corresponding to fig. 2 may be a processing manner of a first PSS sample, that is, the first PSS may be a PSS sample received for the first time after initializing a sample counter for the terminal device; thus, the terminal device may determine the first shift factor for the first PSS sample processing from the first correlation power sequence described above.

In one implementation, the first correlation power sequence may include a plurality of power values. The terminal device may obtain a maximum power value in the first correlation power sequence; and determining a first shift factor based on the maximum power value. Wherein, the calculation formula is as follows:

wherein the content of the first and second substances,

for the first shifting factor, the normafactor 1 is a default value of software configuration, the sign bit (a) represents the sign extension bit of a, and a is a signed number; a in this embodiment may be a maximum power value in the first correlated power sequence. It should be noted that, the sign extension bit of a is understood to extend the value of a to be operated to the standard bit width. For example: if the value of a is 10 bits but the standard bit width is 16 bits, the sign extension bit of the value of a needs to be set to 6 bits to satisfy the standard bit width.

Step S204, the terminal device performs a shift process on the first correlated power sequence according to the first shift factor to obtain a first node power sequence.

The shifting process of the first correlation power sequence according to the first shifting factor can be understood as shifting and truncating each group of correlation power sequences (such as the correlation power sequence 1, the correlation power sequence 2, and the correlation power sequence 3) in the first correlation power sequence according to the first shifting factor. For example: and after a first group of related power sequences (such as the related power sequence 1) in the first related power sequence is shifted to the left or the right according to the first shift factor, intercepting the power value of the shifted node position to be used as the node power value corresponding to the first group of related power sequences. It will be appreciated that each set of associated power sequences may correspond to a node power value. That is, if there are three sets of correlated power sequences, that is, there may be three node power values in the first node power sequence.

It should be noted that, the terminal device determines the first shifting factor according to the maximum power value in the first relevant power sequence, which can ensure that the maximum power value after shifting is also within the range that can be processed by the terminal device, thereby avoiding shifting factors determined by other power values in the first relevant power sequence from causing the power value after shifting to be out of the range that can be processed by the terminal device.

The method comprises the steps of carrying out correlation operation on a first PSS received from a cell to be accessed and a local PSS to obtain a first correlation power sequence, determining a first shifting factor according to the first correlation power sequence, carrying out shifting processing on the first correlation power sequence according to the first shifting factor to obtain a first node power sequence, outputting a node power value exceeding a threshold value in the first node power sequence, and further being beneficial to determining the position of the cell to be accessed PSS from a position corresponding to the node power value.

Referring to fig. 3, fig. 3 is a flowchart of another power processing method according to an embodiment of the present disclosure. The power processing method may be implemented by the terminal device, or may be implemented by a chip in the terminal device. As shown in fig. 3, the power processing method includes, but is not limited to, the following steps S301 to S309.

Step S301, the terminal device may receive a first PSS of a cell to be accessed, and perform a correlation operation between the first PSS and a local PSS to obtain a first correlation sequence.

Alternatively, the first correlation sequence may be formulated

Represents; wherein, f0 may be used to represent the value of the frequency offset branch, and the value range of f0 may be 0-4, that is, at most, 5 frequency offset branches may exist; i may be used to denote the index of the PSS segment, i.e. which segment of the PSS sample the first PSS received is, i is a positive integer; p may be used to represent NID⁽²⁾The value of p can range from 0 to 2, i.e., up to 3 NIDs can exist⁽²⁾(ii) a k1 can be used to represent the value of the data index in the received PSS sample, and k1 is a positive integer.

It should be noted that the first correlation sequence may be used to represent the received data. Illustratively, assuming f0 is 2, i is 3, p is 2, and k1 is 3

May be used to indicate that the received data is the third one of the third PSS samples and has a frequency offset branch of 2, NID⁽²⁾Is 2. It is understood that the first correlation sequences can be combined into the first correlation sequence according to different values obtained by different values of k 1. For example, in the case where k1 is 3, the first correlation sequence may be represented by

Composition is carried out; wherein the content of the first and second substances,

may be the first data in the received sample data,

may be the second data in the received sample data,

may be the third data in the received sample data.

Step S302, the terminal device may calculate power of the first correlation sequence to obtain a first correlation power sequence, and obtain a maximum power value in the first correlation power sequence. Specifically, the formula for calculating the first correlated power sequence and the formula for calculating the maximum power value in the first correlated power sequence are as follows:

wherein the content of the first and second substances,

may be a first sequence of correlation powers and,

the first correlation sequence; MaxCorrPwr may be the maximum power value in the first correlated power sequence. Specifically, the power calculation of the first correlation sequence may be understood as performing power calculation on each data in the first correlation sequence. For example, if k1 is 3, the two pairs may be used separately

And calculating the power by the value of (2). It is understood that the first correlation power sequence may be combined into the first correlation power sequence according to different correlation power values obtained by different values of k 1.

It should be noted that, the details of step S201 and step S202 in the embodiment of fig. 2 can be referred to for the relevant contents of step S301 and step S302, and are not repeated herein.

In step S303, the terminal device may determine a first shift factor according to the maximum power value. Wherein, according to the formula in the corresponding embodiment of fig. 2, the value of a is substituted into the maximum power value, so as to obtain:

wherein the content of the first and second substances,

for the first shifting factor, Normfactor1 is a default value configured by software, and sign bit (maxcotrpwr) may represent a sign extension bit for finding the maximum power value in the first correlated power sequence. It should be noted that, for the relevant content of step S303, refer to the detailed content of step S203 in the embodiment of fig. 2, and the details are not repeated herein.

In step S304, the terminal device may perform shift processing on the first correlated power sequence according to the first shift factor to obtain a first node power sequence. Specifically, the calculation formula of the first node power sequence is as follows:

wherein the content of the first and second substances,

it may be a first sequence of node powers,

may be the first correlation power sequence described above. It should be noted that, in the process of shifting the first correlation power sequence, if the first shift factor is a positive value, the first correlation power sequence is shifted to the left, that is, the value of the first correlation power sequence is amplified; if the first shift factor is negative, the first correlation power sequence is shifted to the right, i.e. the value of the first correlation power sequence is reduced. Illustratively, if

Has a value of 2, i.e.

Is 2²Multiplying the first correlation power sequence by 4, and amplifying the value of the first correlation power sequence; if it is

Has a value of-1, i.e.

Is 2^-1The first correlation power sequence is multiplied 1/2, and the value of the first correlation power sequence is reduced.

It should be noted that, for the relevant content of step S304, refer to the detailed content of step S204 in the embodiment of fig. 2, and the details are not repeated herein.

Optionally, in step S305, the terminal device may determine the second shift factor according to the first node power sequence.

Optionally, the first node power sequence may include a plurality of power values; the terminal device may obtain a maximum power value in the first node power sequence; and determining a second shift factor based on the maximum power value. Wherein, the calculation formula of the maximum power value in the first node power sequence and the calculation formula of the second shift factor are as follows:

wherein MaxTempCorrPwr may be a maximum power value in the first endpoint power sequence,

may be the second shift factorSign hit (maxtempcorrpwr) indicates the sign extension bit for the maximum power value in the first endpoint power sequence.

It should be noted that, during the processing of the first PSS sample, the maximum power value may be directly obtained in the first node power sequence, and the second shift factor may be determined according to the maximum power value. In the processing process of the non-first PSS sample, two node power sequences (e.g., a second node power sequence and a third node power sequence) can be obtained through two shift processes, and then the two node power sequences are subjected to arithmetic mean operation to obtain an averaged node power sequence (e.g., a fourth node power sequence), so that a second shift factor is determined according to a maximum power value in the averaged node power sequence. For details, reference may be made to the following detailed description in the embodiment corresponding to fig. 4, which is not repeated herein.

Optionally, in step S306, the terminal device may branch and NID according to the frequency offset⁽²⁾And storing the second shift factor at the indicated position for use by a next sample.

Optionally, the terminal device may store the second shifting factor in a buffer. Optionally, the terminal device may store the second shifting factor in a buffer corresponding to the second shifting factor, such as the first buffer. Wherein different buffers (such as the first buffer mentioned above, and the second buffer mentioned below) may provide writing and reading for the shift factors (such as the first shift factor and the second shift factor). Referring to fig. 3A, fig. 3A is a schematic structural diagram of a cache. It should be noted that, in the embodiments of the present application, the size of the cache, the data storage format, and the read/write timing mentioned below are all the same.

As can be seen from fig. 3A, the signal lines connecting the buffers may include: a clock signal line CLK, a reset signal line RST _ N, a chip select signal line CEN, a read/write enable signal line WEN, an address signal line ADDR, and an input data signal line DIN and an output data signal line DOUT. The depth of the cache may be 75, that is, at most 75 shift factors may be stored. It should be noted that a single sample may contain 5 mmSecond of data, each millisecond of data may include a maximum of 5 frequency offset branches and 3 NIDs⁽²⁾. Thus, there may be up to 75 shift factors in a single sample. The storage format of the 75 shifting factors can be as shown in fig. 3B.

Optionally, in step S307, the terminal device may update the first shifting factor according to the first shifting factor and the second shifting factor; and based on the frequency offset branch and NID⁽²⁾The indicated location, the updated first shift factor is stored for use by the next sample. In one implementation, the updated first shifting factor is a sum of the first shifting factor and the second shifting factor.

Optionally, the terminal device may store the updated first shifting factor into a buffer. Optionally, the terminal device may store the updated first shifting factor into a buffer corresponding to the shifting factor, such as a second buffer. For the size of the first buffer and the related content of the data storage format, reference may be made to the detailed content in the foregoing step S306, and details of this application are not repeated herein.

Referring to fig. 3C, fig. 3C is a timing diagram of reading and writing of the cache. It should be noted that the read/write timing of the cache may be a mechanism that reads the history value and then writes the updated value. As shown in FIG. 3C, when the chip select signal line is low, it can be understood that the current bit is selected, i.e., the current bit is valid. When the read/write enable signal line is high, the current bit can be read; when the read/write enable signal line is low, it can be understood that the current bit is written. Thus, when address ADDR0 appears in the address signal line, the chip select signal line can be pulled low, i.e., read for the shift factor of address ADDR 0. After reading the shift factor of ADDR0, the data signal line output DOUT0 is output. It should be noted that the output data signal line will not output new data until the next reading is completed, otherwise, the previous data will be output all the time. After the shift factor is updated, the chip select signal line and the read/write enable signal line are pulled low, and the updated shift factor is input into the input data signal line, i.e., the updated shift factor is written into the original address ADDR 0. Note that when the next shift factor is to be processed, the above operation is repeated for the shift factor at ADDR 1.

Step S308, the terminal device determines whether to complete the calculation of each path of data of the first PSS sample, i.e., whether to complete all frequency offset branches and NID⁽²⁾And (4) calculating. If the calculation of each path of data of the first PSS sample is completed, step S309 is executed; if the calculation of each path of data of the first PSS sample is not finished, continuing the next frequency offset branch and NID⁽²⁾The step of calculating (1), namely, performing correlation operation between the first PSS and the local PSS in step S301 to obtain a first correlation sequence.

In step S309, the terminal device ends the shift processing flow of the correlation power value of the first PSS sample.

Note that the frequency offset branch and NID⁽²⁾For each determined path of data, the first PSS sample of the path of data may exist, that is, the shift processing for the first PSS sample may be performed on the first PSS sample in each path of data. After the terminal device completes the shift processing for the first PSS sample in each path of data, the next PSS sample can be processed.

The method comprises the steps of carrying out correlation operation on a received first PSS and a local PSS to obtain a first correlation power sequence, determining a first shifting factor according to a maximum power value in the first correlation power sequence to shift the first correlation power sequence according to the first shifting factor so as to obtain a first node power sequence, determining a second shifting factor according to the maximum power value in the first node power sequence, and updating the first shifting factor according to the sum of the first shifting factor and the second shifting factor so as to be used by a next sample.

Referring to fig. 4, fig. 4 is a flowchart of another power processing method according to an embodiment of the present disclosure. The method takes the non-first PSS as the second PSS sample as an example, and describes the processing flow of the second PSS sample. The power processing method may be implemented by the terminal device, or may be implemented by a chip in the terminal device. As shown in fig. 4, the power processing method includes, but is not limited to, the following steps S401 to S411.

Step S401, the terminal equipment can receive a second PSS of a cell to be accessed, and perform correlation operation on the second PSS and a local PSS to obtain a second correlation sequence; and then, the second correlation sequence is powered to obtain a second correlation power sequence.

The second PSS may be any non-first PSS sample received by the terminal device, and the second correlation power sequence may be a correlation power sequence obtained by performing correlation operation between the second PSS and the local PSS. Alternatively, the second correlation sequence may be formulated

Represents; the second correlation power sequence can be used

Represents; wherein k2 is a positive integer.

It should be noted that, for the relevant content of step S401, reference may be made to details of step S301 and step S302 in the embodiment of fig. 3, and details of this application are not repeated herein.

In step S402, the terminal device obtains the updated first shifting factor (for example, referred to as the first shifting factor 1).

Optionally, the terminal device may obtain the first shifting factor1 from the second buffer. The first shift factor1 may be a sum of the first shift factor and the second shift factor.

It should be noted that, in the shifting process of any non-first PSS sample, the updated first shifting factor may be determined according to the historical node power sequence. For example, if the non-first PSS sample received by the terminal device is the tenth PSS sample, the updated first shift factor may be determined according to the first shift factor and the second shift factor in the ninth PSS sample.

As can be appreciated from the foregoing, the storage of the shift factors (e.g., the second shift factor and the first shift factor of 1, as described above) may be based on frequency offset branching and NID⁽²⁾Indicated bitAnd correspondingly storing in the cache (such as the first cache and the second cache). Thus, in obtaining the shifting factor, the frequency offset branch and NID with the current PSS sample may be obtained in the buffer⁽²⁾The corresponding shift factor.

In step S403, the terminal device shifts the third related power sequence according to the updated first shift factor (i.e., the first shift factor 1), so as to obtain a second node power sequence. Wherein the third correlation power sequence is the sum of the first correlation power sequence and the second correlation power sequence.

Specifically, the calculation formula of the second node power sequence is as follows:

wherein the content of the first and second substances,

the current node power sequence, i.e. the second node power sequence,

may be the related power sequence currently requiring the shift processing, i.e. the third related power sequence described above. Specifically, the first correlation power sequence and the second correlation power sequence each include a plurality of power values, and the third correlation power sequence is a sum of corresponding power values of the first correlation power sequence and the second correlation power sequence, which is understood to be a sum of corresponding power values of the first correlation power sequence and the second correlation power sequence

In the process of shifting the third related power sequence, if the first shift factor1 is a positive value, the third related power sequence is shifted to the left, that is, the value of the third related power sequence is amplified; if the first shift factor1 is negative, the value of the third correlation power sequence is decreased. For details, reference may be made to the detailed description of step S304 in the corresponding embodiment of fig. 3, which is not described herein again.

It should be noted that, in the shifting process of any non-first PSS sample, the correlation power sequence currently needing the shifting process may be determined according to the sum of the correlation power sequence of the historical PSS sample and the correlation power sequence of the received PSS sample. For example, assuming that the PSS sample received by the terminal device is the tenth PSS sample, the correlation power sequence currently required to be shifted may be the sum of the correlation power sequence of the first nine PSS samples and the correlation power sequence of the tenth PSS sample.

Step S404, the terminal device acquires a second shift factor.

Optionally, the terminal device may obtain the second shifting factor from the first buffer. Optionally, when the terminal device obtains the second shifting factor, the terminal device may obtain the frequency offset branch and the NID of the current PSS sample in the first buffer⁽²⁾A corresponding second shift factor. Alternatively, the second shift factor may be used

And (4) showing.

It should be noted that the second shifting factor may be a second shifting factor stored in the first buffer during the shifting process of the historical PSS sample, that is, a second shifting factor determined according to the historical PSS sample. For example, assuming that the PSS sample received by the terminal device is the tenth PSS sample, the second shift factor obtained by the terminal device may be the second shift factor corresponding to the ninth PSS sample.

Step S405, the terminal device shifts the first related power sequence according to the second shift factor to obtain a third node power sequence.

Optionally, the calculation formula of the third node power sequence is as follows:

wherein the content of the first and second substances,

the power of the historical node, i.e. the third node power sequence described above,

may be a historical correlation power sequence, i.e. the first correlation power sequence described above. It should be noted that, in the embodiment of the present application, the non-first PSS sample received by the terminal device is the second PSS sample, that is, the second PSS; therefore, the historical correlation power sequence may be the first correlation power sequence. It can be understood that, if the non-first PSS sample received by the terminal device is the tenth PSS sample, the historical correlation power sequence may be the sum of the correlation power sequences of the first nine PSS samples, which is not limited in this application.

Step S406, the terminal device may perform arithmetic average operation on corresponding power values in the second node power sequence and the third node power sequence to obtain a fourth node power sequence; and determining the maximum power value of the fourth power sequence according to the fourth node power sequence. Alternatively, the maximum power value of the fourth power sequence may be represented by maxccucorrpwr.

It should be noted that the second node power sequence and the third node power sequence both include a plurality of power values, and arithmetic mean operation may be performed on the corresponding power values in the two node power sequences. For example: if k is 6, that is, there are 6 node power values in both the historical sample data and the current sample data, adding the node power values corresponding to the 6 nodes and averaging, for example: and adding the first node power value in the second node power sequence and the first node power value in the third node power sequence, and solving the power average value of the first node, namely the first node power value in the fourth node power sequence.

Optionally, the terminal device may output a node power value exceeding the threshold value in the fourth node power sequence, so as to determine the PSS position of the cell to be accessed through the node power value exceeding the threshold value. Optionally, the terminal device may further determine the maximum power value of the accumulated node power sequence according to the fourth node power sequence. For example, assuming that k is 6, the terminal device may find the maximum power value from the 6 power values after calculating the average value of the 6 node powers, such as: the power value of the second node is the maximum, i.e. the power value of the second node is the maximum power value after accumulation.

Optionally, in step S407, the terminal device may update the second shifting factor (for example, referred to as a second shifting factor 1) according to the maximum power value of the fourth node power sequence.

Optionally, the calculation formula of the second shift factor1 is as follows:

wherein the content of the first and second substances,

may be a second shift factor of 1, and Normfactor2 may be a default value configured by software; maxcucurpwr is the maximum power value in the fourth node power sequence, and sign bit (maxcucurpwr) represents the sign extension bit of maxcucurpwr. It should be noted that the normafactor 2 may be the same as or different from the normafactor 1, and the present application is not limited thereto.

Optionally, in step S408, the terminal device may branch and NID according to the frequency offset⁽²⁾The updated second shift factor (i.e., second shift factor 1) is stored for use by the next sample at the indicated location.

It should be noted that, the relevant content of step S408 can refer to the detailed content of step S306 in the embodiment of fig. 3, and is not described herein again.

Optionally, in step S409, the terminal device may update the updated first shift factor (for example, referred to as a first shift factor 2) according to the updated first shift factor (i.e., a first shift factor 1) and the updated second shift factor (i.e., a second shift factor 1); and based on the frequency offset branch and NID⁽²⁾The indicated position, the first shift factor (i.e., the first) updated againShift factor 2) for storage for use with the next sample.

It should be noted that the first shift factor2 may be determined by a first shift factor1 and a second shift factor 1. That is, the first shifting factor may be updated again by the first shifting factor used by the previous PSS sample and the second shifting factor updated by the current PSS sample, and the updated first shifting factor may be used for the shifting process of the next sample. For example, if the terminal device receives the tenth non-first PSS sample, the terminal device may update the first shift factor again for use by the eleventh non-first PSS sample according to the first shift factor used by the ninth non-first PSS sample and the second shift factor updated at the tenth non-first PSS sample.

It should be noted that, the details of step S307 in the embodiment of fig. 3 can be referred to for the relevant content of step S409, and the details are not repeated herein.

Step S410, the terminal device determines whether to complete the calculation of each path of data of the non-first PSS sample, i.e. whether to complete all frequency offset branches and NID⁽²⁾And (4) calculating. If the calculation of each path of data of the non-first PSS sample is completed, executing step S411; if the calculation of each path of data of the non-first PSS sample is not finished, continuing to obtain the next frequency offset branch and NID⁽²⁾The step of (3) is to perform a correlation operation between the second PSS and the local PSS in step S401 to obtain a second correlation sequence.

In step S411, the terminal device ends the shift processing flow of the correlation power value of the non-first PSS sample.

It should be noted that, for the relevant contents of step S410 and step S411, refer to the details of step S308 and step S309 in the embodiment of fig. 3, and the details of this application are not repeated herein.

Performing correlation operation on the received second PSS and the local PSS to obtain a second correlation power sequence; obtaining a first shift factor updated after the previous PSS sample is shifted, and shifting the second related power sequence and a third related power sequence determined by the historical related power sequence to obtain a second node power sequence; obtaining a second shift factor of the previous PSS sample, and shifting the historical related power sequence to obtain a third node power sequence; and determining a fourth node power sequence according to the second node power sequence and the third node power sequence so as to output a node power value exceeding a threshold value in the fourth node power sequence and further determine the position of the cell PSS to be accessed.

The power processing method for the first PSS sample and the non-first PSS sample provided by the embodiment of the application can utilize the autocorrelation and the cross correlation of the PSS to perform correlation operation on the received PSS and the local PSS so as to determine the related power sequence, and can determine the shifting factor corresponding to each PSS sample in real time according to the maximum power value in the related power sequence, so that the related power sequence can be shifted according to the shifting factor updated in real time, and further the shifting factor can be dynamically adjusted according to the actual scene and the signal quality, so that the shifted power value is more accurate, and further the position of the PSS to be accessed is screened.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a communication device according to an embodiment of the present disclosure. The device may be a terminal device, or a device in the terminal device, or a device capable of being used in cooperation with the terminal device. The communication apparatus shown in fig. 5 may include a communication unit 501, a processing unit 502, and a determination unit 503. The processing unit 502 is configured to perform data processing. Wherein:

the communication unit 501 is configured to receive a first primary synchronization signal PSS of a cell to be accessed;

the processing unit 502 is configured to perform correlation operation on the first PSS and a local PSS to obtain a first correlation power sequence;

the determining unit 503 is configured to determine a first shifting factor according to the first correlation power sequence;

the processing unit 502 is further configured to perform a shift process on the first correlated power sequence according to the first shift factor to obtain a first node power sequence.

In an implementation manner, the processing unit 502 is further configured to obtain a maximum power value in the first correlation power sequence; the determining unit 503 is further configured to determine the first shifting factor according to the maximum power value.

In an implementation manner, the determining unit 503 is further configured to determine a second shifting factor according to the first node power sequence; the processing unit 502 is further configured to update the first shifting factor according to the first shifting factor and the second shifting factor to obtain an updated first shifting factor; the communication unit 501 is further configured to receive a second PSS of the cell to be accessed; the processing unit 502 is further configured to perform correlation operation on the second PSS and the local PSS to obtain a second correlation power sequence; the processing unit 502 is further configured to shift the third relevant power sequence according to the updated first shift factor to obtain a second node power sequence; wherein the third correlation power sequence is a sum of the first correlation power sequence and the second correlation power sequence.

In an implementation manner, the processing unit 502 is further configured to update the second shifting factor according to the second node power sequence.

In an implementation manner, the processing unit 502 is further configured to perform a shift processing on the first correlated power sequence according to the second shift factor to obtain a third node power sequence; wherein the second node power sequence and the third node power sequence each include a plurality of power values; the processing unit 502 is further configured to perform arithmetic average operation on corresponding power values in the second node power sequence and the third node power sequence to obtain a fourth node power sequence; the processing unit 502 is further configured to update the second shifting factor according to the fourth node power sequence.

In an implementation manner, the processing unit 502 is further configured to obtain a maximum power value in the first node power sequence; the determining unit 503 is further configured to determine the second shifting factor according to the maximum power value.

According to the embodiment of the present application, the units in the communication apparatus shown in fig. 5 may be respectively or entirely combined into one or several other units to form the unit, or some unit(s) therein may be further split into multiple units with smaller functions to form the unit(s), which may achieve the same operation without affecting the achievement of the technical effect of the embodiment of the present application. The units are divided based on logic functions, and in practical application, the functions of one unit can be realized by a plurality of units, or the functions of a plurality of units can be realized by one unit. In other embodiments of the present application, the communication device may also include other units, and in practical applications, the functions may also be implemented by being assisted by other units, and may be implemented by cooperation of a plurality of units.

The communication device may be, for example: a chip, or a chip module. Each module included in each apparatus and product described in the above embodiments may be a software module, a hardware module, or a part of the software module and a part of the hardware module. For example, for each device or product applied to or integrated in a chip, each module included in the device or product may be implemented by hardware such as a circuit, or at least a part of the modules may be implemented by a software program running on a processor integrated in the chip, and the rest (if any) part of the modules may be implemented by hardware such as a circuit; for each device and product applied to or integrated with the chip module, each module included in the device and product may be implemented in a hardware manner such as a circuit, and different modules may be located in the same component (e.g., a chip, a circuit module, etc.) or different components of the chip module, or at least a part of the modules may be implemented in a software program running on a processor integrated within the chip module, and the rest (if any) part of the modules may be implemented in a hardware manner such as a circuit; for each device and product applied to or integrated in the terminal, each module included in the device and product may be implemented by using hardware such as a circuit, different modules may be located in the same component (e.g., a chip, a circuit module, etc.) or different components in the terminal, or at least a part of the modules may be implemented by using a software program running on a processor integrated in the terminal, and the rest (if any) part of the modules may be implemented by using hardware such as a circuit.

The embodiments of the present application and the embodiments of the foregoing method are based on the same concept, and the technical effects thereof are also the same, and for the specific principle, reference is made to the description of the foregoing embodiments, which is not repeated herein.

Referring to fig. 6, fig. 6 is a communication device 60 according to an embodiment of the present disclosure. As shown in fig. 6, the communication device 60 may include a transceiver 601 and a processor 602. Optionally, the communication device may further comprise a memory 603. The transceiver 601, the processor 602, and the memory 603 may be connected by a bus 604 or other means. The bus lines are shown in fig. 6 as thick lines, and the connection between other components is merely illustrative and not intended to be limiting. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in FIG. 6, but this is not intended to represent only one bus or type of bus.

The coupling in the embodiments of the present application is an indirect coupling or a communication connection between devices, units or modules, and may be an electrical, mechanical or other form for information interaction between the devices, units or modules. The specific connection medium among the transceiver 601, the processor 602, and the memory 603 is not limited in the embodiments of the present application.

Memory 603 may include both read-only memory and random access memory, and provides instructions and data to processor 602. A portion of the memory 603 may also include non-volatile random access memory.

The Processor 602 may be a Central Processing Unit (CPU), and the Processor 602 may also be other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, etc. A general purpose processor may be a microprocessor, but in the alternative, the processor 602 may be any conventional processor or the like. Wherein:

a memory 603 for storing program instructions.

A processor 602 for invoking program instructions stored in memory 603 for:

calling a transceiver 601 for receiving a first primary synchronization signal PSS of a cell to be accessed;

the processor 602 is further configured to perform correlation operation on the first PSS and a local PSS to obtain a first correlation power sequence;

the processor 602 is further configured to determine a first shifting factor according to the first correlation power sequence;

the processor 602 is further configured to perform a shift process on the first correlation power sequence according to the first shift factor to obtain a first node power sequence.

In an implementation manner, the processor 602 is further configured to obtain a maximum power value in the first correlation power sequence; the processor 602 is further configured to determine a first shift factor according to the maximum power value.

In one implementation, the processor 602 is further configured to determine a second shift factor according to the first node power sequence; the processor 602 is further configured to update the first shifting factor according to the first shifting factor and the second shifting factor to obtain an updated first shifting factor; the transceiver 601 is further configured to receive a second PSS of the cell to be accessed; the processor 602 is further configured to perform correlation operation on the second PSS and the local PSS to obtain a second correlation power sequence; the processor 602 is further configured to perform shift processing on the third relevant power sequence according to the updated first shift factor, so as to obtain a second node power sequence; wherein the third correlation power sequence is a sum of the first correlation power sequence and the second correlation power sequence.

In one implementation, the processor 602 is further configured to update the second shifting factor according to the second node power sequence.

In an implementation manner, the processor 602 is further configured to perform a shift processing on the first correlation power sequence according to the second shift factor to obtain a third node power sequence; wherein the second node power sequence and the third node power sequence each include a plurality of power values; the processor 602 is further configured to perform an arithmetic average operation on corresponding power values in the second node power sequence and the third node power sequence to obtain a fourth node power sequence; the processor 602 is further configured to update the second shifting factor according to the fourth node power sequence.

In an implementation manner, the processor 602 is further configured to obtain a maximum power value in the first node power sequence; the processor 602 is further configured to determine the second shifting factor according to the maximum power value.

In the embodiments of the present application, the methods provided by the embodiments of the present application may be implemented by running a computer program (including program codes) capable of executing the steps involved in the respective methods as shown in fig. 2, 3, and 4 on a general-purpose computing device such as a computer including a Central Processing Unit (CPU), a random access storage medium (RAM), a read-only storage medium (ROM), and the like, and a storage element. The computer program may be recorded on a computer-readable recording medium, for example, and loaded and executed in the above-described computing apparatus via the computer-readable recording medium.

Based on the same inventive concept, the principle and the advantageous effect of the communication apparatus to solve the problem provided in the embodiment of the present application are similar to the principle and the advantageous effect of the communication apparatus to solve the problem in the embodiment of the method of the present application, and for brevity, the principle and the advantageous effect of the implementation of the method may be referred to, and are not described herein again.

The embodiment of the present application further provides a chip, where the chip may perform relevant steps of the terminal device in the foregoing method embodiment. The chip is used for: receiving a first primary synchronization signal PSS of a cell to be accessed; carrying out correlation operation on the first PSS and a local PSS to obtain a first correlation power sequence;

the chip is further configured to determine a first shifting factor according to the first correlation power sequence;

the chip is further configured to perform a shift process on the first correlation power sequence according to the first shift factor to obtain a first node power sequence.

In an implementation manner, the chip is further configured to obtain a maximum power value in the first correlated power sequence; the chip is further configured to determine a first shift factor according to the maximum power value.

In an implementation manner, the chip is further configured to determine a second shift factor according to the first node power sequence; the chip is further configured to update the first shifting factor according to the first shifting factor and the second shifting factor to obtain an updated first shifting factor; the chip is further configured to receive a second PSS of the cell to be accessed; the chip is also used for carrying out correlation operation on the second PSS and the local PSS to obtain a second correlation power sequence; the chip is further configured to shift the third relevant power sequence according to the updated first shift factor to obtain a second node power sequence; wherein the third correlation power sequence is a sum of the first correlation power sequence and the second correlation power sequence.

In an implementation manner, the chip is further configured to update the second shifting factor according to the second node power sequence.

In an implementation manner, the chip is further configured to perform a shift processing on the first correlation power sequence according to the second shift factor to obtain a third node power sequence; wherein the second node power sequence and the third node power sequence each include a plurality of power values; the chip is further configured to perform arithmetic average operation on corresponding power values in the second node power sequence and the third node power sequence to obtain a fourth node power sequence; the chip is further configured to update the second shifting factor according to the fourth node power sequence.

In an implementation manner, the chip is further configured to obtain a maximum power value in the first node power sequence; the chip is further configured to determine the second shift factor according to the maximum power value.

In one implementation, the chip includes at least one processor, at least one first memory, and at least one second memory; the at least one first memory and the at least one processor are interconnected through a line, and instructions are stored in the first memory; the at least one second memory and the at least one processor are interconnected through a line, and the second memory stores the data required to be stored in the method embodiment.

For each device or product applied to or integrated in the chip, each module included in the device or product may be implemented by hardware such as a circuit, or at least a part of the modules may be implemented by a software program running on a processor integrated in the chip, and the rest (if any) part of the modules may be implemented by hardware such as a circuit.

Referring to fig. 7, fig. 7 is a schematic structural diagram of a module apparatus according to an embodiment of the present disclosure. The module device 70 can perform the steps related to the terminal device in the foregoing method embodiments, and the module device 70 includes: a communication module 701, a power module 702, a memory module 703 and a chip module 704.

The power module 702 is used for providing power for the module device; the storage module 703 is used for storing data and instructions; the communication module 701 is used for performing internal communication of module equipment, or is used for performing communication between the module equipment and external equipment; the chip module 704 is used for:

receiving a first primary synchronization signal PSS of a cell to be accessed;

carrying out correlation operation on the first PSS and a local PSS to obtain a first correlation power sequence;

the chip module 704 is further configured to determine a first shifting factor according to the first correlation power sequence;

the chip module 704 is further configured to shift the first correlation power sequence according to the first shift factor to obtain a first node power sequence.

In an implementation manner, the chip module 704 is further configured to obtain a maximum power value in the first relevant power sequence; the chip module 704 is further configured to determine a first shift factor according to the maximum power value.

In one implementation, the chip module 704 is further configured to determine a second shifting factor according to the first node power sequence; the chip module 704 is further configured to update the first shifting factor according to the first shifting factor and the second shifting factor to obtain an updated first shifting factor; the chip module 704 is further configured to receive a second PSS of the cell to be accessed; the chip module 704 is further configured to perform correlation operation on the second PSS and a local PSS to obtain a second correlation power sequence; the chip module 704 is further configured to shift the third relevant power sequence according to the updated first shift factor to obtain a second node power sequence; wherein the third correlation power sequence is a sum of the first correlation power sequence and the second correlation power sequence.

In one implementation, the chip module 704 is further configured to update the second shifting factor according to the second node power sequence.

In an implementation manner, the chip module 704 is further configured to shift the first correlated power sequence according to the second shift factor to obtain a third node power sequence; wherein the second node power sequence and the third node power sequence each include a plurality of power values; the chip module 704 is further configured to perform arithmetic average operation on corresponding power values in the second node power sequence and the third node power sequence to obtain a fourth node power sequence; the chip module 704 is further configured to update the second shifting factor according to the fourth node power sequence.

In an implementation manner, the chip module 704 is further configured to obtain a maximum power value in the first node power sequence; the chip module 704 is further configured to determine the second shifting factor according to the maximum power value.

For each device and product applied to or integrated in the chip module, each module included in the device and product may be implemented by using hardware such as a circuit, and different modules may be located in the same component (e.g., a chip, a circuit module, etc.) or different components of the chip module, or at least some of the modules may be implemented by using a software program running on a processor integrated in the chip module, and the rest (if any) of the modules may be implemented by using hardware such as a circuit.

The embodiment of the present application further provides a computer-readable storage medium, in which one or more instructions are stored, and the one or more instructions are adapted to be loaded by a processor and execute the method provided by the foregoing method embodiment.

Embodiments of the present application also provide a computer program product containing instructions, which when run on a computer, cause the computer to perform the method provided by the above method embodiments.

It should be noted that, for simplicity of description, the above-mentioned embodiments of the method are described as a series of acts or combinations, but those skilled in the art should understand that the present application is not limited by the order of acts described, as some steps may be performed in other orders or simultaneously according to the present application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.

The steps in the method of the embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs.

The modules in the device can be merged, divided and deleted according to actual needs.

Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, which may include: flash disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.

The above disclosure is only one preferred embodiment of the present invention, which is only a part of the present invention, and certainly not intended to limit the scope of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Claims

1. A method of power processing, the method comprising:

receiving a first primary synchronization signal PSS of a cell to be accessed;

performing correlation operation on the first PSS and a local PSS to obtain a first correlation power sequence;

determining a first shift factor according to the first correlation power sequence;

and carrying out shift processing on the first correlation power sequence according to the first shift factor to obtain a first node power sequence.

2. The method of claim 1, wherein the first correlation power sequence comprises a plurality of power values; the determining a first shift factor according to the first correlation power sequence comprises:

acquiring a maximum power value in the first relevant power sequence;

determining the first shift factor according to the maximum power value.

3. The method of claim 1, further comprising:

determining a second shift factor according to the first node power sequence;

updating the first shifting factor according to the first shifting factor and the second shifting factor to obtain an updated first shifting factor;

receiving a second PSS of the cell to be accessed;

performing correlation operation on the second PSS and the local PSS to obtain a second correlation power sequence;

shifting the third related power sequence according to the updated first shifting factor to obtain a second node power sequence; the third correlation power sequence is the sum of the first correlation power sequence and the second correlation power sequence.

4. The method of claim 3, further comprising:

and updating the second shifting factor according to the second node power sequence.

5. The method of claim 4, wherein said updating said second shifting factor according to said second node power sequence comprises:

according to the second shift factor, shift processing is carried out on the first correlation power sequence to obtain a third node power sequence; wherein the second junction power sequence and the third junction power sequence each comprise a plurality of power values;

performing arithmetic mean operation on corresponding power values in the second node power sequence and the third node power sequence to obtain a fourth node power sequence;

and updating the second shift factor according to the fourth node power sequence.

6. The method of claim 3, wherein the first sequence of node powers comprises a plurality of power values; the determining a second shift factor according to the first node power sequence comprises:

acquiring a maximum power value in the first node power sequence;

determining the second shift factor according to the maximum power value.

7. The method of claim 3, wherein the updated first shifting factor is a sum of the second shifting factor and the first shifting factor.

8. A communication apparatus comprising means for performing the method of any of claims 1-7.

9. A communications apparatus, comprising a processor;

the processor is used for executing the method of any one of claims 1 to 7.

10. The communications apparatus of claim 9, the communications apparatus further comprising a memory:

the memory for storing a computer program;

the processor, in particular for calling the computer program from the memory, to perform the method according to any one of claims 1 to 7.

11. A chip, characterized in that,

the chip is used for receiving a first primary synchronization signal PSS of a cell to be accessed;

the chip is also used for carrying out correlation operation on the first PSS and a local PSS to obtain a first correlation power sequence;

the chip is further configured to determine a first shift factor according to the first correlation power sequence;

the chip is further configured to perform shift processing on the first correlation power sequence according to the first shift factor to obtain a first node power sequence.

12. The utility model provides a module equipment, its characterized in that, module equipment includes communication module, power module, storage module and chip module, wherein:

the power supply module is used for providing electric energy for the module equipment;

the storage module is used for storing data and instructions;

the communication module is used for carrying out internal communication of module equipment or is used for carrying out communication between the module equipment and external equipment;

the chip module is used for:

receiving a first primary synchronization signal PSS of a cell to be accessed;