CN113794412A

CN113794412A - PWM control method and device

Info

Publication number: CN113794412A
Application number: CN202110920758.7A
Authority: CN
Inventors: 周原; 章雪亮; 封宁波
Original assignee: Huawei Digital Power Technologies Co Ltd
Current assignee: Huawei Digital Power Technologies Co Ltd
Priority date: 2021-08-11
Filing date: 2021-08-11
Publication date: 2021-12-14

Abstract

The application provides a PWM control method and a device, and the method comprises the following steps: acquiring junction temperatures of N power semiconductor devices in an inverter circuit, wherein N is an integer greater than 1; when the junction temperature of M power semiconductor devices in the N power semiconductor devices is larger than a first threshold value, injecting a common-mode voltage into the modulation wave, wherein the common-mode voltage is used for reducing the conduction duty ratio of K power semiconductor devices in the M power semiconductor devices, K is an integer larger than 0 and smaller than or equal to M, and M is an integer larger than 0 and smaller than or equal to N; and sending a control signal according to the modulation wave injected with the common-mode voltage. In the technical scheme, the common-mode voltage is injected into the modulation wave, the conduction duty ratio of the power semiconductor device in the inverter circuit is adjusted, the loss of the power semiconductor device in the inverter circuit can be reasonably distributed, the probability of the damage of the power semiconductor device is favorably reduced, and therefore the safety of the system is improved.

Description

PWM control method and device

Technical Field

The present invention relates to the field of power electronics, and in particular, to a Pulse Width Modulation (PWM) control method and apparatus.

Background

For a system using an inverter circuit, when the modulation ratio, the output power factor, or the output frequency of the inverter circuit is small, the current in the inverter circuit may be regarded as direct current, and a part of the power semiconductor devices in the inverter circuit may continuously bear the current. The power semiconductor device that is responsible for this current will have a relatively large loss, whereas the power semiconductor device that is not responsible for this current has a loss of almost 0. That is, the power loss in the inverter circuit is very uneven. Therefore, the loss of individual power semiconductor devices exceeds the standard, and the junction temperature of the power semiconductor devices is too high, so that the power semiconductor devices are damaged, and the safety of the system is influenced.

Disclosure of Invention

The application provides a PWM control method and device, can adjust the turn-on duty ratio of power semiconductor devices in an inverter circuit, can realize the loss of the power semiconductor devices in the inverter circuit of rational distribution, help to reduce the probability of the damage of the power semiconductor devices, thus improve the security of the system.

In a first aspect, the present application provides a PWM control method, which may be performed by a PWM control apparatus, which may be a separately provided module or unit, or may be integrated with other apparatuses, and the present application is not limited thereto.

The method comprises the following steps:

acquiring junction temperatures of N power semiconductor devices in an inverter circuit, wherein N is an integer greater than 1;

when the junction temperature of M power semiconductor devices in the N power semiconductor devices is larger than a first threshold value, injecting a common-mode voltage into a modulation wave, wherein the modulation wave is used for generating a signal for controlling the on or off of at least part of the N power semiconductor devices, the common-mode voltage is used for reducing the on duty ratio of K power semiconductor devices in the M power semiconductor devices, K is an integer larger than 0 and smaller than or equal to M, and M is an integer larger than 0 and smaller than or equal to N;

and sending a control signal according to the modulation wave after the common-mode voltage is injected, wherein the control signal is used for controlling the on or off of at least part of the power semiconductor devices.

The power semiconductor device in the inverter circuit of the present application may include at least one of: insulated Gate Bipolar Transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), diodes, and the like. At least some of the N power semiconductor devices may include at least one of: IGBTs, MOSFETs, and the like.

In the technical scheme, the common-mode voltage is injected into the modulation wave, so that the conduction duty ratio of the power semiconductor device in the inverter circuit can be reasonably distributed, the loss distribution of the power semiconductor device in the inverter circuit is more reasonable, the probability of the damage of the power semiconductor device is favorably reduced, and the safety of the system is improved. In addition, because the on duty ratio of the power semiconductor devices in the inverter circuit can be distributed by injecting the common-mode voltage into the modulation wave, the power semiconductor devices with smaller current levels can be adopted in the inverter circuit, and the cost of the inverter circuit is reduced.

With reference to the first aspect, in a possible implementation manner, the common-mode voltage may cause a change in on duty ratios of power semiconductor devices other than the M power semiconductor devices among the N power semiconductor devices while reducing the on duty ratios of the K power semiconductor devices.

For example, the common mode voltage is used for reducing the on duty ratios of the K power semiconductor devices and simultaneously increasing the on duty ratios of P power semiconductor devices, the P power semiconductor devices belong to the power semiconductor devices except the M power semiconductor devices in the N power semiconductor devices, and P is an integer greater than 0. It can be understood that the common mode voltage is used to adjust the on duty ratios of the K power semiconductor devices and the P power semiconductor devices, so that the P power semiconductor devices share part of the current that should be borne by the K power semiconductor devices, thereby reducing the loss of the K power semiconductor devices and lowering the junction temperature of the K power semiconductor devices.

For another example, the common mode voltage is used to reduce the turn-on duty cycles of the K power semiconductor devices and simultaneously increase the turn-on duty cycles of the P power semiconductor devices, and is also used to reduce the turn-on duty cycles of the R power semiconductor devices, junction temperatures of the R power semiconductor devices do not exceed a first threshold, and the R power semiconductor devices belong to the N power semiconductor devices but do not belong to the K power semiconductor devices and the P power semiconductor devices. It can be understood that the common mode voltage, while decreasing the on duty cycles of the K power semiconductor devices and increasing the on duty cycles of the P power semiconductor devices, may also change the on duty cycles of one or more power semiconductor devices whose junction temperature does not exceed the first threshold.

With reference to the first aspect or any one of possible implementation manners of the first aspect, in another possible implementation manner, when junction temperatures of M power semiconductor devices of the N power semiconductor devices are greater than a first threshold, injecting a common-mode voltage into a modulation wave includes: when the junction temperature of M power semiconductor devices in the N power semiconductor devices is larger than the first threshold value and the modulation ratio of the inverter circuit is lower than a second threshold value, injecting the common-mode voltage into the modulation wave; or, when the junction temperature of M power semiconductor devices of the N power semiconductor devices is greater than the first threshold and the output power factor of the inverter circuit is lower than a third threshold, injecting the common mode voltage into the modulated wave; or, when the junction temperature of M power semiconductor devices of the N power semiconductor devices is greater than the first threshold and the output frequency of the inverter circuit is lower than a fourth threshold, the common-mode voltage is injected into the modulated wave.

That is to say, under the condition that the modulation ratio of the inverter circuit, the output power factor of the inverter circuit, or the output frequency of the inverter circuit is low, the PWM control device injects the common mode voltage into the modulation wave, thereby avoiding the influence of the common mode voltage on the system under the normal working condition.

With reference to the first aspect or any one of possible implementation manners of the first aspect, in another possible implementation manner, the N power semiconductor devices correspond to the N first threshold values one by one, and a junction temperature of each of the M power semiconductor devices is greater than the first threshold value corresponding to the power semiconductor device. In other words, the junction temperatures of the M power semiconductor devices are greater than the first threshold, which can be understood as that the junction temperatures of the M power semiconductor devices are greater than the first threshold corresponding to the power semiconductor devices, respectively.

The N first thresholds may be the same or different. For example, the first threshold values of the same type of power semiconductor device may be the same, and the first threshold values of different types or different types of power semiconductor devices may be different.

With reference to the first aspect or any one of possible implementation manners of the first aspect, in another possible implementation manner, the inverter circuit is a single-phase or multi-phase inverter circuit.

With reference to the first aspect or any one of possible implementation manners of the first aspect, in another possible implementation manner, the inverter circuit adopts a two-level topology or a multi-level topology.

With reference to the first aspect or any one of possible implementations thereof, in another possible implementation, the multi-level topology includes a Neutral Point Clamped (NPC) three-level topology.

The NPC three-level topology structure may include an I-type three-level topology structure, a T-type three-level topology structure, and an Active Neutral Point Clamped (ANPC) three-level topology structure.

With reference to the first aspect or any one of possible implementation manners of the first aspect, in another possible implementation manner, when the inverter circuit adopts an I-type three-level topology or a T-type three-level topology, the amplitude of the common-mode voltage is one fourth of a dc input voltage of the inverter circuit. This makes it possible to achieve a reasonable distribution of the losses of the N power semiconductor devices.

In a second aspect, the present application provides a PWM control apparatus that corresponds to the PWM control method of the first aspect, to which reference may be made for a detailed description, and therefore may also achieve advantageous effects similar to those of the PWM control method of the first aspect.

The device comprises:

the acquiring unit is used for acquiring junction temperatures of N power semiconductor devices in the inverter circuit, wherein N is an integer greater than 1;

the processing unit is used for injecting a common-mode voltage into a modulation wave when the junction temperature of M power semiconductor devices in the N power semiconductor devices is larger than a first threshold, wherein the modulation wave is used for generating signals for controlling at least part of the N power semiconductor devices to be switched on or switched off, the common-mode voltage is used for reducing the on duty ratio of K power semiconductor devices in the M power semiconductor devices, K is an integer larger than 0 and smaller than or equal to M, and M is an integer larger than 0 and smaller than or equal to N;

the processing unit is further configured to send a control signal according to the modulation wave injected with the common-mode voltage, where the control signal is used to control the at least part of the power semiconductor devices to be turned on or off.

With reference to the second aspect, in a possible implementation manner, the common mode voltage is further used to increase on duty ratios of P power semiconductor devices, where the P power semiconductor devices belong to power semiconductor devices other than the M power semiconductor devices in the N power semiconductor devices, and P is an integer greater than 0.

With reference to the second aspect or any one of possible implementations thereof, in another possible implementation, the processing unit is specifically configured to: when the junction temperature of M power semiconductor devices in the N power semiconductor devices is larger than the first threshold value and the modulation ratio of the inverter circuit is lower than a second threshold value, injecting the common-mode voltage into the modulation wave; or, when the junction temperature of M power semiconductor devices of the N power semiconductor devices is greater than the first threshold and the output power factor of the inverter circuit is lower than a third threshold, injecting the common mode voltage into the modulated wave; or, when the junction temperature of M power semiconductor devices of the N power semiconductor devices is greater than the first threshold and the output frequency of the inverter circuit is lower than a fourth threshold, the common-mode voltage is injected into the modulated wave.

With reference to the second aspect or any one of the possible implementation manners of the second aspect, in another possible implementation manner, the N power semiconductor devices correspond to the N first threshold values one by one, and the junction temperature of each of the M power semiconductor devices is greater than the first threshold value corresponding to the power semiconductor device. In other words, the junction temperatures of the M power semiconductor devices are greater than the first threshold, which can be understood as that the junction temperatures of the M power semiconductor devices are greater than the first threshold corresponding to the power semiconductor devices, respectively.

With reference to the second aspect or any one of the possible implementation manners of the second aspect, in another possible implementation manner, the inverter circuit is a single-phase or multi-phase inverter circuit.

With reference to the second aspect or any one of the possible implementation manners of the second aspect, in another possible implementation manner, the inverter circuit adopts a two-level topology or a multi-level topology.

With reference to the second aspect or any one of the possible implementation manners of the second aspect, in another possible implementation manner, when the inverter circuit adopts an I-type three-level topology or a T-type three-level topology, the amplitude of the common-mode voltage is one fourth of a dc input voltage of the inverter circuit.

In a third aspect, the present application provides a PWM control apparatus, which includes a processor and an interface circuit, where the interface circuit is configured to receive a signal from a device other than the PWM control apparatus and transmit the signal to the processor or send the signal from the processor to the device other than the PWM control apparatus, and the processor is configured to implement the method according to the first aspect or any possible implementation manner thereof through a logic circuit or executing code instructions.

In a fourth aspect, the present application provides a PWM control apparatus comprising a processor configured to execute computer instructions stored in a memory to cause the apparatus to perform the method of the first aspect or any possible implementation thereof.

In a fifth aspect, the present application provides a motor controller including the PWM control apparatus according to the second aspect, the third aspect, the fourth aspect, or any possible implementation manner thereof.

In a sixth aspect, the present application provides a chip, where the chip includes a processor, where the processor is connected to a memory, where the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the chip executes the method of the first aspect or any possible implementation manner thereof.

In a seventh aspect, the present application provides a computer storage medium, in which a computer program or instructions are stored, and when the computer program or instructions are executed by a computer, the method of the first aspect or any possible implementation manner thereof can be implemented.

In an eighth aspect, the present application provides a computer program product comprising a computer program or instructions which, when executed by a computer, may implement the method of the first aspect or any possible implementation thereof.

In a ninth aspect, the present application provides an electric drive system, including the PWM control apparatus of the second aspect, the third aspect, the fourth aspect, or any possible implementation manner thereof, or including the motor controller of the fifth aspect, or including the chip of the sixth aspect.

Drawings

Fig. 1 is a block diagram of an electric drive system 100 to which the technical solution of the present application can be applied.

Fig. 2 is a schematic flow chart of a PWM control method 200 provided herein.

Fig. 3 is a schematic diagram of a two-level topology.

Fig. 4 is a schematic diagram of the on duty ratios of S1 and D4.

Fig. 5 is a simulation waveform of two-level inverter modulation wave injection common mode voltage.

Fig. 6 is a schematic diagram of an NPC three-level topology.

FIG. 7 shows S1, S2, D_p1Schematic of the on duty cycles of D3 and D4.

Fig. 8 is a schematic diagram of a T-type three-level topology.

Fig. 9 is a schematic diagram of the on duty ratios of S1, S3, D2, and D4.

Fig. 10 is a schematic structural diagram of an apparatus provided in an embodiment of the present application.

Fig. 11 is another schematic structural diagram of an apparatus provided in an embodiment of the present application.

Detailed Description

The technical solution in the present application will be described below with reference to the accompanying drawings.

This application is intended to present various aspects, embodiments or features around a system comprising a number of devices, components, modules, and the like. It is to be understood and appreciated that the various systems may include additional devices, components, modules, etc. and/or may not include all of the devices, components, modules etc. discussed in connection with the figures. Furthermore, a combination of these schemes may also be used.

In addition, in the embodiments of the present application, words such as "exemplary", "for example", etc. are used to mean serving as examples, illustrations or explanations. Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, the term using examples is intended to present concepts in a concrete fashion.

In the embodiments of the present application, "corresponding" and "corresponding" may be sometimes used in a mixed manner, and it should be noted that the intended meaning is consistent when the difference is not emphasized.

The scenario described in the embodiment of the present application is for more clearly illustrating the technical solution in the embodiment of the present application, and does not form a limitation on the technical solution provided in the embodiment of the present application, and as a person having ordinary skill in the art knows, along with the evolution of the scenario and the appearance of a new service scenario, the technical solution provided in the embodiment of the present application is also applicable to similar technical problems.

Unless otherwise defined, technical or scientific terms used herein in the specification and claims should have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. As used in this specification and the appended claims, the terms "first" or "second," and the like, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.

In the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: including the presence of a alone, a and B together, and B alone, where a, B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple.

Aiming at the problems, the conduction duty ratio of the power semiconductor device in the inverter circuit can be adjusted, the loss of the power semiconductor device in the inverter circuit can be reasonably distributed, the probability of the damage of the power semiconductor device is favorably reduced, and therefore the safety of the system is improved.

It should be noted that the technical solution of the present application can be applied to various systems using an inverter circuit, and the present application is not limited thereto. As an example, the technical solution of the present application may be applied to an electric drive system, for example, an electric drive system of a vehicle, or the like. For convenience of description, the technical solution of the present application will be described below in conjunction with an electric drive system.

As shown in fig. 1, the system 100 includes an inverter circuit, a motor, and a motor controller, wherein the inverter circuit is connected to the dc voltage, the motor, and the motor controller, respectively. An inverter circuit, which may also be referred to as an inverter, is a converter for converting direct current (e.g., batteries, storage batteries, etc.) into alternating current. An electric machine is a device for converting electric energy and mechanical energy into each other. The motor controller, which may also be referred to as a Motor Control Unit (MCU), is configured to control turning on or off of some power semiconductor devices in the inverter circuit according to the received signal wave and the carrier wave. In the system 100, the motor controller controls the on/off of a part of power semiconductor devices in the inverter circuit according to the signal wave and the carrier wave, so that the direct current input into the inverter circuit is converted into alternating current, and the alternating current is converted into mechanical energy for the rotation of the motor through electromagnetic induction after being input into the motor.

It should be noted that the present application does not limit the specific topology of the inverter circuit, for example, the inverter circuit may adopt a two-level topology or a multi-level topology. The multi-level topology may include an NPC three-level topology, among others. The number of phases of the inverter circuit is not limited in the present application, and the inverter circuit may be a single-phase or multi-phase inverter circuit, for example.

It should be understood that the motor controller and the inverter circuit may be integrated into one device, or may be separate devices, which is not specifically limited in this application. In other examples, system 100 may include more, fewer, or different systems, and each system may include more, fewer, or different components. Further, the systems and components shown may be combined or divided in any number of ways.

In the process of driving the motor to rotate, the phenomenon that the motor cannot start or stop rotating may occur, that is, the motor is locked. The motor stalling is a condition that the motor still outputs torque when the rotating speed is 0 revolution, and is generally mechanical or artificial. For example, motor stalling may be caused by excessive motor load, mechanical failure of the traction, or damaged bearings sweeping the chamber. When the motor runs in a locked-rotor mode, the problem of uneven power loss in the inverter circuit can occur. Similarly, the low-speed operation of the motor can be regarded as the splicing of locked-rotor working conditions with different angles and short time, and the problems also exist.

The PWM control method provided in the present application is described below with reference to fig. 2 to 8.

Fig. 2 is a schematic flow chart of a PWM control method 200 provided herein. The method 200 may be applied to the system 100 shown in fig. 1. The method 200 may be performed by a PWM control apparatus, which may be a stand-alone module or unit, or may be integrated with other apparatuses (e.g., a motor controller shown in fig. 1), and the present application is not limited thereto.

And step 210, the PWM control device acquires junction temperatures of N power semiconductor devices in the inverter circuit. Wherein N is an integer greater than 1.

The specific topology of the inverter circuit is not limited in the present application. For example, the inverter circuit may employ a two-level topology or a multi-level topology. The multi-level topology may include an NPC three-level topology, among others. The NPC three-level topology may include an I-type three-level topology, a T-type three-level topology, an ANPC three-level topology, and the like.

The present application also does not limit the number of phases of the inverter circuit. For example, the inverter circuit may be a single-phase or multi-phase inverter circuit.

The method for acquiring the junction temperatures of the N power semiconductor devices by the PWM control apparatus is not limited in the present application.

In some implementations, the PWM control apparatus may obtain a voltage of a modulation wave, determine the on duty ratios of the N power semiconductor devices according to the voltage of the modulation wave, further determine losses of the N power semiconductor devices according to the on duty ratios of the N power semiconductor devices, and further determine junction temperatures of the N power semiconductor devices according to the losses of the N power semiconductor devices, where the modulation wave is a signal for generating a signal for controlling on or off of at least some of the N power semiconductor devices, and the modulation wave may correspond to the signal wave shown in fig. 1. Taking an inverter circuit as a three-phase inverter circuit as an example, the PWM control device may obtain phase voltages of A, B and C three-phase modulation waves, determine conduction duty ratios of the N power semiconductor devices according to the phase voltages of A, B and C three-phase modulation waves, further determine losses of the N power semiconductor devices according to the conduction duty ratios of the N power semiconductor devices, and further determine junction temperatures of the N power semiconductor devices according to the losses of the N power semiconductor devices. The present application does not limit the manner in which the PWM control apparatus obtains the voltage of the modulated wave, and may be, for example, any one of the existing methods or the methods that will come out in the future.

In another implementation, the PWM control apparatus may also directly obtain the junction temperatures of the N power semiconductor devices.

It is to be understood that the manner in which the PWM control apparatus obtains the junction temperatures of the N power semiconductor devices may also be any one of other conventional methods or methods that will come up in the future.

The power semiconductor device in the inverter circuit of the present application may include at least one of: IGBTs, MOSFETs, diodes, and the like. At least some of the N power semiconductor devices may include: IGBTs and/or MOSFETs.

Step 220, when the junction temperature of M power semiconductor devices in the N power semiconductor devices is greater than a first threshold, injecting a common mode voltage to the modulation wave. The common-mode voltage is used for reducing the conduction duty ratio of K power semiconductor devices in the M power semiconductor devices, K is an integer which is larger than 0 and smaller than or equal to M, and M is an integer which is larger than 0 and smaller than or equal to N.

The N power semiconductor devices correspond to the N first threshold values one by one, and the N first threshold values may be the same or different. For example, the first threshold values of the same type of power semiconductor device may be the same, and the first threshold values of different types or different types of power semiconductor devices may be different. The junction temperatures of the M power semiconductor devices are greater than the first threshold, which can be understood as that the junction temperatures of the M power semiconductor devices are greater than the first thresholds corresponding to the power semiconductor devices, respectively.

Because the current in the motor and the inverter circuit depends on the input differential mode voltage, the common mode voltage does not contribute to the current, and the high and low of the common mode voltage can determine the conduction duty ratio of the power semiconductor device of the inverter circuit, the conduction duty ratio of the power semiconductor device of the inverter circuit can be adjusted by adjusting the common mode voltage, and therefore the loss of the power semiconductor device of the inverter circuit can be adjusted.

Optionally, the common-mode voltage may cause a change in the on duty ratios of the power semiconductor devices other than the M power semiconductor devices among the N power semiconductor devices while reducing the on duty ratios of the K power semiconductor devices.

Optionally, in some implementations, the PWM control apparatus may also determine whether the adjustment of the on duty ratio needs to be performed directly according to the losses of the N power semiconductor devices.

Optionally, when the inverter circuit adopts an I-type three-level topology or a T-type three-level topology, the magnitude of the common-mode voltage may be one fourth of the dc input voltage of the inverter circuit. This makes it possible to achieve a reasonable distribution of the losses of the N power semiconductor devices.

In some implementations, before injecting the common mode voltage into the modulated wave, the PWM control apparatus may further determine that a modulation ratio of the inverter circuit is lower than a second threshold, or determine that an output power factor of the inverter circuit is lower than a third threshold, or determine that an output frequency of the inverter circuit is lower than a fourth threshold, that is, when junction temperatures of M power semiconductor devices of the N power semiconductor devices are greater than the first threshold and the modulation ratio of the inverter circuit is lower than the second threshold, or when junction temperatures of M power semiconductor devices of the N power semiconductor devices are greater than the first threshold and the output power factor of the inverter circuit is lower than the third threshold, or when junction temperatures of M power semiconductor devices of the N power semiconductor devices are greater than the first threshold and the output frequency of the inverter circuit is lower than the fourth threshold, and injecting the common mode voltage into the modulation wave. That is, when the modulation ratio of the inverter circuit, the output power factor of the inverter circuit, or the output frequency of the inverter circuit is low, the PWM control device injects the common mode voltage into the modulation wave to adjust the on duty ratios of some of the power semiconductor devices in the inverter circuit. For example, under the condition that the motor is in a locked-rotor condition or a low-frequency large-torque condition, the PWM control device injects common-mode voltage into the modulation wave, so that the influence of the common-mode voltage on the system under the normal condition is avoided.

Step 230, sending a control signal according to the modulation wave after the injection of the common mode voltage, where the control signal is used to control at least some of the N power semiconductor devices to be turned on or off, for example, the control signal controls an IGBT and/or a MOSFET in an inverter circuit to be turned on or off.

The control signal is sent according to the modulation wave injected with the common-mode voltage, so that the conduction duty ratio of part of the power semiconductor devices in the N power semiconductor devices can be changed, and the loss of the N power semiconductor devices can be reasonably distributed.

Like this, above-mentioned technical scheme injects the common mode voltage in the modulation wave, can rationally distribute power semiconductor device's among the inverter circuit turn-on duty cycle to make inverter circuit power semiconductor device's loss distribution more reasonable, help reducing the probability of power semiconductor device damage, thereby improve the security of system. In addition, because the on duty ratio of the power semiconductor devices in the inverter circuit can be distributed by injecting the common-mode voltage into the modulation wave, the power semiconductor devices with smaller current levels can be adopted in the inverter circuit, and the cost of the inverter circuit is reduced.

The PWM control method of the present application is described below with reference to a specific example.

Example 1

Assume that the inverter circuit employs a two-level topology as shown in fig. 3. When the locked-rotor angle of the motor is 90 degrees, the A-phase current I_aMaximum, two phase currents of B phase and C phase are equal, and I_b＝I_c＝-1/2I_a. In this case, the a-phase currents are carried by the S1 and D4 of the a-phase, and the losses approach 0 because no current flows through the S2 and D1 of the a-phase.

Fig. 4 is a schematic diagram of the on duty ratios of S1 and D4.

When the motor is locked, if the on duty is not adjusted, as shown in fig. 4 (a), the on duty of S1 and D4 is about 0.5.

If the PWM control means determines that the junction temperature of D4 is too high and there is a margin for the junction temperature of S1, the PWM control means may inject a positive common mode voltage (e.g., V) to the A, B and C three-phase modulated waves_dc/4), as shown in fig. 4 (b), the on duty of S1 increases, and the on duty of D4 decreases.

If the PWM control means determines that the junction temperature of S1 is too high and there is a margin for the junction temperature of D4, the PWM control means may inject a negative common mode voltage (e.g., -Vdc/4) to the A, B and C three-phase modulation waves, as shown in (C) of fig. 4, the on duty of S1 decreases and the on duty of D4 increases.

In example 1, for a three-phase two-level topology, the injected common-mode voltage only changes the on duty cycles of S1 and D4, and the current of the a phase is not carried by the power semiconductor devices other than S1 and D4.

Fig. 4 is only illustrated with phase a as an example, and the on duty ratio adjustment of phase B and phase C is similar, and is not repeated here.

Fig. 5 is a simulation waveform of two-level inverter modulation wave injection common mode voltage. Fig. 5 shows a schematic diagram of injecting a common mode voltage for a two-level Space Vector Pulse Width Modulation (SVPWM) modulation signal to vary the on-duty of a power semiconductor device. In the graph (a) of fig. 5, at 0 to 0.02s, the inverter three-phase modulation wave is a conventional SVPWM modulation wave, and it can be understood that the injected common-mode signal is zero at this time; at the time of 0.02s, the common-mode voltage signal jumps from 0 to 0.3V, and the three-phase modulation wave moves upwards as a whole. The graph (b) is a schematic diagram of comparing the A-phase bridge arm modulation wave with the triangular carrier wave, and the comparison of the A-phase bridge arm modulation wave and the triangular carrier wave generates a driving signal of the A-phase bridge arm; for an A-phase bridge arm upper tube, when a modulation wave Vca is larger than a triangular carrier wave Vcarr, the upper tube is conducted, and when the modulation wave Vca is smaller than the triangular carrier wave Vcarr, the upper tube is cut off. Fig. c shows the on duty ratio of the a-phase tube significantly changed before and after 0.02s, as a result of comparing the modulated wave with the carrier wave in fig. b.

Example 2

Assume that the inverter circuit employs an NPC three-level topology as shown in fig. 6. If the output current and the output voltage of the inverter circuit are positive when the motor is in locked rotor, the current in the inverter circuit is controlled by S1, S2 and D_p1And (4) carrying.

FIG. 7 shows S1, S2, D_p1Schematic of the on duty cycles of D3 and D4.

When the motor is locked, if the on duty is not adjusted, as shown in fig. 7 (a), the on duty of S1 is small, the on duty of S2 is large, and D is large_p1The on duty is also large, and D3 and D4 do not pass current, so S2 and D4_p1The losses will be relatively large.

If the PWM control device determines S2 and/or D_p1The PWM control means may inject a positive common mode voltage (e.g., V) to the modulated wave if the junction temperature is too high_dc/4) as shown in FIG. 7 (b), D_p1The on duty of S1 is increased, D_p1And S1 to the vicinity of 0.5, S2 is still normally on. Thus, D can be assumed to be S1_p1Part of the current.

If the PWM control device determines S2 and/or D_p1The PWM control means may also inject a negative common mode voltage (e.g., -V) into the modulated wave if the junction temperature is too high_dc/4), as shown in fig. 7 (c), S1 does not pass current, D_p1The on duty ratios of 1 and S2 are decreased, the on duty ratios of D3 and D4 are increased, and D_p1The on duty ratios of S2, D3, and D4 all become around 0.5. Thus, D3 and D4 can bear D _p11. Partial currents of S2 and S1.

Fig. 6 and fig. 7 are only illustrated by taking one phase as an example, and if the inverter circuit further includes more phases, the on duty ratios of other phases are adjusted similarly, and are not described again here.

Example 3

Assume that the inverter circuit employs a T-type three-level topology as shown in fig. 8. If the output current and the output voltage of the inverter circuit are positive when the motor is in locked rotor, the current in the inverter circuit is borne by S1, S3 and D4.

Fig. 9 is a schematic diagram of the on duty ratios of S1, S3, D2, and D4.

When the motor is locked, if the on duty is not adjusted, as shown in fig. 9 (a), the on duty of S1 is small, the duty of S3 and D4 is large, and no current flows through D2, so that the losses of S3 and D4 are large.

If the PWM control means determines that the junction temperature of S3 and/or D4 is too high, the PWM control means may inject a positive common mode voltage (e.g., V) to the modulated wave_dc/4), as shown in fig. 9 (b), the on duty of S3 and D4 decreases, the on duty of S1 increases, the on duty of S1, S3, and D4 becomes close to 0.5, and D2 does not pass current. Thus, part of the currents of S3 and D4 can be borne by S1.

If the PWM control device determines S3 and/or D4, the PWM control means may also inject a negative common mode voltage (e.g., -V) into the modulated wave_dc/4), as shown in the graph (c) of fig. 9, S1 does not pass current, the on duty of S3 and D4 decreases, the on duty of D2 increases, and the on duty of S3, D2, and D4 all become close to 0.5. Thus, part of the currents of S1, S3 and D4 can be borne by D2.

Fig. 8 and fig. 9 are only illustrated by taking one phase as an example, and if the inverter circuit further includes more phases, the on duty ratios of other phases are adjusted similarly, and are not described again here. The PWM control method provided by the present application is described in detail above with reference to fig. 2 to 9, and the device embodiment of the present application will be described in detail below with reference to fig. 10 and 11. It is understood that, in order to implement the functions of the above embodiments, the apparatus in fig. 10 or fig. 11 includes a corresponding hardware structure and/or software module for performing each function. Those of skill in the art will readily appreciate that the various illustrative elements and method steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is performed as hardware or computer software driven hardware depends on the particular application scenario and design constraints imposed on the solution.

Fig. 10 and 11 are schematic structural diagrams of possible devices provided by embodiments of the present application. These means can be used to implement the functions of the PWM control means in the above method embodiments, and therefore can also implement the advantageous effects of the above method embodiments.

As shown in fig. 10, the apparatus 900 includes an acquisition unit 910 and a processing unit 920.

An obtaining unit 910, configured to obtain junction temperatures of N power semiconductor devices in an inverter circuit, where N is an integer greater than 1.

A processing unit 920, configured to inject a common-mode voltage into a modulation wave when junction temperatures of M power semiconductor devices in the N power semiconductor devices are greater than a first threshold, where the modulation wave is used to generate a signal for controlling at least some of the N power semiconductor devices to turn on or off, the common-mode voltage is used to reduce on duty ratios of K power semiconductor devices in the M power semiconductor devices, K is an integer greater than 0 and less than or equal to M, and M is an integer greater than 0 and less than or equal to N.

The processing unit 920 is further configured to send a control signal according to the modulation wave after the common-mode voltage is injected, where the control signal is used to control the at least part of the power semiconductor devices to be turned on or off.

Optionally, the common mode voltage is further used to increase the on duty cycles of P power semiconductor devices, where the P power semiconductor devices belong to power semiconductor devices other than the M power semiconductor devices in the N power semiconductor devices, and P is an integer greater than 0.

Optionally, the processing unit 920 is further configured to: when the junction temperature of M power semiconductor devices in the N power semiconductor devices is larger than the first threshold value and the modulation ratio of the inverter circuit is lower than a second threshold value, injecting the common-mode voltage into the modulation wave; or, when the junction temperature of M power semiconductor devices of the N power semiconductor devices is greater than the first threshold and the output power factor of the inverter circuit is lower than a third threshold, injecting the common mode voltage into the modulated wave; or, when the junction temperature of M power semiconductor devices of the N power semiconductor devices is greater than the first threshold and the output frequency of the inverter circuit is lower than a fourth threshold, the common-mode voltage is injected into the modulated wave.

Optionally, the N power semiconductor devices correspond to N first threshold values one by one, and the junction temperature of each of the M power semiconductor devices is greater than the first threshold value corresponding to the power semiconductor device. In other words, the junction temperatures of the M power semiconductor devices are greater than the first threshold, which can be understood as that the junction temperatures of the M power semiconductor devices are greater than the first threshold corresponding to the power semiconductor devices, respectively. The N first thresholds may be the same or different. For example, the first threshold values of the same type of power semiconductor device may be the same, and the first threshold values of different types or different types of power semiconductor devices may be different.

Optionally, the inverter circuit is a single-phase or multi-phase inverter circuit.

Optionally, the inverter circuit adopts a two-level topology or a multi-level topology.

Optionally, when the inverter circuit adopts an I-type three-level topology or a T-type three-level topology, the amplitude of the common-mode voltage is one fourth of the dc input voltage of the inverter circuit.

More detailed descriptions about the obtaining unit 910 and the processing unit 920 can be directly obtained by referring to the related descriptions in the above method embodiments, which are not repeated herein.

As shown in fig. 11, the apparatus 1000 includes a processor 1010 and an interface circuit 1020. The processor 1010 and the interface circuit 1020 are coupled to each other. It is understood that the interface circuit 1020 may be a transceiver or an input-output interface. Optionally, the apparatus 1000 may further include a memory 1030 for storing instructions to be executed by the processor 1010 or for storing input data required by the processor 1010 to execute the instructions or for storing data generated by the processor 1010 after executing the instructions.

When the apparatus 1000 is configured to implement the method described above, the processor 1010 is configured to implement the functions of the processing unit 920 described above, and the interface circuit 1020 is configured to implement the functions of the obtaining unit 910 described above.

The embodiment of the application also provides a motor controller which comprises any one of the PWM control devices.

The embodiment of the application also provides a chip, and the chip acquires the instruction and executes the instruction to realize the method.

Optionally, as an implementation manner, the chip includes a processor and a data interface, and the processor reads instructions stored on the memory through the data interface to execute the method.

Optionally, as an implementation manner, the chip may further include a memory, where the memory stores instructions, and the processor is configured to execute the instructions stored on the memory, and when the instructions are executed, the processor is configured to execute the method.

An embodiment of the present application further provides an electric drive system, which includes any one of the PWM control apparatuses described above, or includes any one of the motor controllers described above, or includes any one of the chips described above.

The embodiment of the present application further provides a computer-readable storage medium, where the computer-readable storage medium stores instructions for the method in the above method embodiment.

The embodiment of the present application further provides a computer program product containing instructions for implementing the method in the above method embodiment.

It is understood that the processor in the embodiments of the present application may be a Central Processing Unit (CPU), other general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. The general purpose processor may be a microprocessor, but may be any conventional processor.

The memory in embodiments of the present application may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. Volatile memory can be Random Access Memory (RAM), which acts as external cache memory. By way of example, but not limitation, many forms of Random Access Memory (RAM) are available, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct bus RAM (DR RAM).

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

It is to be understood that the various numerical references referred to in the embodiments of the present application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of the present application. The sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of the processes should be determined by their functions and inherent logic.

Unless otherwise defined, all technical and scientific terms used in the examples of this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to limit the scope of the present application. It should be understood that the above examples are for illustrative purposes only and are not intended to limit the claimed embodiments to the particular values or particular scenarios illustrated to assist those skilled in the art in understanding the claimed embodiments. It will be apparent to those skilled in the art from the examples given above that various equivalent modifications or variations can be made, and such modifications and variations also fall within the scope of the embodiments of the present application.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A PWM control method, comprising:

2. The method of claim 1, wherein the common mode voltage is further used to increase the on duty cycles of P power semiconductor devices belonging to the power semiconductor devices of the N power semiconductor devices other than the M power semiconductor devices, P being an integer greater than 0.

3. The method according to claim 1 or 2, wherein the injecting a common mode voltage to the modulated wave when the junction temperature of M of the N power semiconductor devices is greater than a first threshold value comprises:

when the junction temperature of M power semiconductor devices in the N power semiconductor devices is larger than the first threshold value and the modulation ratio of the inverter circuit is lower than a second threshold value, injecting the common-mode voltage into the modulation wave; or,

when the junction temperature of M power semiconductor devices in the N power semiconductor devices is larger than the first threshold value and the output power factor of the inverter circuit is lower than a third threshold value, injecting the common-mode voltage into the modulation wave; or,

and when the junction temperature of M power semiconductor devices in the N power semiconductor devices is greater than the first threshold value and the output frequency of the inverter circuit is lower than a fourth threshold value, injecting the common-mode voltage into the modulation wave.

4. A method according to any one of claims 1 to 3, wherein the N power semiconductor devices correspond one-to-one to the N first threshold values, and wherein the junction temperature of each of the M power semiconductor devices is greater than the first threshold value to which it corresponds.

5. The method according to any one of claims 1 to 4, wherein the inverter circuit is a single-phase or multi-phase inverter circuit.

6. The method of any one of claims 1 to 5, wherein the inverter circuit employs a two-level topology or a multi-level topology.

7. The method according to any one of claims 1 to 6, wherein when the inverter circuit adopts a type I three-level topology or a type T three-level topology, the magnitude of the common mode voltage is one quarter of the DC input voltage of the inverter circuit.

8. A PWM control apparatus, characterized in that the apparatus comprises:

9. The apparatus of claim 8, wherein the common mode voltage is further configured to increase the turn-on duty cycles of P power semiconductor devices belonging to the power semiconductor devices of the N power semiconductor devices other than the M power semiconductor devices, P being an integer greater than 0.

10. The apparatus according to claim 7 or 8, wherein the processing unit is specifically configured to:

11. The apparatus of any of claims 8 to 10, wherein the N power semiconductor devices correspond one-to-one to the N first threshold values, and wherein the junction temperature of each of the M power semiconductor devices is greater than the first threshold value to which the power semiconductor device corresponds.

12. The apparatus of any one of claims 8 to 11, wherein the inverter circuit is a single-phase or multi-phase inverter circuit.

13. The apparatus of any one of claims 8 to 12, wherein the inverter circuit employs a two-level topology or a multi-level topology.

14. The apparatus of claim 13, wherein the magnitude of the common mode voltage is one quarter of a dc input voltage of the inverter circuit when the inverter circuit employs a type I tri-level topology or a type T tri-level topology.

15. A PWM control apparatus, comprising:

a processor to execute computer instructions stored in the memory to cause the apparatus to perform: the method of any one of claims 1 to 7.

16. A motor controller comprising a PWM control apparatus according to any one of claims 8 to 14.

17. A chip comprising a processor coupled to a memory for storing a computer program, the processor being configured to execute the computer program stored in the memory to cause the chip to perform the method of any of claims 1 to 7.

18. An electric drive system comprising a PWM control arrangement according to any one of claims 8 to 14, or comprising a motor controller according to claim 16, or comprising a chip according to claim 17.

19. A computer storage medium, having stored thereon a computer program which, when executed by a computer, causes the computer to carry out the method of any one of claims 1 to 7.