CN113791561A - Satellite electrical performance test signal source based on Ethernet and test signal generation method - Google Patents
Satellite electrical performance test signal source based on Ethernet and test signal generation method Download PDFInfo
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Abstract
A satellite electrical performance test signal source based on Ethernet and a test signal generation method relate to the field of testing of satellite equipment batch production lines. The problems that the transmission rate of test data is low, the output transmission throughput and the data storage capacity are low, and the multi-channel user-defined waveform output with variable requirements cannot be adapted in the whole star-level electric energy comprehensive test process of the conventional PXI signal source board card are solved. The invention adopts a microcontroller MCU, a hundred-mega Ethernet PHY chip and a decoding and isolating circuit to time-share control the N4-channel parallel DACs, wherein the N4-channel parallel DACs share a parallel interface of the microcontroller MCU and are used for transmitting data signals of different channels of each 4-channel parallel DAC in parallel; the decoding part of the decoding and isolating circuit is used for gating and isolating the corresponding 4-channel parallel DAC. The invention is mainly used for generating each path of electric quantity output direct current voltage value and each type of waveform which are customized by the user.
Description
Technical Field
The invention relates to the field of testing of a batch production line of satellite equipment.
Background
For the electrical performance test of the satellite equipment, a dedicated PXI signal source board card is generally connected to a main control module of the whole satellite test system through an internal synchronous RS-485 communication bus. When the whole satellite testing system works, the main control computer sends working parameters to the special PXI signal source board card through the internal RS-485 bus, and the PXI signal source board card outputs various waveforms required by the testing system outwards by using the working parameters, wherein the waveforms comprise direct current signals, sine waves, square waves, triangular waves and the like. With the application of a large number of low-orbit broadband internet satellites in recent years, the functional requirements of subsystem tests and whole-satellite-level comprehensive tests on signal sources are improved, and the traditional PXI signal source board card can not adapt to the requirements of rapid configuration, large-capacity storage of configuration data, user-defined waveform multi-path simultaneous output and the like of the current whole-satellite-level comprehensive tests gradually.
On one hand, a synchronous RS-485 bus is adopted between the traditional special PXI signal source board card and the main control computer for data communication, and data signals of the traditional special PXI signal source board card are transmitted in a differential mode, so that the special PXI signal source board card has certain anti-interference capacity. However, because the half-duplex communication mode is adopted, only one transmitter can transmit data at any time on the bus, and because the highest communication speed is 10Mb/s, the highest speed transmission can be obtained only under an extremely short transmission distance, and the common transmission speed is only 2 Mb/s.
On the other hand, the external storage device on the traditional special PXI signal source board card mostly adopts NorFlash as a data storage device, and simultaneously, a program is directly operated in the NorFlash. When the capacity is small, the cost benefit is high, but the storage capacity is small, and the data throughput performance of the whole board card is greatly influenced by the low writing and erasing speeds.
And the third point is that the traditional special PXI signal source board card mostly adopts the FPGA and a multi-channel serial input DAC controller to output a signal source, before the board card works each time, configuration parameters of the FPGA need to be reloaded through an RS-485 bus, and then a fixed voltage is output for the test of the whole satellite test system. With the increase of the number of test channels and the increase of frequency components of user-defined waveforms, the amplitude span is large, and the low communication rate and the low data throughput of the traditional special PXI signal source board card limit the large application of the board card in the whole star-level comprehensive test.
Therefore, in the three aspects, in the comprehensive test process of the whole-satellite-level electric energy of the low-orbit broadband internet satellite, the traditional special PXI signal source board card needs to make corresponding improvements in the three aspects of the transmission rate, the output transmission throughput and the data storage capacity of test data, the adaptation to the multi-channel user-defined waveform output with variable requirements and the like, so that the user requirements can be better met, and a better guarantee is provided for the whole-satellite environment test and the whole-satellite factory rapid test.
Disclosure of Invention
The invention aims to solve the problems that the transmission rate of test data is low, the output transmission throughput and the data storage capacity are low, and the existing PXI signal source board is not suitable for the output of multi-channel user-defined waveforms (such as simulated overload signals, target parameter preparation completion signals and trigger pulse test signals) with various requirements in the whole-satellite-level electric energy comprehensive test process of the existing PXI signal source board card.
The satellite electrical performance test signal source based on the Ethernet comprises a power supply module, a microcontroller MCU, a decoding and isolating circuit, N4-channel parallel DACs, N high-voltage operational amplifier circuits, a large-capacity memory, a hundred-mega Ethernet PHY chip, a hundred-mega Ethernet transformer and an inter-board connector; the Ethernet transmission unit comprises a first data communication interface, a second data communication interface and an inter-board connector, wherein the first data communication interface is connected with the inter-board connector;
the second data communication interface of the hundred-mega Ethernet transformer is connected with the first data communication interface of the hundred-mega Ethernet PHY chip, and the second data communication interface of the hundred-mega Ethernet PHY chip is connected with the RMII interface of the microcontroller MCU;
the N4-channel parallel DACs are respectively in one-to-one correspondence with the N high-voltage operational amplifier circuits, and N is an integer greater than or equal to 2;
the Ethernet transmission unit is connected with the peripheral equipment through the inter-board connector;
the microcontroller MCU is used for receiving command parameters output by the peripheral equipment through the Ethernet transmission unit and storing the command parameters to the mass storage; the decoding and isolating circuit is also used for parallelly outputting command parameters output by the peripheral equipment and received by the Ethernet transmission unit to the decoding and isolating circuit;
the decoding and isolating circuit is used for decoding the received command parameters, realizing parallel gating of the corresponding 4-channel parallel DAC, isolating the decoded command parameters and then parallelly transmitting the command parameters to the corresponding 4-channel parallel DAC;
the 4-channel parallel DAC is used for performing digital-to-analog conversion on the received isolated command parameters, transmitting the converted command parameters to the high-voltage operational amplifier circuit corresponding to the 4-channel parallel DAC for amplification, and enabling the high-voltage operational amplifier circuit corresponding to the 4-channel parallel DAC to output 4 paths of test signals;
the power supply module receives external given voltage through the inter-board connector;
the power supply module is used for performing voltage conversion on the received external given voltage and then supplying power to the microcontroller MCU, the decoding and isolating circuit, the N4-channel parallel DACs, the N high-voltage operational amplifier circuits, the large-capacity memory, the hundred-mega Ethernet PHY chip and the hundred-mega Ethernet transformer.
Preferably, the decoding and isolation circuit is isolated by magnetic coupling isolation.
Preferably, the high-voltage operational amplifier circuit comprises 4 operational amplifier units, and the 4 operational amplifier units have the same structure;
4 channels of parallel DAC outputs 4 channels of signals;
4 operational amplifier units of the high-voltage operational amplifier circuit respectively process 4 paths of signals output by the 4-channel parallel DAC, and each 4 operational amplifier units outputs 1 path of test signals, so that the high-voltage operational amplifier circuit outputs 4 paths of test signals;
each of the 4 operational amplifier units comprises resistors R1-R5, an amplifier chip U1, a positive power supply V1, a positive power supply V2 and a negative power supply V3; the model number of the amplifier chip U1 is FX 2640;
one end of the resistor R2 is used as the input end of the operational amplifier unit and is used for receiving one path of signals output by the 4-channel parallel DAC;
the other end of the resistor R2 is connected with a pin No. 2 of the amplifier chip U1 and one end of the resistor R4, the other end of the resistor R4 is connected with a pin No. 6 of the amplifier chip U1 and one end of the resistor R5, and the other end of the resistor R5 is connected with a power ground; one end of the resistor R1 is connected with the positive power supply V1, the other end of the resistor R1 is simultaneously connected with the No. 3 pin of the amplifier chip U1 and one end of the resistor R3, and the other end of the resistor R3 is connected with the power ground;
the pin No. 7 of the amplifier chip U1 is connected with a positive power supply V2, and the pin No. 4 of the amplifier chip U1 is connected with a negative power supply V3;
Preferably, the output signal of the operational amplifier unit is VoutWherein, in the step (A),
Vinthe signal is input by the input end of the operational amplifier unit.
Preferably, the positive power supply V1 is 1.25V, the positive power supply V2 is 40V, and the negative power supply V3 is-40V.
Preferably, the 4-channel parallel DAC is of the type JDA 8412.
Preferably, the large-capacity memory is of model GD5F4GQ6 UFYIG.
The method for generating the test signal by using the Ethernet-based satellite electrical performance test signal source comprises the following steps:
s1, after initializing the microcontroller MCU, the hundred mega Ethernet PHY chip and the hundred mega Ethernet transformer, executing the step S2;
s2, command parameters for controlling the 4-channel parallel DAC are prestored in the large-capacity memory, the microcontroller MCU reads the command parameters from the large-capacity memory, decodes the read command parameters through the decoding and isolating circuit, realizes parallel gating of the corresponding 4-channel parallel DAC, isolates the decoded command parameters and sends the command parameters to the corresponding 4-channel parallel DAC in parallel;
after performing digital-to-analog conversion on the received isolated command parameters by the gated corresponding 4-channel parallel DAC, transmitting the converted isolated command parameters to a high-voltage operational amplifier circuit corresponding to the 4-channel parallel DAC for amplification, so that the high-voltage operational amplifier circuit generates a test signal with a corresponding waveform, and then executing S3;
s3, the microcontroller MCU regularly inquires whether the Ethernet transmission unit has new parameter command injection, if so, the step S4 is executed, otherwise, the step S2 is continuously executed;
and S4, storing the newly injected command parameters into a mass storage through the microcontroller MCU, simultaneously, sending the newly injected command parameters to a decoding and isolating circuit through the microcontroller MCU for gating and isolating, and outputting corresponding digital quantity by the gated corresponding 4-channel parallel DAC to change the test signal output by the high-voltage operational amplifier circuit corresponding to the gated corresponding 4-channel, thereby completing the generation of the test signal.
The invention has the following beneficial effects: the satellite electrical performance test signal source based on the Ethernet comprises two working modes, wherein one working mode is that a microcontroller MCU reads command parameters from a large-capacity memory so as to control a corresponding high-voltage operational amplifier circuit to generate test signals, and the other working mode is that the microcontroller MCU receives new command parameters through an Ethernet transmission unit so as to change waveforms of the generated test signals output by the corresponding high-voltage operational amplifier circuit according to the new command parameters.
In the whole process, test signals are generated in two modes, the waveforms of the test signals can be changed in real time to adapt to changeable multi-channel user-defined waveforms, meanwhile, the mode that N4-channel parallel DACs are combined with a microcontroller MCU and a decoding and isolating circuit is adopted, 1 or more 4-channel parallel DACs are gated to perform parallel multi-path output, the transmission rate and the output transmission throughput are improved, and the integral storage capacity of an electrical performance test signal source is improved by combining a large-capacity storage.
The satellite electrical performance test signal source based on the Ethernet has the advantages of high data transmission rate, high output transmission throughput and data storage capacity and good self-defined waveform multi-channel simultaneous output capability, and can meet new technical indexes provided for test signal source equipment in the current whole satellite environment test and whole satellite factory rapid test environments. Meanwhile, the main control device adopted by the invention adopts the MCU, so that the cost is obviously reduced compared with the FPGA. The core devices can be localized by 100%, and various key technologies for realizing autonomous and controllable localization of the signal source equipment are effectively verified.
Drawings
FIG. 1 is a schematic block diagram of an Ethernet-based satellite electrical performance test signal source according to the present invention;
fig. 2 is a schematic diagram of the operational amplifier unit 5-1.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The first embodiment is as follows: the embodiment is described below with reference to fig. 1, and the satellite electrical performance test signal source based on the ethernet in the embodiment includes a power supply module 1, a microcontroller MCU2, a decoding and isolating circuit 3, N4-channel parallel DACs 4, N high-voltage operational amplifier circuits 5, a large-capacity memory 6, a hundred mega ethernet PHY chip 7, a hundred mega ethernet transformer 8, and an inter-board connector 9; the gigabit Ethernet PHY chip 7 and the gigabit Ethernet transformer 8 form an Ethernet transmission unit, and a first data communication interface of the gigabit Ethernet transformer 8 is connected with the inter-board connector 9;
the second data communication interface of the hundred-mega Ethernet transformer 8 is connected with the first data communication interface of the hundred-mega Ethernet PHY chip 7, and the second data communication interface of the hundred-mega Ethernet PHY chip 7 is connected with the RMII interface of the microcontroller MCU 2;
the N4-channel parallel DACs 4 are respectively in one-to-one correspondence with the N high-voltage operational amplifier circuits 5, and N is an integer greater than or equal to 2;
the Ethernet transmission unit is connected with the peripheral equipment through the inter-board connector 9;
the microcontroller MCU2 is used for receiving command parameters output by the peripheral equipment through the Ethernet transmission unit and storing the command parameters into the mass memory 6; the decoding and isolating circuit 3 is also used for parallelly outputting command parameters output by the peripheral equipment and received by the Ethernet transmission unit;
the decoding and isolating circuit 3 is used for decoding the received command parameters, realizing parallel gating of the corresponding 4-channel parallel DAC4, isolating the decoded command parameters and then sending the command parameters to the corresponding 4-channel parallel DAC4 in parallel;
the 4-channel parallel DAC4 is used for performing digital-to-analog conversion on the received isolated command parameters, transmitting the converted command parameters to the high-voltage operational amplifier circuit 5 corresponding to the 4-channel parallel DAC4 for amplification, and enabling the high-voltage operational amplifier circuit 5 corresponding to the 4-channel parallel DAC4 to output 4 paths of test signals;
the power supply module 1 receives an external given voltage through the board-to-board connector 9;
after voltage conversion is performed on the received external given voltage, the power supply module 1 supplies power to the microcontroller MCU2, the decoding and isolating circuit 3, the N4-channel parallel DACs 4, the N high-voltage operational amplifier circuits 5, the large-capacity memory 6, the hundred-mega ethernet PHY chip 7, and the hundred-mega ethernet transformer 8.
In the embodiment, a satellite electrical performance test signal source based on the ethernet is provided, a microcontroller MCU2, a gigabit ethernet PHY chip 7 and a decoding and isolating circuit 3 are adopted to time-share control over N4-channel parallel DACs 4, and the N4-channel parallel DACs 4 share data lines and address lines of a parallel interface of the microcontroller MCU2 and are used for transmitting data signals of different channels of each 4-channel parallel DAC 4; the decoding part in the decoding and isolating circuit 3 is used for gating the corresponding 4-channel parallel DAC4, and the isolating part in the decoding and isolating circuit 3 is used for isolating the command parameters from the signals generated by the high-voltage operational amplifier circuit 5.
The hundred mega ethernet PHY chip 7 is connected to the physical data transmission channel through a hundred mega ethernet transformer 8. A domestic hundred megabyte network isolation transformer may be used to enhance the reliability and environmental suitability of ethernet interface communications.
In specific application, the decoding and isolating circuit 3 is implemented by adopting the prior art, the satellite electrical performance test signal source based on the ethernet according to the embodiment includes two working modes, wherein one working mode is that the microcontroller MCU2 reads command parameters from the mass memory 6 to control the corresponding high-voltage operational amplifier circuit 5 to generate a test signal, and the other working mode is that the microcontroller MCU2 receives new command parameters through the ethernet transmission unit, so that the microcontroller MCU2 changes the waveform of the test signal generated by the corresponding high-voltage operational amplifier circuit 5 according to the new command parameters.
In the whole process, test signals are generated in two modes, the waveforms of the test signals can be changed in real time to adapt to changeable multi-channel user-defined waveforms, meanwhile, N4-channel parallel DACs 4 are adopted to be combined with the microcontroller MCU2 and the decoding and isolating circuit 3, 1 or more 4-channel parallel DACs 4 are gated to perform parallel multi-path output, the transmission rate and the output transmission throughput are improved, and the integral storage capacity of an electrical performance test signal source is improved by combining with the large-capacity storage 6.
In the present embodiment, the optimum value of N is 8, and a memory having a capacity of 2M/4Mbytes or more is generally regarded as a mass memory.
In specific application, the power supply module 1 can receive 12V and 27V voltages input from the outside, convert the 12V voltages into 1.25V, 2.5V, 3.3V and 5V, and convert the 27V voltages into 40V and-40V voltages, wherein 3.3V is used for supplying power to the microcontroller MCU2, the decoding and isolating circuit 3, the mass storage 6, the gigabit ethernet PHY chip 7 and the gigabit ethernet transformer 8, and the 2.5V and 5V are used for supplying power to the 4-channel parallel DAC4, and the 1.25V and ± 40V are used for supplying power to the high-voltage operational amplifier circuit 5.
Furthermore, the decoding and isolation circuit 3 is isolated by magnetic coupling.
In the preferred embodiment, the control interfaces of the MCU and the DAC are isolated by magnetic coupling.
When the magnetic isolation power supply is applied specifically, the power supply can be isolated through the isolation power supply module, and the magnetic coupling isolator can be used for digital isolation, so that the safety and the reliability of module design are ensured.
Further, referring specifically to fig. 2, the high-voltage operational amplifier circuit 5 includes 4 operational amplifier units 5-1, and the 4 operational amplifier units 5-1 have the same structure;
4-channel parallel DAC4 outputs 4-channel signals;
4 operational amplifier units 5-1 of the high-voltage operational amplifier circuit 5 respectively process 4 paths of signals output by the 4-channel parallel DAC4, and each 4 operational amplifier units 5-1 outputs 1 path of test signals, so that the high-voltage operational amplifier circuit 5 outputs 4 paths of test signals;
each of the 4 operational amplifier units 5-1 includes resistors R1 to R5, an amplifier chip U1, a positive power supply V1, a positive power supply V2, and a negative power supply V3; the model number of the amplifier chip U1 is FX 2640;
one end of the resistor R2 is used as an input end of the operational amplifier unit 5-1 and is used for receiving a signal output by the 4-channel parallel DAC 4;
the other end of the resistor R2 is connected with a pin No. 2 of the amplifier chip U1 and one end of the resistor R4, the other end of the resistor R4 is connected with a pin No. 6 of the amplifier chip U1 and one end of the resistor R5, and the other end of the resistor R5 is connected with a power ground; one end of the resistor R1 is connected with the positive power supply V1, the other end of the resistor R1 is simultaneously connected with the No. 3 pin of the amplifier chip U1 and one end of the resistor R3, and the other end of the resistor R3 is connected with the power ground;
the pin No. 7 of the amplifier chip U1 is connected with a positive power supply V2, and the pin No. 4 of the amplifier chip U1 is connected with a negative power supply V3;
In the preferred embodiment, the high-voltage operational amplifier circuit 5 amplifies the 4-channel signal output from the 4-channel parallel DAC4 as the final output signal of the signal source. The amplifier chip U1 is FX2640, and the operational amplifier is a high-voltage operational amplifier with broadband working power supply voltage and has the characteristics of high power supply voltage and high output current.
Further, the positive power supply V1 was 1.25V, the positive power supply V2 was 40V, and the negative power supply V3 was-40V.
Furthermore, the output end of the operational amplifier unit 5-1 outputs a signal VoutWherein, in the step (A),
Vinis a signal input by the input end of the operational amplifier unit 5-1.
Further, the 4-channel parallel DAC4 is model JDA 8412.
In the preferred embodiment, the quantization accuracy of the 4-channel parallel DAC4 is 12 bits, and the output voltage accuracy is better than ± 0.2% FS.
Further, the large-capacity memory 6 is of a model GD5F4GQ6 UFYIG.
In the preferred embodiment, the mass storage model: GD5F4GQ6UFYIG, this type memory is NandFlash, the memory space is 512 Mbytes.
The second embodiment is as follows: the present embodiment is described below with reference to fig. 1, and a method for generating a test signal by using a satellite electrical performance test signal source based on ethernet according to a first embodiment includes the following steps:
s1, initializing the microcontroller MCU2, the hundred-mega Ethernet PHY chip 7 and the hundred-mega Ethernet transformer 8, and then executing the step S2;
s2, command parameters for controlling the 4-channel parallel DAC4 are prestored in the large-capacity storage 6, the microcontroller MCU2 reads the command parameters from the large-capacity storage 6 and decodes the read command parameters through the decoding and isolating circuit 3 to realize parallel gating of the corresponding 4-channel parallel DAC4, and then isolates the decoded command parameters and sends the command parameters to the corresponding 4-channel parallel DAC4 in parallel;
after performing digital-to-analog conversion on the received isolated command parameters by the gated corresponding 4-channel parallel DAC4, sending the converted isolated command parameters to the high-voltage operational amplifier circuit 5 corresponding to the 4-channel parallel DAC4 for amplification, so that the high-voltage operational amplifier circuit 5 generates a test signal with a corresponding waveform, and then executing S3;
s3, the microcontroller MCU2 periodically inquires whether the Ethernet transmission unit has a new parameter command injection, if so, the step S4 is executed, otherwise, the step S2 is continuously executed;
s4, storing the newly injected command parameters into the mass memory 6 through the microcontroller MCU2, and simultaneously sending the newly injected command parameters to the decoding and isolating circuit 3 through the microcontroller MCU2 for gating and isolating, and then outputting corresponding digital quantity by the gated corresponding 4-channel parallel DAC4 to change the test signal output by the high-voltage operational amplifier circuit 5 corresponding to the gated corresponding 4-channel, thereby completing the generation of the test signal.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that features described in different dependent claims and herein may be combined in ways different from those described in the original claims. It is also to be understood that features described in connection with individual embodiments may be used in other described embodiments.
Claims (8)
1. The satellite electrical performance test signal source based on the Ethernet is characterized by comprising a power supply module (1), a microcontroller MCU (2), a decoding and isolating circuit (3), N4-channel parallel DACs (4), N high-voltage operational amplifier circuits (5), a large-capacity memory (6), a hundred-mega Ethernet PHY chip (7), a hundred-mega Ethernet transformer (8) and an inter-board connector (9); the Ethernet transmission unit comprises a one hundred mega Ethernet PHY chip (7) and a one hundred mega Ethernet transformer (8), wherein a first data communication interface of the one hundred mega Ethernet transformer (8) is connected with an inter-board connector (9);
a second data communication interface of the hundred-mega Ethernet transformer (8) is connected with a first data communication interface of the hundred-mega Ethernet PHY chip (7), and a second data communication interface of the hundred-mega Ethernet PHY chip (7) is connected with an RMII interface of the microcontroller MCU (2);
n4-channel parallel DACs (4) are respectively in one-to-one correspondence with N high-voltage operational amplifier circuits (5), wherein N is an integer greater than or equal to 2;
the Ethernet transmission unit is connected with the peripheral equipment through an inter-board connector (9);
the microcontroller MCU (2) is used for receiving command parameters output by peripheral equipment through the Ethernet transmission unit and storing the command parameters into the mass memory (6); the decoding and isolating circuit (3) is also used for parallelly outputting command parameters output by the peripheral equipment and received by the Ethernet transmission unit;
the decoding and isolating circuit (3) is used for decoding the received command parameters, realizing the parallel gating of the corresponding 4-channel parallel DAC (4), isolating the decoded command parameters and then sending the command parameters to the corresponding 4-channel parallel DAC (4) in parallel;
the 4-channel parallel DAC (4) is used for carrying out digital-to-analog conversion on the received isolated command parameters, transmitting the converted command parameters to the high-voltage operational amplifier circuit (5) corresponding to the 4-channel parallel DAC (4) for amplification, and enabling the high-voltage operational amplifier circuit (5) corresponding to the 4-channel parallel DAC (4) to output 4 paths of test signals;
the power supply module (1) receives external given voltage through the inter-board connector (9);
the power supply module (1) performs voltage conversion on the received external given voltage and then supplies power to the microcontroller MCU (2), the decoding and isolating circuit (3), the N4-channel parallel DACs (4), the N high-voltage operational amplifier circuits (5), the large-capacity memory (6), the hundred-mega Ethernet PHY chip (7) and the hundred-mega Ethernet transformer (8).
2. The signal source for testing electrical performance of an ethernet-based satellite according to claim 1, wherein the decoding and isolating circuit (3) is isolated by magnetic coupling isolation.
3. The Ethernet-based satellite electrical performance test signal source of claim 1, wherein the high-voltage operational amplifier circuit (5) comprises 4 operational amplifier units (5-1), and the 4 operational amplifier units (5-1) have the same structure;
4 channels of parallel DAC (4) outputs 4 channels of signals;
4 operational amplifier units (5-1) of the high-voltage operational amplifier circuit (5) respectively process 4 paths of signals output by the 4-channel parallel DAC (4), and each 4 operational amplifier units (5-1) outputs 1 path of test signals, so that the high-voltage operational amplifier circuit (5) outputs 4 paths of test signals;
each of the 4 operational amplifier units (5-1) comprises resistors R1-R5, an amplifier chip U1, a positive power supply V1, a positive power supply V2 and a negative power supply V3; the model number of the amplifier chip U1 is FX 2640;
one end of the resistor R2 is used as the input end of the operational amplifier unit (5-1) and is used for receiving one path of signals output by the 4-channel parallel DAC (4);
the other end of the resistor R2 is connected with a pin No. 2 of the amplifier chip U1 and one end of the resistor R4, the other end of the resistor R4 is connected with a pin No. 6 of the amplifier chip U1 and one end of the resistor R5, and the other end of the resistor R5 is connected with a power ground; one end of the resistor R1 is connected with the positive power supply V1, the other end of the resistor R1 is simultaneously connected with the No. 3 pin of the amplifier chip U1 and one end of the resistor R3, and the other end of the resistor R3 is connected with the power ground;
the pin No. 7 of the amplifier chip U1 is connected with a positive power supply V2, and the pin No. 4 of the amplifier chip U1 is connected with a negative power supply V3;
and the No. 6 pin of the amplifier chip U1 is used as the output end of the operational amplifier unit (5-1).
4. The signal source for testing the electrical performance of the Ethernet-based satellite according to claim 3, wherein the signal output by the output terminal of the operational amplifier unit (5-1) is VoutWherein, in the step (A),
Vinto transportThe input end of the amplifying unit (5-1) inputs signals.
5. The signal source of claim 1, wherein the positive power supply V1 is 1.25V, the positive power supply V2 is 40V, and the negative power supply V3 is-40V.
6. The ethernet-based satellite electrical performance test signal source of claim 1, wherein the 4-channel parallel DAC (4) is of the type JDA 8412.
7. The Ethernet-based satellite electrical performance test signal source of claim 1, wherein the mass storage device (6) is of a type GD5F4GQ6 UFYIG.
8. The method for generating a test signal using an ethernet-based satellite electrical performance test signal source of claim 1, the method comprising the steps of:
s1, after the microcontroller MCU (2), the hundred-mega Ethernet PHY chip (7) and the hundred-mega Ethernet transformer (8) are initialized, executing the step S2;
s2, command parameters for controlling the 4-channel parallel DAC (4) are prestored in the mass memory (6), the microcontroller MCU (2) reads the command parameters from the mass memory (6), and decodes the read command parameters through the decoding and isolating circuit (3) to realize parallel gating of the corresponding 4-channel parallel DAC (4), and then isolates the decoded command parameters and sends the command parameters to the corresponding 4-channel parallel DAC (4) in parallel;
after carrying out digital-to-analog conversion on the received isolated command parameters by the corresponding gated 4-channel parallel DAC (4), sending the converted isolated command parameters to a high-voltage operational amplifier circuit (5) corresponding to the 4-channel parallel DAC (4) for amplification, so that the high-voltage operational amplifier circuit (5) generates a test signal with a corresponding waveform, and then executing S3;
s3, the microcontroller MCU (2) periodically inquires whether the Ethernet transmission unit has new parameter command injection, if so, the step S4 is executed, otherwise, the step S2 is continuously executed;
s4, storing the newly injected command parameters into a mass storage (6) through the microcontroller MCU (2), and simultaneously sending the newly injected command parameters to the decoding and isolating circuit (3) through the microcontroller MCU (2) for gating and isolating, and then outputting corresponding digital quantity by the gated corresponding 4-channel parallel DAC (4) to change the test signal output by the high-voltage operational amplifier circuit (5) corresponding to the gated corresponding 4-channel, thereby completing the generation of the test signal.
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